Lines Matching full:fifo

22 #define AACI_RXCR	0x000	/* 29 bits Control Rx FIFO */
23 #define AACI_TXCR	0x004	/* 17 bits Control Tx FIFO */
44 #define AACI_ALLINTS	0x084	/* all fifo interrupt status */
46 #define AACI_DR1	0x090	/* data read/written fifo 1 */
47 #define AACI_DR2	0x0b0	/* data read/written fifo 2 */
48 #define AACI_DR3	0x0d0	/* data read/written fifo 3 */
49 #define AACI_DR4	0x0f0	/* data read/written fifo 4 */
52  * TX/RX fifo control register (CR). P48
54 #define CR_FEN		(1 << 16)	/* fifo enable */
77 #define SR_RXTOFE	(1 << 11)	/* rx timeout fifo empty */
78 #define SR_TXTO		(1 << 10)	/* rx timeout fifo nonempty */
83 #define SR_TXFF		(1 << 5)	/* tx fifo full */
84 #define SR_RXFF		(1 << 4)	/* rx fifo full */
85 #define SR_TXHE		(1 << 3)	/* tx fifo half empty */
86 #define SR_RXHF		(1 << 2)	/* rx fifo half full */
87 #define SR_TXFE		(1 << 1)	/* tx fifo empty */
88 #define SR_RXFE		(1 << 0)	/* rx fifo empty */
93 #define ISR_RXTOFEINTR	(1 << 6)	/* rx fifo empty */
96 #define ISR_RXINTR	(1 << 3)	/* rx fifo */
97 #define ISR_TXINTR	(1 << 2)	/* tx fifo intr */
115 #define ISR_RXTOFE	(1 << 6)	/* rx timeout fifo empty */
116 #define ISR_UR		(1 << 5)	/* tx fifo underrun */
117 #define ISR_OR		(1 << 4)	/* rx fifo overrun */
126 #define IE_RXTOFE	(1 << 6)	/* rx timeout fifo empty */
127 #define IE_UR		(1 << 5)	/* tx fifo underrun */
128 #define IE_OR		(1 << 4)	/* rx fifo overrun */
204 	void			__iomem *fifo;  member