Lines Matching +full:clock +full:- +full:output +full:- +full:names
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
35 #include <sound/pcm-indirect.h>
42 /* ------------------- DEFINES -------------------- */
53 /* FIXME? - according to the OSS driver the EMU10K1 needs a 29 bit DMA mask */
55 #define AUDIGY_DMA_MASK 0x7fffffffUL /* 31bit FIXME - 32 should work? */
56 /* See ALSA bug #1276 - rlrevell */
72 #define PTR_CHANNELNUM_MASK 0x0000003f /* For each per-channel register, indicates the */
74 /* accessed. For non per-channel registers the */
110 #define IPR_CDROMSTATUSCHANGE 0x00000400 /* CD-ROM channel status change */
123 #define INTE_VIRTUALSB_220 0x00000000 /* Capture at I/O base address 0x220-0x22f */
128 #define INTE_VIRTUALMPU_300 0x00000000 /* Capture at I/O base address 0x300-0x301 */
132 #define INTE_MASTERDMAENABLE 0x08000000 /* Master DMA emulation at 0x000-0x00f */
133 #define INTE_SLAVEDMAENABLE 0x04000000 /* Slave DMA emulation at 0x0c0-0x0df */
134 #define INTE_MASTERPICENABLE 0x02000000 /* Master PIC emulation at 0x020-0x021 */
135 #define INTE_SLAVEPICENABLE 0x01000000 /* Slave PIC emulation at 0x0a0-0x0a1 */
137 #define INTE_ADLIBENABLE 0x00400000 /* Enable AdLib emulation at 0x388-0x38b */
148 #define INTE_A_MIDITXENABLE2 0x00020000 /* Enable MIDI transmit-buffer-empty interrupts */
149 #define INTE_A_MIDIRXENABLE2 0x00010000 /* Enable MIDI receive-buffer-empty interrupts */
165 #define INTE_MIDITXENABLE 0x00000002 /* Enable MIDI transmit-buffer-empty interrupts */
166 #define INTE_MIDIRXENABLE 0x00000001 /* Enable MIDI receive-buffer-empty interrupts */
168 #define WC 0x10 /* Wall Clock register */
200 #define HCFG_CODECFORMAT_AC97_1 0x00000000 /* AC97 CODEC format -- Ver 1.03 */
201 #define HCFG_CODECFORMAT_AC97_2 0x00010000 /* AC97 CODEC format -- Ver 2.1 */
203 /* will automatically mute their output when */
204 /* they are not rate-locked to the external */
207 /* will automatically mute their output when */
208 /* the SPDIF V-bit indicates invalid audio */
223 #define HCFG_CODECFORMAT_AC97 0x00000000 /* AC97 CODEC format -- Primary Output */
224 #define HCFG_CODECFORMAT_I2S 0x00010000 /* I2S CODEC format -- Secondary (Rear) Output */
235 #define HCFG_AC3ENABLE_MASK 0x000000e0 /* AC3 async input control - Not implemented */
240 /* will automatically mute their output when */
241 /* they are not rate-locked to the external */
254 #define HCFG_AUDIOENABLE 0x00000001 /* 0 = CODECs transmit zero-valued samples */
258 //For Audigy, MPU port move to 0x70-0x74 ptr register
275 // Audigy output/GPIO stuff taken from the kX drivers
281 #define A_IOCFG_DISABLE_AC97_FRONT 0x0080 /* turn off ac97 front -> front (10k2.1) */
308 #define AC97ADDRESS_READY 0x80 /* Read-only bit, reflects CODEC READY signal */
334 /* 0x00000000 2-channel output. */
335 /* 0x00000200 8-channel output. */
337 /* Rest of bits no nothing to sound output */
342 * bit 8: Record 8-channel in phase.
343 * bit 9: Playback 8-channel in phase.
344 * bit 11-12: Playback mixer attenuation: 0=0dB, 1=-6dB, 2=-12dB, 3=Mute.
346 * bit 14: Route SRC48 mixer output to fx engine.
364 /* When writing, any write causes JOYSTICK_COMPARATOR output enable to be pulsed on write. */
371 /* Emu10k1 pointer-offset register set, accessed through the PTR and DATA registers */
384 #define PTRX_FXSENDAMOUNT_A_MASK 0x0000ff00 /* Linear level of channel output sent to FX send bus A…
386 #define PTRX_FXSENDAMOUNT_B_MASK 0x000000ff /* Linear level of channel output sent to FX send bus B…
406 #define PSST_FXSENDAMOUNT_C_MASK 0xff000000 /* Linear level of channel output sent to FX send bus C…
414 #define DSL_FXSENDAMOUNT_D_MASK 0xff000000 /* Linear level of channel output sent to FX send bus D …
437 #define CCCA_8BITSELECT 0x01000000 /* 1 = Sound memory for this channel uses 8-bit samples */
480 /* 0x8000-n == 666*n usec delay */
484 #define ATKHLDV_HOLDTIME_MASK 0x00007f00 /* Envelope hold time (127-n == n*88.2msec) */
499 /* 0x8000-n == 666*n usec delay */
503 /* 0x8000-n == 666*n usec delay */
507 #define ATKHLDM_HOLDTIME 0x00007f00 /* Envelope hold time (127-n == n*42msec) */
519 /* 0x8000-n == 666*n usec delay */
537 /* Signed 2's complement, +/- one octave peak extremes */
540 /* Signed 2's complement, +/- six octaves peak extremes */
544 /* Signed 2's complement, +/- one octave extremes */
546 /* Signed 2's complement, +/- three octave extremes */
551 /* Signed 2's complement, with +/- 12dB extremes */
557 /* Signed 2's complement, +/- one octave extremes */
562 #define TEMPENV_MASK 0x0000ffff /* 16-bit value */
585 /* 0x30-3f seem to be the same as 0x20-2f */
601 #define A_ADCCR_SAMPLERATE_MASK 0x0000000F /* Audigy sample rate convertor output rate */
602 #define ADCCR_SAMPLERATE_MASK 0x00000007 /* Sample rate convertor output rate */
615 #define FXWC 0x43 /* FX output write channels register */
617 /* corresponding FX output channel (internal registers */
618 /* 0x20-0x3f) to host memory. This mode of recording */
658 #define A_HWM 0x48 /* High PCI Water Mark - word access, defaults to 3f */
666 /* register: 0x4c..4f: ffff-ffff current amounts, per-channel */
715 #define CDCS 0x50 /* CD-ROM digital channel status register */
733 // NOTE: 0x54,55,56: 64-bit
734 #define SPCS0 0x54 /* SPDIF output Channel Status 0 register */
736 #define SPCS1 0x55 /* SPDIF output Channel Status 1 register */
738 #define SPCS2 0x56 /* SPDIF output Channel Status 2 register */
740 #define SPCS_CLKACCYMASK 0x30000000 /* Clock accuracy */
754 #define SPCS_GENERATIONSTATUS 0x00008000 /* Originality flag (see IEC-958 spec) */
755 #define SPCS_CATEGORYCODEMASK 0x00007f00 /* Category code (see IEC-958 spec) */
756 #define SPCS_MODEMASK 0x000000c0 /* Mode (see IEC-958 spec) */
760 #define SPCS_COPYRIGHT 0x00000004 /* Copyright asserted flag -- do not modify */
762 #define SPCS_PROFESSIONAL 0x00000001 /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992) */
766 /* The 32-bit CLIx and SOLx registers all have one bit per channel control/status */
782 /* bypass mode: 0 - DSP; 1 - SPDIF A, 2 - SPDIF B, 3 - SPDIF C */
783 #define SPBYPASS_FORMAT 0x00000f00 /* If 1, SPDIF XX uses 24 bit, if 0 - 20 bit */
794 // NOTE: 0x60,61,62: 64-bit
795 #define CDSRCS 0x60 /* CD-ROM Sample Rate Converter status register */
809 /* Note that these values can vary +/- by a small amount */
815 #define MICIDX_MASK 0x0000ffff /* 16-bit value */
829 #define FXIDX_MASK 0x0000ffff /* 16-bit value */
832 /* The 32-bit HLIx and HLIPx registers all have one bit per channel control/status */
865 /* the Audigy can record any output (16bit, 48kHz, up to 64 channel simultaneously) */
867 #define A_FXWC1 0x74 /* Selects 0x7f-0x60 for FX recording */
868 #define A_FXWC2 0x75 /* Selects 0x9f-0x80 for FX recording */
871 #define A_SPDIF_SAMPLERATE 0x76 /* Set the sample rate of SPDIF output */
901 /* - default to 0x01080000 on my audigy 2 ZS --rlrevell */
933 #define A_TANKMEMCTLREGBASE 0x100 /* Tank memory control registers base - only for Audigy */
934 #define A_TANKMEMCTLREG_MASK 0x1f /* only 5 bits used - only for Audigy */
978 #define EMU_HANA_WCLOCK 0x05 /* 0000xxx 3 bits Word Clock source select */
996 #define EMU_HANA_DEFCLOCK 0x06 /* 000000x 1 bits Default Word Clock */
1085 /* 0x14 - 0x1f Unused R/W registers */
1112 #define EMU_HANA_WC_SPDIF_HI 0x28 /* 0xxxxxx 6 bit SPDIF IN Word clock, upper 6 bits */
1113 #define EMU_HANA_WC_SPDIF_LO 0x29 /* 0xxxxxx 6 bit SPDIF IN Word clock, lower 6 bits */
1115 #define EMU_HANA_WC_ADAT_HI 0x2a /* 0xxxxxx 6 bit ADAT IN Word clock, upper 6 bits */
1116 #define EMU_HANA_WC_ADAT_LO 0x2b /* 0xxxxxx 6 bit ADAT IN Word clock, lower 6 bits */
1118 #define EMU_HANA_WC_BNC_LO 0x2c /* 0xxxxxx 6 bit BNC IN Word clock, lower 6 bits */
1119 #define EMU_HANA_WC_BNC_HI 0x2d /* 0xxxxxx 6 bit BNC IN Word clock, upper 6 bits */
1121 #define EMU_HANA2_WC_SPDIF_HI 0x2e /* 0xxxxxx 6 bit HANA2 SPDIF IN Word clock, upper 6 bits */
1122 #define EMU_HANA2_WC_SPDIF_LO 0x2f /* 0xxxxxx 6 bit HANA2 SPDIF IN Word clock, lower 6 bits */
1123 /* 0x30 - 0x3f Unused Read only registers */
1130 * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2
1131 * 0x01, 0x10-0x1f: 32 Elink channels to Audio Dock
1148 * 0x04, 0x00-0x07: Hana ADAT
1161 * 0x00, 0x00-0x0f: 16 EMU32A channels to Tina
1162 * 0x01, 0x10-0x1f: 32 EDI channels to Micro Dock
1171 * 0x01, 0x18-0x1f: Dock ADAT 0-7
1176 * 0x04, 0x00-0x07: Hana3 ADAT 0-7
1177 * 0x05, 0x00-0x0f: 16 EMU32B channels to Tina
1178 * 0x06-0x07: Not used
1182 * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2
1188 * 0x04-0x07: Not used
1192 * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2
1198 * 0x04-0x07: Not used
1202 * 0x00, 0x00-0x0f: 16 EMU32A channels to Tina2
1203 * 0x01, 0x10-0x1f: 32 EDI channels to Micro Dock
1212 * 0x01, 0x18-0x1f: Dock ADAT 0-7
1216 * 0x04, 0x00-0x0f: 16 EMU32B channels to Tina2
1217 * 0x05-0x07: Not used
1221 /* 32-bit destinations of signal in the Hana FPGA. Destinations are either
1223 * - 16 x EMU_DST_ALICE2_EMU32_X.
1225 /* EMU32 = 32-bit serial channel between Alice2 (audigy) and Hana (FPGA) */
1226 /* EMU_DST_ALICE2_EMU32_X - data channels from Hana to Alice2 used for capture.
1228 * setup of mixer control for each destination - see emumixer.c -
1329 * 0x00,0x00-0x1f: Silence
1330 * 0x01, 0x10-0x1f: 32 Elink channels from Audio Dock
1341 * 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu32A output
1342 * 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu32B output
1343 * 0x04, 0x00-0x07: Hana ADAT
1346 * 0x06-0x07: Not used
1353 * 0x00,0x00-0x1f: Silence
1354 * 0x01, 0x10-0x1f: 32 Elink channels from Audio Dock
1363 * 0x01, 0x18-0x1f: Dock ADAT 0-7
1368 * 0x03, 0x00-0x0f: 16 inputs from Tina Emu32A output
1369 * 0x03, 0x10-0x1f: 16 inputs from Tina Emu32B output
1370 * 0x04, 0x00-0x07: Hana3 ADAT
1373 * 0x06-0x07: Not used
1377 * 0x00,0x00-0x1f: Silence
1381 * 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu32A output
1382 * 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu32B output
1386 * 0x06-0x07: Not used
1390 * 0x00,0x00-0x1f: Silence
1394 * 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu32A output
1395 * 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu32B output
1399 * 0x06-0x07: Not used
1403 * 0x00,0x00-0x1f: Silence
1404 * 0x01, 0x10-0x1f: 32 Elink channels from Audio Dock
1413 * 0x01, 0x18-0x1f: Dock ADAT 0-7
1417 * 0x03, 0x00-0x0f: 16 inputs from Tina Emu32A output
1418 * 0x03, 0x10-0x1f: 16 inputs from Tina Emu32B output
1419 * 0x04-0x07: Not used
1423 /* 32-bit sources of signal in the Hana FPGA. The sources are routed to
1424 * destinations using mixer control for each destination - see emumixer.c
1426 * or outputs from Alice (audigy) - 16 x EMU_SRC_ALICE_EMU32A +
1492 /* ------------------- STRUCTURES -------------------- */
1572 …efine snd_emu10k1_memblk_offset(blk) (((blk)->mapped_page << PAGE_SHIFT) | ((blk)->mem.offset & (P…
1601 unsigned int channels; /* 16-bit channels count */
1670 unsigned char sblive51; /* SBLive! 5.1 - extout 0x11 -> center, 0x12 -> lfe */
1681 const char *id; /* for backward compatibility - can be NULL if not needed */
1854 static inline unsigned int snd_emu10k1_wc(struct snd_emu10k1 *emu) { return (inl(emu->port + WC) >>… in snd_emu10k1_wc()
1905 * ---- FX8010 ----
1915 #define iMAC1 0x01 /* R = A + (-X * Y >> 31) ; saturation */
1917 #define iMAC3 0x03 /* R = A + (-X * Y >> 31) ; wraparound */
1919 #define iMACINT1 0x05 /* R = A + X * Y ; wraparound (31-bit) */
1928 #define iINTERP 0x0e /* R = A + (X * (Y - A) >> 31) ; saturation */
1932 #define FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x0f */
1933 #define EXTIN(x) (0x10 + (x)) /* x = 0x00 - 0x0f */
1934 #define EXTOUT(x) (0x20 + (x)) /* x = 0x00 - 0x0f physical outs -> FXWC low 16 bits */
1935 #define FXBUS2(x) (0x30 + (x)) /* x = 0x00 - 0x0f copies of fx buses for capture -> FXWC high 16 bi…
1966 #define GPR(x) (FXGPREGBASE + (x)) /* free GPRs: x = 0x00 - 0xff */
1967 #define ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */
1968 #define ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */
1969 #define ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */
1970 #define ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */
1972 #define A_ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
1973 #define A_ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
1974 #define A_ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
1975 #define A_ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
1976 #define A_ITRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
1977 #define A_ETRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
1979 #define A_FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x3f FX buses */
1980 #define A_EXTIN(x) (0x40 + (x)) /* x = 0x00 - 0x0f physical ins */
1981 #define A_P16VIN(x) (0x50 + (x)) /* x = 0x00 - 0x0f p16v ins (A2 only) "EMU32 inputs" */
1982 #define A_EXTOUT(x) (0x60 + (x)) /* x = 0x00 - 0x1f physical outs -> A_FXWC1 0x79-7f unknown */
1983 #define A_FXBUS2(x) (0x80 + (x)) /* x = 0x00 - 0x1f extra outs used for EFX capture -> A_FXWC2 */
1984 #define A_EMU32OUTH(x) (0xa0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_10 - _1F" - ??? */
1985 #define A_EMU32OUTL(x) (0xb0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_1 - _F" - ??? */
1986 #define A3_EMU32IN(x) (0x160 + (x)) /* x = 0x00 - 0x3f "EMU32_IN_00 - _3F" - Only when .device = 0x…
1987 #define A3_EMU32OUT(x) (0x1E0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_00 - _3F" - Only when .device = …
2017 #define EXTIN_AC97_L 0x00 /* AC'97 capture channel - left */
2018 #define EXTIN_AC97_R 0x01 /* AC'97 capture channel - right */
2019 #define EXTIN_SPDIF_CD_L 0x02 /* internal S/PDIF CD - onboard - left */
2020 #define EXTIN_SPDIF_CD_R 0x03 /* internal S/PDIF CD - onboard - right */
2021 #define EXTIN_ZOOM_L 0x04 /* Zoom Video I2S - left */
2022 #define EXTIN_ZOOM_R 0x05 /* Zoom Video I2S - right */
2023 #define EXTIN_TOSLINK_L 0x06 /* LiveDrive - TOSLink Optical - left */
2024 #define EXTIN_TOSLINK_R 0x07 /* LiveDrive - TOSLink Optical - right */
2025 #define EXTIN_LINE1_L 0x08 /* LiveDrive - Line/Mic 1 - left */
2026 #define EXTIN_LINE1_R 0x09 /* LiveDrive - Line/Mic 1 - right */
2027 #define EXTIN_COAX_SPDIF_L 0x0a /* LiveDrive - Coaxial S/PDIF - left */
2028 #define EXTIN_COAX_SPDIF_R 0x0b /* LiveDrive - Coaxial S/PDIF - right */
2029 #define EXTIN_LINE2_L 0x0c /* LiveDrive - Line/Mic 2 - left */
2030 #define EXTIN_LINE2_R 0x0d /* LiveDrive - Line/Mic 2 - right */
2033 #define EXTOUT_AC97_L 0x00 /* AC'97 playback channel - left */
2034 #define EXTOUT_AC97_R 0x01 /* AC'97 playback channel - right */
2035 #define EXTOUT_TOSLINK_L 0x02 /* LiveDrive - TOSLink Optical - left */
2036 #define EXTOUT_TOSLINK_R 0x03 /* LiveDrive - TOSLink Optical - right */
2037 #define EXTOUT_AC97_CENTER 0x04 /* SB Live 5.1 - center */
2038 #define EXTOUT_AC97_LFE 0x05 /* SB Live 5.1 - LFE */
2039 #define EXTOUT_HEADPHONE_L 0x06 /* LiveDrive - Headphone - left */
2040 #define EXTOUT_HEADPHONE_R 0x07 /* LiveDrive - Headphone - right */
2041 #define EXTOUT_REAR_L 0x08 /* Rear channel - left */
2042 #define EXTOUT_REAR_R 0x09 /* Rear channel - right */
2043 #define EXTOUT_ADC_CAP_L 0x0a /* ADC Capture buffer - left */
2044 #define EXTOUT_ADC_CAP_R 0x0b /* ADC Capture buffer - right */
2046 #define EXTOUT_AC97_REAR_L 0x0d /* SB Live 5.1 (c) 2003 - Rear Left */
2047 #define EXTOUT_AC97_REAR_R 0x0e /* SB Live 5.1 (c) 2003 - Rear Right */
2052 #define A_EXTIN_AC97_L 0x00 /* AC'97 capture channel - left */
2053 #define A_EXTIN_AC97_R 0x01 /* AC'97 capture channel - right */
2056 #define A_EXTIN_OPT_SPDIF_L 0x04 /* audigy drive Optical SPDIF - left */
2058 #define A_EXTIN_LINE2_L 0x08 /* audigy drive line2/mic2 - left */
2060 #define A_EXTIN_ADC_L 0x0a /* Philips ADC - left */
2062 #define A_EXTIN_AUX2_L 0x0c /* audigy drive aux2 - left */
2063 #define A_EXTIN_AUX2_R 0x0d /* - right */
2078 #define A_EXTOUT_ASIDE_L 0x0c /* analog side left - Audigy 2 ZS */
2079 #define A_EXTOUT_ASIDE_R 0x0d /* right - Audigy 2 ZS */
2116 #define A_GPR_DBAC 0xdb /* TRAM Delay Base Address Counter - internal */
2117 #define A_GPR_DBACE 0xde /* TRAM Delay Base Address Counter - external */
2140 char fxbus_names[16][32]; /* names of FXBUSes */
2141 char extin_names[16][32]; /* names of external inputs */
2142 char extout_names[32][32]; /* names of external outputs */
2197 __u32 __user *code; /* one instruction - 64 bits */
2201 unsigned int address; /* 31.bit == 1 -> external TRAM */
2203 unsigned int *samples; /* pointer to samples (20-bit) */
2204 /* NULL->clear memory */
2210 unsigned int channels; /* 16-bit channels count, zero = remove this substream */
2241 /* typedefs for compatibility to user-space */