Lines Matching defs:mlx4_caps
235 struct mlx4_caps { struct
236 u64 fw_ver;
237 u32 function;
238 int num_ports;
239 int vl_cap[MLX4_MAX_PORTS + 1];
240 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
241 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
242 u64 def_mac[MLX4_MAX_PORTS + 1];
243 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
244 int gid_table_len[MLX4_MAX_PORTS + 1];
245 int pkey_table_len[MLX4_MAX_PORTS + 1];
246 int trans_type[MLX4_MAX_PORTS + 1];
247 int vendor_oui[MLX4_MAX_PORTS + 1];
248 int wavelength[MLX4_MAX_PORTS + 1];
249 u64 trans_code[MLX4_MAX_PORTS + 1];
250 int local_ca_ack_delay;
251 int num_uars;
252 u32 uar_page_size;
253 int bf_reg_size;
254 int bf_regs_per_page;
255 int max_sq_sg;
256 int max_rq_sg;
257 int num_qps;
258 int max_wqes;
259 int max_sq_desc_sz;
260 int max_rq_desc_sz;
261 int max_qp_init_rdma;
262 int max_qp_dest_rdma;
263 int sqp_start;
264 int num_srqs;
265 int max_srq_wqes;
266 int max_srq_sge;
267 int reserved_srqs;
268 int num_cqs;
269 int max_cqes;
270 int reserved_cqs;
271 int num_eqs;
272 int reserved_eqs;
273 int num_comp_vectors;
274 int comp_pool;
275 int num_mpts;
276 int num_mtts;
277 int fmr_reserved_mtts;
278 int reserved_mtts;
279 int reserved_mrws;
280 int reserved_uars;
281 int num_mgms;
282 int num_amgms;
283 int reserved_mcgs;
284 int num_qp_per_mgm;
285 int num_pds;
286 int reserved_pds;
287 int max_xrcds;
288 int reserved_xrcds;
289 int mtt_entry_sz;
290 u32 max_msg_sz;
291 u32 page_size_cap;
292 u64 flags;
293 u32 bmme_flags;
294 u32 reserved_lkey;
295 u16 stat_rate_support;
296 u8 port_width_cap[MLX4_MAX_PORTS + 1];
297 int max_gso_sz;
298 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
299 int reserved_qps;
300 int reserved_qps_base[MLX4_NUM_QP_REGION];
301 int log_num_macs;
302 int log_num_vlans;
303 int log_num_prios;
304 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
305 u8 supported_type[MLX4_MAX_PORTS + 1];
306 u8 suggested_type[MLX4_MAX_PORTS + 1];
307 u8 default_sense[MLX4_MAX_PORTS + 1];
308 u32 port_mask[MLX4_MAX_PORTS + 1];
309 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
310 u32 max_counters;
311 u8 ext_port_cap[MLX4_MAX_PORTS + 1];