Lines Matching +full:simple +full:- +full:framebuffer
4 * framebuffer driver for ATI Radeon chipset video boards
38 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
79 #include <asm/pci-bridge.h>
267 static int default_dynclk = -2;
291 if (!rinfo->bios_seg) in radeon_unmap_ROM()
293 pci_unmap_rom(dev, rinfo->bios_seg); in radeon_unmap_ROM()
319 pci_name(rinfo->pdev)); in radeon_map_ROM()
320 return -ENOMEM; in radeon_map_ROM()
323 rinfo->bios_seg = rom; in radeon_map_ROM()
325 /* Very simple test to make sure it appeared */ in radeon_map_ROM()
329 pci_name(rinfo->pdev), BIOS_IN16(0)); in radeon_map_ROM()
341 * relative start of ROM, but so far, I never found a dual-image ATI card in radeon_map_ROM()
361 "incorrect: %08x\n", pci_name(rinfo->pdev), BIOS_IN32(dptr)); in radeon_map_ROM()
373 printk(KERN_INFO "radeonfb: Found HP PA-RISC ROM Image\n"); in radeon_map_ROM()
381 rinfo->fp_bios_start = BIOS_IN16(0x48); in radeon_map_ROM()
385 rinfo->bios_seg = NULL; in radeon_map_ROM()
387 return -ENXIO; in radeon_map_ROM()
404 return -ENOMEM; in radeon_find_mem_vbios()
411 return -ENXIO; in radeon_find_mem_vbios()
414 rinfo->bios_seg = rom_base; in radeon_find_mem_vbios()
415 rinfo->fp_bios_start = BIOS_IN16(0x48); in radeon_find_mem_vbios()
428 struct device_node *dp = rinfo->of_node; in radeon_read_xtal_OF()
432 return -ENODEV; in radeon_read_xtal_OF()
436 return -EINVAL; in radeon_read_xtal_OF()
439 rinfo->pll.ref_clk = (*val) / 10; in radeon_read_xtal_OF()
443 rinfo->pll.sclk = (*val) / 10; in radeon_read_xtal_OF()
447 rinfo->pll.mclk = (*val) / 10; in radeon_read_xtal_OF()
469 * here, so... --BenH in radeon_probe_pll_params()
495 total_secs = stop_tv.tv_sec - start_tv.tv_sec; in radeon_probe_pll_params()
497 return -1; in radeon_probe_pll_params()
498 total_usecs = stop_tv.tv_usec - start_tv.tv_usec; in radeon_probe_pll_params()
501 total_usecs = -total_usecs; in radeon_probe_pll_params()
570 return -1; in radeon_probe_pll_params()
583 rinfo->pll.ref_clk = xtal; in radeon_probe_pll_params()
584 rinfo->pll.ref_div = ref_div; in radeon_probe_pll_params()
585 rinfo->pll.sclk = sclk; in radeon_probe_pll_params()
586 rinfo->pll.mclk = mclk; in radeon_probe_pll_params()
601 switch (rinfo->chipset) { in radeon_get_pllinfo()
604 rinfo->pll.ppll_max = 35000; in radeon_get_pllinfo()
605 rinfo->pll.ppll_min = 12000; in radeon_get_pllinfo()
606 rinfo->pll.mclk = 23000; in radeon_get_pllinfo()
607 rinfo->pll.sclk = 23000; in radeon_get_pllinfo()
608 rinfo->pll.ref_clk = 2700; in radeon_get_pllinfo()
615 rinfo->pll.ppll_max = 35000; in radeon_get_pllinfo()
616 rinfo->pll.ppll_min = 12000; in radeon_get_pllinfo()
617 rinfo->pll.mclk = 27500; in radeon_get_pllinfo()
618 rinfo->pll.sclk = 27500; in radeon_get_pllinfo()
619 rinfo->pll.ref_clk = 2700; in radeon_get_pllinfo()
625 rinfo->pll.ppll_max = 35000; in radeon_get_pllinfo()
626 rinfo->pll.ppll_min = 12000; in radeon_get_pllinfo()
627 rinfo->pll.mclk = 25000; in radeon_get_pllinfo()
628 rinfo->pll.sclk = 25000; in radeon_get_pllinfo()
629 rinfo->pll.ref_clk = 2700; in radeon_get_pllinfo()
635 rinfo->pll.ppll_max = 40000; in radeon_get_pllinfo()
636 rinfo->pll.ppll_min = 20000; in radeon_get_pllinfo()
637 rinfo->pll.mclk = 27000; in radeon_get_pllinfo()
638 rinfo->pll.sclk = 27000; in radeon_get_pllinfo()
639 rinfo->pll.ref_clk = 2700; in radeon_get_pllinfo()
646 rinfo->pll.ppll_max = 35000; in radeon_get_pllinfo()
647 rinfo->pll.ppll_min = 12000; in radeon_get_pllinfo()
648 rinfo->pll.mclk = 16600; in radeon_get_pllinfo()
649 rinfo->pll.sclk = 16600; in radeon_get_pllinfo()
650 rinfo->pll.ref_clk = 2700; in radeon_get_pllinfo()
653 rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK; in radeon_get_pllinfo()
670 if (!force_measure_pll && rinfo->bios_seg) { in radeon_get_pllinfo()
671 u16 pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30); in radeon_get_pllinfo()
673 rinfo->pll.sclk = BIOS_IN16(pll_info_block + 0x08); in radeon_get_pllinfo()
674 rinfo->pll.mclk = BIOS_IN16(pll_info_block + 0x0a); in radeon_get_pllinfo()
675 rinfo->pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e); in radeon_get_pllinfo()
676 rinfo->pll.ref_div = BIOS_IN16(pll_info_block + 0x10); in radeon_get_pllinfo()
677 rinfo->pll.ppll_min = BIOS_IN32(pll_info_block + 0x12); in radeon_get_pllinfo()
678 rinfo->pll.ppll_max = BIOS_IN32(pll_info_block + 0x16); in radeon_get_pllinfo()
694 * Fall back to already-set defaults... in radeon_get_pllinfo()
704 if (rinfo->pll.mclk == 0) in radeon_get_pllinfo()
705 rinfo->pll.mclk = 20000; in radeon_get_pllinfo()
706 if (rinfo->pll.sclk == 0) in radeon_get_pllinfo()
707 rinfo->pll.sclk = 20000; in radeon_get_pllinfo()
710 rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100, in radeon_get_pllinfo()
711 rinfo->pll.ref_div, in radeon_get_pllinfo()
712 rinfo->pll.mclk / 100, rinfo->pll.mclk % 100, in radeon_get_pllinfo()
713 rinfo->pll.sclk / 100, rinfo->pll.sclk % 100); in radeon_get_pllinfo()
714 printk("radeonfb: PLL min %d max %d\n", rinfo->pll.ppll_min, rinfo->pll.ppll_max); in radeon_get_pllinfo()
719 struct radeonfb_info *rinfo = info->par; in radeonfb_check_var()
725 return -EINVAL; in radeonfb_check_var()
739 return -EINVAL; in radeonfb_check_var()
744 return -EINVAL; in radeonfb_check_var()
795 var->xres, var->yres, var->bits_per_pixel); in radeonfb_check_var()
796 return -EINVAL; in radeonfb_check_var()
808 if (rinfo->info->flags & FBINFO_HWACCEL_DISABLED) { in radeonfb_check_var()
816 if (((v.xres_virtual * v.yres_virtual * nom) / den) > rinfo->mapped_vram) in radeonfb_check_var()
817 return -EINVAL; in radeonfb_check_var()
827 if (v.xoffset > v.xres_virtual - v.xres) in radeonfb_check_var()
828 v.xoffset = v.xres_virtual - v.xres - 1; in radeonfb_check_var()
830 if (v.yoffset > v.yres_virtual - v.yres) in radeonfb_check_var()
831 v.yoffset = v.yres_virtual - v.yres - 1; in radeonfb_check_var()
846 struct radeonfb_info *rinfo = info->par; in radeonfb_pan_display()
848 if ((var->xoffset + info->var.xres > info->var.xres_virtual) in radeonfb_pan_display()
849 || (var->yoffset + info->var.yres > info->var.yres_virtual)) in radeonfb_pan_display()
850 return -EINVAL; in radeonfb_pan_display()
852 if (rinfo->asleep) in radeonfb_pan_display()
856 OUTREG(CRTC_OFFSET, (var->yoffset * info->fix.line_length + in radeonfb_pan_display()
857 var->xoffset * info->var.bits_per_pixel / 8) & ~7); in radeonfb_pan_display()
865 struct radeonfb_info *rinfo = info->par; in radeonfb_ioctl()
872 * TODO: set mirror accordingly for non-Mobility chipsets with 2 CRTC's in radeonfb_ioctl()
877 if (!rinfo->is_mobility) in radeonfb_ioctl()
878 return -EINVAL; in radeonfb_ioctl()
914 if (!rinfo->is_mobility) in radeonfb_ioctl()
915 return -EINVAL; in radeonfb_ioctl()
927 return -EINVAL; in radeonfb_ioctl()
930 return -EINVAL; in radeonfb_ioctl()
940 if (rinfo->lock_blank) in radeon_screen_blank()
969 switch (rinfo->mon1_type) { in radeon_screen_blank()
981 del_timer_sync(&rinfo->lvds_timer); in radeon_screen_blank()
985 | LVDS_EN | (rinfo->init_state.lvds_gen_cntl in radeon_screen_blank()
992 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK; in radeon_screen_blank()
993 rinfo->init_state.lvds_gen_cntl |= in radeon_screen_blank()
996 radeon_msleep(rinfo->panel_info.pwr_delay); in radeon_screen_blank()
1000 rinfo->pending_lvds_gen_cntl = target_val; in radeon_screen_blank()
1001 mod_timer(&rinfo->lvds_timer, in radeon_screen_blank()
1003 msecs_to_jiffies(rinfo->panel_info.pwr_delay)); in radeon_screen_blank()
1010 /* We don't do a full switch-off on a simple mode switch */ in radeon_screen_blank()
1018 if (rinfo->is_mobility || rinfo->is_IGP) in radeon_screen_blank()
1026 rinfo->pending_lvds_gen_cntl = val; in radeon_screen_blank()
1027 mod_timer(&rinfo->lvds_timer, in radeon_screen_blank()
1029 msecs_to_jiffies(rinfo->panel_info.pwr_delay)); in radeon_screen_blank()
1030 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK; in radeon_screen_blank()
1031 rinfo->init_state.lvds_gen_cntl |= val & LVDS_STATE_MASK; in radeon_screen_blank()
1032 if (rinfo->is_mobility || rinfo->is_IGP) in radeon_screen_blank()
1047 struct radeonfb_info *rinfo = info->par; in radeonfb_blank()
1049 if (rinfo->asleep) in radeonfb_blank()
1064 return -EINVAL; in radeon_setcolreg()
1069 rinfo->palette[regno].red = red; in radeon_setcolreg()
1070 rinfo->palette[regno].green = green; in radeon_setcolreg()
1071 rinfo->palette[regno].blue = blue; in radeon_setcolreg()
1076 if (!rinfo->asleep) { in radeon_setcolreg()
1079 if (rinfo->bpp == 16) { in radeon_setcolreg()
1082 if (rinfo->depth == 16 && regno > 63) in radeon_setcolreg()
1083 return -EINVAL; in radeon_setcolreg()
1084 if (rinfo->depth == 15 && regno > 31) in radeon_setcolreg()
1085 return -EINVAL; in radeon_setcolreg()
1090 if (rinfo->depth == 16) { in radeon_setcolreg()
1093 (rinfo->palette[regno>>1].red << 16) | in radeon_setcolreg()
1095 (rinfo->palette[regno>>1].blue)); in radeon_setcolreg()
1096 green = rinfo->palette[regno<<1].green; in radeon_setcolreg()
1100 if (rinfo->depth != 16 || regno < 32) { in radeon_setcolreg()
1107 u32 *pal = rinfo->info->pseudo_palette; in radeon_setcolreg()
1108 switch (rinfo->depth) { in radeon_setcolreg()
1131 struct radeonfb_info *rinfo = info->par; in radeonfb_setcolreg()
1135 if (!rinfo->asleep) { in radeonfb_setcolreg()
1136 if (rinfo->is_mobility) { in radeonfb_setcolreg()
1143 if (rinfo->has_CRTC2) { in radeonfb_setcolreg()
1152 if (!rinfo->asleep && rinfo->is_mobility) in radeonfb_setcolreg()
1160 struct radeonfb_info *rinfo = info->par; in radeonfb_setcmap()
1165 if (!rinfo->asleep) { in radeonfb_setcmap()
1166 if (rinfo->is_mobility) { in radeonfb_setcmap()
1173 if (rinfo->has_CRTC2) { in radeonfb_setcmap()
1180 red = cmap->red; in radeonfb_setcmap()
1181 green = cmap->green; in radeonfb_setcmap()
1182 blue = cmap->blue; in radeonfb_setcmap()
1183 transp = cmap->transp; in radeonfb_setcmap()
1184 start = cmap->start; in radeonfb_setcmap()
1186 for (i = 0; i < cmap->len; i++) { in radeonfb_setcmap()
1200 if (!rinfo->asleep && rinfo->is_mobility) in radeonfb_setcmap()
1210 save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL); in radeon_save_state()
1211 save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL); in radeon_save_state()
1212 save->crtc_more_cntl = INREG(CRTC_MORE_CNTL); in radeon_save_state()
1213 save->dac_cntl = INREG(DAC_CNTL); in radeon_save_state()
1214 save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP); in radeon_save_state()
1215 save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID); in radeon_save_state()
1216 save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP); in radeon_save_state()
1217 save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID); in radeon_save_state()
1218 save->crtc_pitch = INREG(CRTC_PITCH); in radeon_save_state()
1219 save->surface_cntl = INREG(SURFACE_CNTL); in radeon_save_state()
1222 save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP); in radeon_save_state()
1223 save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP); in radeon_save_state()
1224 save->fp_gen_cntl = INREG(FP_GEN_CNTL); in radeon_save_state()
1225 save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID); in radeon_save_state()
1226 save->fp_horz_stretch = INREG(FP_HORZ_STRETCH); in radeon_save_state()
1227 save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID); in radeon_save_state()
1228 save->fp_vert_stretch = INREG(FP_VERT_STRETCH); in radeon_save_state()
1229 save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL); in radeon_save_state()
1230 save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL); in radeon_save_state()
1231 save->tmds_crc = INREG(TMDS_CRC); in radeon_save_state()
1232 save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL); in radeon_save_state()
1233 save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL); in radeon_save_state()
1236 save->clk_cntl_index = INREG(CLOCK_CNTL_INDEX) & ~0x3f; in radeon_save_state()
1238 save->ppll_div_3 = INPLL(PPLL_DIV_3); in radeon_save_state()
1239 save->ppll_ref_div = INPLL(PPLL_REF_DIV); in radeon_save_state()
1250 if (rinfo->is_mobility) { in radeon_write_pll_regs()
1258 if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) && in radeon_write_pll_regs()
1259 (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) & in radeon_write_pll_regs()
1265 mode->clk_cntl_index & PPLL_DIV_SEL_MASK, in radeon_write_pll_regs()
1283 mode->clk_cntl_index & PPLL_DIV_SEL_MASK, in radeon_write_pll_regs()
1290 rinfo->family == CHIP_FAMILY_RS300 || in radeon_write_pll_regs()
1291 rinfo->family == CHIP_FAMILY_RS400 || in radeon_write_pll_regs()
1292 rinfo->family == CHIP_FAMILY_RS480) { in radeon_write_pll_regs()
1293 if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { in radeon_write_pll_regs()
1297 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0); in radeon_write_pll_regs()
1301 (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), in radeon_write_pll_regs()
1305 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK); in radeon_write_pll_regs()
1308 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK); in radeon_write_pll_regs()
1309 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK); in radeon_write_pll_regs()
1346 OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl); in radeon_lvds_timer_func()
1371 OUTREG(SURFACE0_LOWER_BOUND + 0x10*i, mode->surf_lower_bound[i]); in radeon_write_mode()
1372 OUTREG(SURFACE0_UPPER_BOUND + 0x10*i, mode->surf_upper_bound[i]); in radeon_write_mode()
1373 OUTREG(SURFACE0_INFO + 0x10*i, mode->surf_info[i]); in radeon_write_mode()
1376 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl); in radeon_write_mode()
1377 OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl, in radeon_write_mode()
1379 OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl); in radeon_write_mode()
1380 OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING); in radeon_write_mode()
1381 OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp); in radeon_write_mode()
1382 OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid); in radeon_write_mode()
1383 OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp); in radeon_write_mode()
1384 OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid); in radeon_write_mode()
1387 OUTREG(CRTC_PITCH, mode->crtc_pitch); in radeon_write_mode()
1388 OUTREG(SURFACE_CNTL, mode->surface_cntl); in radeon_write_mode()
1394 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp); in radeon_write_mode()
1395 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp); in radeon_write_mode()
1396 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid); in radeon_write_mode()
1397 OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid); in radeon_write_mode()
1398 OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch); in radeon_write_mode()
1399 OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch); in radeon_write_mode()
1400 OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl); in radeon_write_mode()
1401 OUTREG(TMDS_CRC, mode->tmds_crc); in radeon_write_mode()
1402 OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl); in radeon_write_mode()
1409 OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl); in radeon_write_mode()
1452 while (rinfo->has_CRTC2) { in radeon_calc_pll_regs()
1463 if (rinfo->family == CHIP_FAMILY_R200 || IS_R300_VARIANT(rinfo)) { in radeon_calc_pll_regs()
1474 /* sourced from CRTC2 -> exit */ in radeon_calc_pll_regs()
1485 if (freq > rinfo->pll.ppll_max) in radeon_calc_pll_regs()
1486 freq = rinfo->pll.ppll_max; in radeon_calc_pll_regs()
1487 if (freq*12 < rinfo->pll.ppll_min) in radeon_calc_pll_regs()
1488 freq = rinfo->pll.ppll_min / 12; in radeon_calc_pll_regs()
1490 freq, rinfo->pll.ppll_min, rinfo->pll.ppll_max); in radeon_calc_pll_regs()
1492 for (post_div = &post_divs[0]; post_div->divider; ++post_div) { in radeon_calc_pll_regs()
1493 pll_output_freq = post_div->divider * freq; in radeon_calc_pll_regs()
1497 if (uses_dvo && (post_div->divider & 1)) in radeon_calc_pll_regs()
1499 if (pll_output_freq >= rinfo->pll.ppll_min && in radeon_calc_pll_regs()
1500 pll_output_freq <= rinfo->pll.ppll_max) in radeon_calc_pll_regs()
1505 given by the terminal post_div->bitvalue */ in radeon_calc_pll_regs()
1506 if ( !post_div->divider ) { in radeon_calc_pll_regs()
1507 post_div = &post_divs[post_div->bitvalue]; in radeon_calc_pll_regs()
1508 pll_output_freq = post_div->divider * freq; in radeon_calc_pll_regs()
1511 rinfo->pll.ref_div, rinfo->pll.ref_clk, in radeon_calc_pll_regs()
1515 given by the terminal post_div->bitvalue */ in radeon_calc_pll_regs()
1516 if ( !post_div->divider ) { in radeon_calc_pll_regs()
1517 post_div = &post_divs[post_div->bitvalue]; in radeon_calc_pll_regs()
1518 pll_output_freq = post_div->divider * freq; in radeon_calc_pll_regs()
1521 rinfo->pll.ref_div, rinfo->pll.ref_clk, in radeon_calc_pll_regs()
1524 fb_div = round_div(rinfo->pll.ref_div*pll_output_freq, in radeon_calc_pll_regs()
1525 rinfo->pll.ref_clk); in radeon_calc_pll_regs()
1526 regs->ppll_ref_div = rinfo->pll.ref_div; in radeon_calc_pll_regs()
1527 regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16); in radeon_calc_pll_regs()
1529 pr_debug("post div = 0x%x\n", post_div->bitvalue); in radeon_calc_pll_regs()
1531 pr_debug("ppll_div_3 = 0x%x\n", regs->ppll_div_3); in radeon_calc_pll_regs()
1536 struct radeonfb_info *rinfo = info->par; in radeonfb_set_par()
1537 struct fb_var_screeninfo *mode = &info->var; in radeonfb_set_par()
1554 return -ENOMEM; in radeonfb_set_par()
1561 hSyncStart = mode->xres + mode->right_margin; in radeonfb_set_par()
1562 hSyncEnd = hSyncStart + mode->hsync_len; in radeonfb_set_par()
1563 hTotal = hSyncEnd + mode->left_margin; in radeonfb_set_par()
1565 vSyncStart = mode->yres + mode->lower_margin; in radeonfb_set_par()
1566 vSyncEnd = vSyncStart + mode->vsync_len; in radeonfb_set_par()
1567 vTotal = vSyncEnd + mode->upper_margin; in radeonfb_set_par()
1568 pixClock = mode->pixclock; in radeonfb_set_par()
1570 sync = mode->sync; in radeonfb_set_par()
1575 if (rinfo->panel_info.xres < mode->xres) in radeonfb_set_par()
1576 mode->xres = rinfo->panel_info.xres; in radeonfb_set_par()
1577 if (rinfo->panel_info.yres < mode->yres) in radeonfb_set_par()
1578 mode->yres = rinfo->panel_info.yres; in radeonfb_set_par()
1580 hTotal = mode->xres + rinfo->panel_info.hblank; in radeonfb_set_par()
1581 hSyncStart = mode->xres + rinfo->panel_info.hOver_plus; in radeonfb_set_par()
1582 hSyncEnd = hSyncStart + rinfo->panel_info.hSync_width; in radeonfb_set_par()
1584 vTotal = mode->yres + rinfo->panel_info.vblank; in radeonfb_set_par()
1585 vSyncStart = mode->yres + rinfo->panel_info.vOver_plus; in radeonfb_set_par()
1586 vSyncEnd = vSyncStart + rinfo->panel_info.vSync_width; in radeonfb_set_par()
1588 h_sync_pol = !rinfo->panel_info.hAct_high; in radeonfb_set_par()
1589 v_sync_pol = !rinfo->panel_info.vAct_high; in radeonfb_set_par()
1591 pixClock = 100000000 / rinfo->panel_info.clock; in radeonfb_set_par()
1593 if (rinfo->panel_info.use_bios_dividers) { in radeonfb_set_par()
1595 newmode->ppll_div_3 = rinfo->panel_info.fbk_divider | in radeonfb_set_par()
1596 (rinfo->panel_info.post_divider << 16); in radeonfb_set_par()
1597 newmode->ppll_ref_div = rinfo->panel_info.ref_divider; in radeonfb_set_par()
1608 hsync_wid = (hSyncEnd - hSyncStart) / 8; in radeonfb_set_par()
1609 vsync_wid = vSyncEnd - vSyncStart; in radeonfb_set_par()
1620 hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1; in radeonfb_set_par()
1621 vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1; in radeonfb_set_par()
1623 cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0; in radeonfb_set_par()
1626 bytpp = mode->bits_per_pixel >> 3; in radeonfb_set_par()
1629 hsync_fudge = hsync_fudge_fp[format-1]; in radeonfb_set_par()
1631 hsync_fudge = hsync_adj_tab[format-1]; in radeonfb_set_par()
1633 hsync_start = hSyncStart - 8 + hsync_fudge; in radeonfb_set_par()
1635 newmode->crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN | in radeonfb_set_par()
1638 /* Clear auto-center etc... */ in radeonfb_set_par()
1639 newmode->crtc_more_cntl = rinfo->init_state.crtc_more_cntl; in radeonfb_set_par()
1640 newmode->crtc_more_cntl &= 0xfffffff0; in radeonfb_set_par()
1643 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN; in radeonfb_set_par()
1645 newmode->crtc_ext_cntl |= CRTC_CRT_ON; in radeonfb_set_par()
1647 newmode->crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN | in radeonfb_set_par()
1650 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN | in radeonfb_set_par()
1654 newmode->dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN | in radeonfb_set_par()
1657 newmode->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) | in radeonfb_set_par()
1658 (((mode->xres / 8) - 1) << 16)); in radeonfb_set_par()
1660 newmode->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) | in radeonfb_set_par()
1663 newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) | in radeonfb_set_par()
1664 ((mode->yres - 1) << 16); in radeonfb_set_par()
1666 newmode->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) | in radeonfb_set_par()
1669 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) { in radeonfb_set_par()
1671 rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f) in radeonfb_set_par()
1674 /* Then, re-multiply it to get the CRTC pitch */ in radeonfb_set_par()
1675 newmode->crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8); in radeonfb_set_par()
1677 newmode->crtc_pitch = (mode->xres_virtual >> 3); in radeonfb_set_par()
1679 newmode->crtc_pitch |= (newmode->crtc_pitch << 16); in radeonfb_set_par()
1686 newmode->surface_cntl = 0; in radeonfb_set_par()
1694 switch (mode->bits_per_pixel) { in radeonfb_set_par()
1696 newmode->surface_cntl |= NONSURF_AP0_SWP_16BPP; in radeonfb_set_par()
1697 newmode->surface_cntl |= NONSURF_AP1_SWP_16BPP; in radeonfb_set_par()
1701 newmode->surface_cntl |= NONSURF_AP0_SWP_32BPP; in radeonfb_set_par()
1702 newmode->surface_cntl |= NONSURF_AP1_SWP_32BPP; in radeonfb_set_par()
1709 newmode->surf_lower_bound[i] = 0; in radeonfb_set_par()
1710 newmode->surf_upper_bound[i] = 0x1f; in radeonfb_set_par()
1711 newmode->surf_info[i] = 0; in radeonfb_set_par()
1715 newmode->crtc_h_total_disp, newmode->crtc_h_sync_strt_wid); in radeonfb_set_par()
1717 newmode->crtc_v_total_disp, newmode->crtc_v_sync_strt_wid); in radeonfb_set_par()
1719 rinfo->bpp = mode->bits_per_pixel; in radeonfb_set_par()
1720 rinfo->depth = depth; in radeonfb_set_par()
1726 newmode->clk_cntl_index = 0x300; in radeonfb_set_par()
1732 newmode->vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl; in radeonfb_set_par()
1737 if (mode->xres > rinfo->panel_info.xres) in radeonfb_set_par()
1738 mode->xres = rinfo->panel_info.xres; in radeonfb_set_par()
1739 if (mode->yres > rinfo->panel_info.yres) in radeonfb_set_par()
1740 mode->yres = rinfo->panel_info.yres; in radeonfb_set_par()
1742 newmode->fp_horz_stretch = (((rinfo->panel_info.xres / 8) - 1) in radeonfb_set_par()
1744 newmode->fp_vert_stretch = ((rinfo->panel_info.yres - 1) in radeonfb_set_par()
1747 if (mode->xres != rinfo->panel_info.xres) { in radeonfb_set_par()
1748 hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX, in radeonfb_set_par()
1749 rinfo->panel_info.xres); in radeonfb_set_par()
1750 newmode->fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) | in radeonfb_set_par()
1751 (newmode->fp_horz_stretch & in radeonfb_set_par()
1754 newmode->fp_horz_stretch |= (HORZ_STRETCH_BLEND | in radeonfb_set_par()
1758 newmode->fp_horz_stretch &= ~HORZ_AUTO_RATIO; in radeonfb_set_par()
1760 if (mode->yres != rinfo->panel_info.yres) { in radeonfb_set_par()
1761 vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX, in radeonfb_set_par()
1762 rinfo->panel_info.yres); in radeonfb_set_par()
1763 newmode->fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) | in radeonfb_set_par()
1764 (newmode->fp_vert_stretch & in radeonfb_set_par()
1766 newmode->fp_vert_stretch |= (VERT_STRETCH_BLEND | in radeonfb_set_par()
1770 newmode->fp_vert_stretch &= ~VERT_AUTO_RATIO_EN; in radeonfb_set_par()
1772 newmode->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32) in radeonfb_set_par()
1782 newmode->fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR | in radeonfb_set_par()
1787 (rinfo->family == CHIP_FAMILY_R200)) { in radeonfb_set_par()
1788 newmode->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; in radeonfb_set_par()
1790 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX; in radeonfb_set_par()
1792 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1; in radeonfb_set_par()
1794 newmode->fp_gen_cntl |= FP_SEL_CRTC1; in radeonfb_set_par()
1796 newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl; in radeonfb_set_par()
1797 newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl; in radeonfb_set_par()
1798 newmode->tmds_crc = rinfo->init_state.tmds_crc; in radeonfb_set_par()
1799 newmode->tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl; in radeonfb_set_par()
1802 newmode->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON); in radeonfb_set_par()
1803 newmode->fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN); in radeonfb_set_par()
1806 newmode->fp_gen_cntl |= (FP_FPON | FP_TMDS_EN); in radeonfb_set_par()
1807 newmode->tmds_transmitter_cntl &= ~(TMDS_PLLRST); in radeonfb_set_par()
1810 (rinfo->family == CHIP_FAMILY_R200) || !rinfo->has_CRTC2) in radeonfb_set_par()
1811 newmode->tmds_transmitter_cntl &= ~TMDS_PLL_EN; in radeonfb_set_par()
1813 newmode->tmds_transmitter_cntl |= TMDS_PLL_EN; in radeonfb_set_par()
1814 newmode->crtc_ext_cntl &= ~CRTC_CRT_ON; in radeonfb_set_par()
1817 newmode->fp_crtc_h_total_disp = (((rinfo->panel_info.hblank / 8) & 0x3ff) | in radeonfb_set_par()
1818 (((mode->xres / 8) - 1) << 16)); in radeonfb_set_par()
1819 newmode->fp_crtc_v_total_disp = (rinfo->panel_info.vblank & 0xffff) | in radeonfb_set_par()
1820 ((mode->yres - 1) << 16); in radeonfb_set_par()
1821 newmode->fp_h_sync_strt_wid = ((rinfo->panel_info.hOver_plus & 0x1fff) | in radeonfb_set_par()
1823 newmode->fp_v_sync_strt_wid = ((rinfo->panel_info.vOver_plus & 0xfff) | in radeonfb_set_par()
1828 if (!rinfo->asleep) { in radeonfb_set_par()
1829 memcpy(&rinfo->state, newmode, sizeof(*newmode)); in radeonfb_set_par()
1832 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) in radeonfb_set_par()
1836 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) in radeonfb_set_par()
1837 info->fix.line_length = rinfo->pitch*64; in radeonfb_set_par()
1839 info->fix.line_length = mode->xres_virtual in radeonfb_set_par()
1840 * ((mode->bits_per_pixel + 1) / 8); in radeonfb_set_par()
1841 info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR in radeonfb_set_par()
1846 btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres, in radeonfb_set_par()
1847 rinfo->depth, info->fix.line_length); in radeonfb_set_par()
1873 struct fb_info *info = rinfo->info; in radeon_set_fbinfo()
1875 info->par = rinfo; in radeon_set_fbinfo()
1876 info->pseudo_palette = rinfo->pseudo_palette; in radeon_set_fbinfo()
1877 info->flags = FBINFO_DEFAULT in radeon_set_fbinfo()
1882 info->fbops = &radeonfb_ops; in radeon_set_fbinfo()
1883 info->screen_base = rinfo->fb_base; in radeon_set_fbinfo()
1884 info->screen_size = rinfo->mapped_vram; in radeon_set_fbinfo()
1886 strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id)); in radeon_set_fbinfo()
1887 info->fix.smem_start = rinfo->fb_base_phys; in radeon_set_fbinfo()
1888 info->fix.smem_len = rinfo->video_ram; in radeon_set_fbinfo()
1889 info->fix.type = FB_TYPE_PACKED_PIXELS; in radeon_set_fbinfo()
1890 info->fix.visual = FB_VISUAL_PSEUDOCOLOR; in radeon_set_fbinfo()
1891 info->fix.xpanstep = 8; in radeon_set_fbinfo()
1892 info->fix.ypanstep = 1; in radeon_set_fbinfo()
1893 info->fix.ywrapstep = 0; in radeon_set_fbinfo()
1894 info->fix.type_aux = 0; in radeon_set_fbinfo()
1895 info->fix.mmio_start = rinfo->mmio_base_phys; in radeon_set_fbinfo()
1896 info->fix.mmio_len = RADEON_REGSIZE; in radeon_set_fbinfo()
1897 info->fix.accel = FB_ACCEL_ATI_RADEON; in radeon_set_fbinfo()
1899 fb_alloc_cmap(&info->cmap, 256, 0); in radeon_set_fbinfo()
1902 info->flags |= FBINFO_HWACCEL_DISABLED; in radeon_set_fbinfo()
1928 if (rinfo->has_CRTC2) { in fixup_memory_mappings()
1943 /* Set framebuffer to be at the same address as set in PCI BAR */ in fixup_memory_mappings()
1945 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16)); in fixup_memory_mappings()
1946 rinfo->fb_local_base = aper_base; in fixup_memory_mappings()
1949 rinfo->fb_local_base = 0; in fixup_memory_mappings()
1955 /* Set AGP to be just after the framebuffer on a 256Mb boundary. This in fixup_memory_mappings()
1970 if (rinfo->has_CRTC2) in fixup_memory_mappings()
1975 if (rinfo->has_CRTC2) in fixup_memory_mappings()
1984 if (rinfo->has_CRTC2) in fixup_memory_mappings()
1989 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16), in fixup_memory_mappings()
1999 /* framebuffer size */ in radeon_identify_vram()
2000 if ((rinfo->family == CHIP_FAMILY_RS100) || in radeon_identify_vram()
2001 (rinfo->family == CHIP_FAMILY_RS200) || in radeon_identify_vram()
2002 (rinfo->family == CHIP_FAMILY_RS300) || in radeon_identify_vram()
2003 (rinfo->family == CHIP_FAMILY_RC410) || in radeon_identify_vram()
2004 (rinfo->family == CHIP_FAMILY_RS400) || in radeon_identify_vram()
2005 (rinfo->family == CHIP_FAMILY_RS480) ) { in radeon_identify_vram()
2007 tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024); in radeon_identify_vram()
2018 if ((rinfo->family == CHIP_FAMILY_RS100) || in radeon_identify_vram()
2019 (rinfo->family == CHIP_FAMILY_RS200)) { in radeon_identify_vram()
2031 rinfo->video_ram = tmp & CNFG_MEMSIZE_MASK; in radeon_identify_vram()
2037 if (rinfo->video_ram == 0) { in radeon_identify_vram()
2038 switch (rinfo->pdev->device) { in radeon_identify_vram()
2041 rinfo->video_ram = 8192 * 1024; in radeon_identify_vram()
2052 if (rinfo->is_IGP || (rinfo->family >= CHIP_FAMILY_R300) || in radeon_identify_vram()
2054 rinfo->vram_ddr = 1; in radeon_identify_vram()
2056 rinfo->vram_ddr = 0; in radeon_identify_vram()
2062 case 0: rinfo->vram_width = 64; break; in radeon_identify_vram()
2063 case 1: rinfo->vram_width = 128; break; in radeon_identify_vram()
2064 case 2: rinfo->vram_width = 256; break; in radeon_identify_vram()
2065 default: rinfo->vram_width = 128; break; in radeon_identify_vram()
2067 } else if ((rinfo->family == CHIP_FAMILY_RV100) || in radeon_identify_vram()
2068 (rinfo->family == CHIP_FAMILY_RS100) || in radeon_identify_vram()
2069 (rinfo->family == CHIP_FAMILY_RS200)){ in radeon_identify_vram()
2071 rinfo->vram_width = 32; in radeon_identify_vram()
2073 rinfo->vram_width = 64; in radeon_identify_vram()
2076 rinfo->vram_width = 128; in radeon_identify_vram()
2078 rinfo->vram_width = 64; in radeon_identify_vram()
2086 pci_name(rinfo->pdev), in radeon_identify_vram()
2087 rinfo->video_ram / 1024, in radeon_identify_vram()
2088 rinfo->vram_ddr ? "DDR" : "SDRAM", in radeon_identify_vram()
2089 rinfo->vram_width); in radeon_identify_vram()
2109 struct radeonfb_info *rinfo = info->par; in radeon_show_edid1()
2111 return radeon_show_one_edid(buf, off, count, rinfo->mon1_EDID); in radeon_show_edid1()
2122 struct radeonfb_info *rinfo = info->par; in radeon_show_edid2()
2124 return radeon_show_one_edid(buf, off, count, rinfo->mon2_EDID); in radeon_show_edid2()
2165 info = framebuffer_alloc(sizeof(struct radeonfb_info), &pdev->dev); in radeonfb_pci_register()
2169 ret = -ENOMEM; in radeonfb_pci_register()
2172 rinfo = info->par; in radeonfb_pci_register()
2173 rinfo->info = info; in radeonfb_pci_register()
2174 rinfo->pdev = pdev; in radeonfb_pci_register()
2176 spin_lock_init(&rinfo->reg_lock); in radeonfb_pci_register()
2177 init_timer(&rinfo->lvds_timer); in radeonfb_pci_register()
2178 rinfo->lvds_timer.function = radeon_lvds_timer_func; in radeonfb_pci_register()
2179 rinfo->lvds_timer.data = (unsigned long)rinfo; in radeonfb_pci_register()
2181 c1 = ent->device >> 8; in radeonfb_pci_register()
2182 c2 = ent->device & 0xff; in radeonfb_pci_register()
2184 snprintf(rinfo->name, sizeof(rinfo->name), in radeonfb_pci_register()
2185 "ATI Radeon %x \"%c%c\"", ent->device & 0xffff, c1, c2); in radeonfb_pci_register()
2187 snprintf(rinfo->name, sizeof(rinfo->name), in radeonfb_pci_register()
2188 "ATI Radeon %x", ent->device & 0xffff); in radeonfb_pci_register()
2190 rinfo->family = ent->driver_data & CHIP_FAMILY_MASK; in radeonfb_pci_register()
2191 rinfo->chipset = pdev->device; in radeonfb_pci_register()
2192 rinfo->has_CRTC2 = (ent->driver_data & CHIP_HAS_CRTC2) != 0; in radeonfb_pci_register()
2193 rinfo->is_mobility = (ent->driver_data & CHIP_IS_MOBILITY) != 0; in radeonfb_pci_register()
2194 rinfo->is_IGP = (ent->driver_data & CHIP_IS_IGP) != 0; in radeonfb_pci_register()
2197 rinfo->fb_base_phys = pci_resource_start (pdev, 0); in radeonfb_pci_register()
2198 rinfo->mmio_base_phys = pci_resource_start (pdev, 2); in radeonfb_pci_register()
2201 ret = pci_request_region(pdev, 0, "radeonfb framebuffer"); in radeonfb_pci_register()
2204 pci_name(rinfo->pdev)); in radeonfb_pci_register()
2211 pci_name(rinfo->pdev)); in radeonfb_pci_register()
2216 rinfo->mmio_base = ioremap(rinfo->mmio_base_phys, RADEON_REGSIZE); in radeonfb_pci_register()
2217 if (!rinfo->mmio_base) { in radeonfb_pci_register()
2219 pci_name(rinfo->pdev)); in radeonfb_pci_register()
2220 ret = -EIO; in radeonfb_pci_register()
2224 rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16; in radeonfb_pci_register()
2229 rinfo->errata = 0; in radeonfb_pci_register()
2230 if (rinfo->family == CHIP_FAMILY_R300 && in radeonfb_pci_register()
2233 rinfo->errata |= CHIP_ERRATA_R300_CG; in radeonfb_pci_register()
2235 if (rinfo->family == CHIP_FAMILY_RV200 || in radeonfb_pci_register()
2236 rinfo->family == CHIP_FAMILY_RS200) in radeonfb_pci_register()
2237 rinfo->errata |= CHIP_ERRATA_PLL_DUMMYREADS; in radeonfb_pci_register()
2239 if (rinfo->family == CHIP_FAMILY_RV100 || in radeonfb_pci_register()
2240 rinfo->family == CHIP_FAMILY_RS100 || in radeonfb_pci_register()
2241 rinfo->family == CHIP_FAMILY_RS200) in radeonfb_pci_register()
2242 rinfo->errata |= CHIP_ERRATA_PLL_DELAY; in radeonfb_pci_register()
2245 /* On PPC, we obtain the OF device-node pointer to the firmware in radeonfb_pci_register()
2248 rinfo->of_node = pci_device_to_OF_node(pdev); in radeonfb_pci_register()
2249 if (rinfo->of_node == NULL) in radeonfb_pci_register()
2251 pci_name(rinfo->pdev)); in radeonfb_pci_register()
2265 rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, rinfo->video_ram); in radeonfb_pci_register()
2268 rinfo->fb_base = ioremap (rinfo->fb_base_phys, in radeonfb_pci_register()
2269 rinfo->mapped_vram); in radeonfb_pci_register()
2270 } while (rinfo->fb_base == NULL && in radeonfb_pci_register()
2271 ((rinfo->mapped_vram /= 2) >= MIN_MAPPED_VRAM)); in radeonfb_pci_register()
2273 if (rinfo->fb_base == NULL) { in radeonfb_pci_register()
2275 pci_name(rinfo->pdev)); in radeonfb_pci_register()
2276 ret = -EIO; in radeonfb_pci_register()
2280 pr_debug("radeonfb (%s): mapped %ldk videoram\n", pci_name(rinfo->pdev), in radeonfb_pci_register()
2281 rinfo->mapped_vram/1024); in radeonfb_pci_register()
2294 if (!rinfo->is_mobility) in radeonfb_pci_register()
2304 if (rinfo->bios_seg == NULL) in radeonfb_pci_register()
2311 if (rinfo->bios_seg == NULL && rinfo->is_mobility) in radeonfb_pci_register()
2332 if (rinfo->mon1_EDID) in radeonfb_pci_register()
2333 err |= sysfs_create_bin_file(&rinfo->pdev->dev.kobj, in radeonfb_pci_register()
2335 if (rinfo->mon2_EDID) in radeonfb_pci_register()
2336 err |= sysfs_create_bin_file(&rinfo->pdev->dev.kobj, in radeonfb_pci_register()
2345 radeon_save_state (rinfo, &rinfo->init_state); in radeonfb_pci_register()
2346 memcpy(&rinfo->state, &rinfo->init_state, sizeof(struct radeon_regs)); in radeonfb_pci_register()
2349 if (default_dynclk < -1) { in radeonfb_pci_register()
2350 /* -2 is special: means ON on mobility chips and do not in radeonfb_pci_register()
2353 radeonfb_pm_init(rinfo, rinfo->is_mobility ? 1 : -1, ignore_devlist, force_sleep); in radeonfb_pci_register()
2362 printk (KERN_ERR "radeonfb (%s): could not register framebuffer\n", in radeonfb_pci_register()
2363 pci_name(rinfo->pdev)); in radeonfb_pci_register()
2368 rinfo->mtrr_hdl = nomtrr ? -1 : mtrr_add(rinfo->fb_base_phys, in radeonfb_pci_register()
2369 rinfo->video_ram, in radeonfb_pci_register()
2376 printk ("radeonfb (%s): %s\n", pci_name(rinfo->pdev), rinfo->name); in radeonfb_pci_register()
2378 if (rinfo->bios_seg) in radeonfb_pci_register()
2384 iounmap(rinfo->fb_base); in radeonfb_pci_register()
2386 kfree(rinfo->mon1_EDID); in radeonfb_pci_register()
2387 kfree(rinfo->mon2_EDID); in radeonfb_pci_register()
2388 if (rinfo->mon1_modedb) in radeonfb_pci_register()
2389 fb_destroy_modedb(rinfo->mon1_modedb); in radeonfb_pci_register()
2390 fb_dealloc_cmap(&info->cmap); in radeonfb_pci_register()
2394 if (rinfo->bios_seg) in radeonfb_pci_register()
2396 iounmap(rinfo->mmio_base); in radeonfb_pci_register()
2413 struct radeonfb_info *rinfo = info->par; in radeonfb_pci_unregister()
2420 if (rinfo->mon1_EDID) in radeonfb_pci_unregister()
2421 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr); in radeonfb_pci_unregister()
2422 if (rinfo->mon2_EDID) in radeonfb_pci_unregister()
2423 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr); in radeonfb_pci_unregister()
2430 * magic here that I know nothing about. --BenH in radeonfb_pci_unregister()
2432 radeon_write_mode (rinfo, &rinfo->init_state, 1); in radeonfb_pci_unregister()
2435 del_timer_sync(&rinfo->lvds_timer); in radeonfb_pci_unregister()
2438 if (rinfo->mtrr_hdl >= 0) in radeonfb_pci_unregister()
2439 mtrr_del(rinfo->mtrr_hdl, 0, 0); in radeonfb_pci_unregister()
2446 iounmap(rinfo->mmio_base); in radeonfb_pci_unregister()
2447 iounmap(rinfo->fb_base); in radeonfb_pci_unregister()
2452 kfree(rinfo->mon1_EDID); in radeonfb_pci_unregister()
2453 kfree(rinfo->mon2_EDID); in radeonfb_pci_unregister()
2454 if (rinfo->mon1_modedb) in radeonfb_pci_unregister()
2455 fb_destroy_modedb(rinfo->mon1_modedb); in radeonfb_pci_unregister()
2459 fb_dealloc_cmap(&info->cmap); in radeonfb_pci_unregister()
2526 return -ENODEV; in radeonfb_init()
2542 MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");
2546 MODULE_PARM_DESC(default_dynclk, "int: -2=enable on mobility only,-1=do not change,0=off,1=on");
2567 MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");