Lines Matching +full:0 +full:x2000
102 640, 480, 640, 480, 0, 0, 8, 0,
103 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
104 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
105 0, FB_VMODE_NONINTERLACED
113 1024, 768, 1024, 768, 0, 0, 8, 0,
114 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
115 0, 0, -1, -1, 0, 12699, 160, 32, 28, 1, 96, 3,
134 .sync = 0,
175 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3_pci },
177 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3 },
179 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 },
181 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 },
183 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
185 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
187 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
189 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
191 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
193 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
195 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
197 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
199 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
201 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
203 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
205 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
207 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
209 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
211 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
213 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
215 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
217 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
219 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
221 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
223 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
225 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
227 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
229 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
231 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
233 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
235 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
237 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
239 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
241 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
243 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
245 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
247 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
249 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
251 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
253 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
255 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
257 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
259 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
261 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
263 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
265 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
267 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
268 { 0, }
341 .mmio_len = 0x2000,
352 static int default_crt_on __devinitdata = 0;
362 static int backlight __devinitdata = 0;
450 #if 0
536 aty_st_8(CLOCK_CNTL_INDEX, pll_index & 0x3F); in _aty_ld_pll()
544 aty_st_8(CLOCK_CNTL_INDEX, (pll_index & 0x3F) | PLL_WR_EN); in _aty_st_pll()
563 reset = 0; in aty_pll_wait_readupdate()
586 int flag = 0; in register_test()
590 aty_st_le32(BIOS_0_SCRATCH, 0x55555555); in register_test()
591 if (aty_ld_le32(BIOS_0_SCRATCH) == 0x55555555) { in register_test()
592 aty_st_le32(BIOS_0_SCRATCH, 0xAAAAAAAA); in register_test()
594 if (aty_ld_le32(BIOS_0_SCRATCH) == 0xAAAAAAAA) in register_test()
611 for (i = 0; i < 2000000; i++) { in do_wait_for_fifo()
612 par->fifo_slots = aty_ld_le32(GUI_STAT) & 0x0fff; in do_wait_for_fifo()
628 for (i = 0; i < 2000000; i++) { in wait_for_idle()
631 par->blitter_may_be_busy = 0; in wait_for_idle()
654 tmp &= ~(0x00ff); in aty128_flush_pixel_cache()
655 tmp |= 0x00ff; in aty128_flush_pixel_cache()
658 for (i = 0; i < 2000000; i++) in aty128_flush_pixel_cache()
673 aty_st_pll(MCLK_CNTL, mclk_cntl | 0x00030000); in aty128_reset_engine()
700 aty_st_le32(SCALE_3D_CNTL, 0x00000000); in aty128_init_engine()
711 aty_st_le32(DEFAULT_OFFSET, 0x00000000); in aty128_init_engine()
717 aty_st_le32(DEFAULT_SC_BOTTOM_RIGHT, (0x1FFF << 16) | 0x1FFF); in aty128_init_engine()
739 aty_st_le32(DST_BRES_ERR, 0); in aty128_init_engine()
740 aty_st_le32(DST_BRES_INC, 0); in aty128_init_engine()
741 aty_st_le32(DST_BRES_DEC, 0); in aty128_init_engine()
744 aty_st_le32(DP_BRUSH_FRGD_CLR, 0xFFFFFFFF); /* white */ in aty128_init_engine()
745 aty_st_le32(DP_BRUSH_BKGD_CLR, 0x00000000); /* black */ in aty128_init_engine()
748 aty_st_le32(DP_SRC_FRGD_CLR, 0xFFFFFFFF); /* white */ in aty128_init_engine()
749 aty_st_le32(DP_SRC_BKGD_CLR, 0x00000000); /* black */ in aty128_init_engine()
752 aty_st_le32(DP_WRITE_MASK, 0xFFFFFFFF); in aty128_init_engine()
792 temp &= 0x00ffffffu; in aty128_map_ROM()
793 temp |= 0x04 << 24; in aty128_map_ROM()
805 if (BIOS_IN16(0) != 0xaa55) { in aty128_map_ROM()
807 " be 0xaa55\n", BIOS_IN16(0)); in aty128_map_ROM()
812 dptr = BIOS_IN16(0x18); in aty128_map_ROM()
823 * u32 signature; + 0x00 in aty128_map_ROM()
824 * u16 vendor; + 0x04 in aty128_map_ROM()
825 * u16 device; + 0x06 in aty128_map_ROM()
826 * u16 reserved_1; + 0x08 in aty128_map_ROM()
827 * u16 dlen; + 0x0a in aty128_map_ROM()
828 * u8 drevision; + 0x0c in aty128_map_ROM()
829 * u8 class_hi; + 0x0d in aty128_map_ROM()
830 * u16 class_lo; + 0x0e in aty128_map_ROM()
831 * u16 ilen; + 0x10 in aty128_map_ROM()
832 * u16 irevision; + 0x12 in aty128_map_ROM()
833 * u8 type; + 0x14 in aty128_map_ROM()
834 * u8 indicator; + 0x15 in aty128_map_ROM()
835 * u16 reserved_2; + 0x16 in aty128_map_ROM()
843 rom_type = BIOS_IN8(dptr + 0x14); in aty128_map_ROM()
845 case 0: in aty128_map_ROM()
871 bios_hdr = BIOS_IN16(0x48); in aty128_get_pllinfo()
872 bios_pll = BIOS_IN16(bios_hdr + 0x30); in aty128_get_pllinfo()
874 par->constants.ppll_max = BIOS_IN32(bios_pll + 0x16); in aty128_get_pllinfo()
875 par->constants.ppll_min = BIOS_IN32(bios_pll + 0x12); in aty128_get_pllinfo()
876 par->constants.xclk = BIOS_IN16(bios_pll + 0x08); in aty128_get_pllinfo()
877 par->constants.ref_divider = BIOS_IN16(bios_pll + 0x10); in aty128_get_pllinfo()
878 par->constants.ref_clk = BIOS_IN16(bios_pll + 0x0e); in aty128_get_pllinfo()
898 for (segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) { in aty128_find_mem_vbios()
899 rom_base = ioremap(segstart, 0x10000); in aty128_find_mem_vbios()
902 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa) in aty128_find_mem_vbios()
923 unsigned PostDivSet[] = { 0, 1, 2, 4, 8, 3, 6, 12 }; in aty128_timings()
931 xclk_cntl = aty_ld_pll(XCLK_CNTL) & 0x7; in aty128_timings()
932 Nx = (x_mpll_ref_fb_div & 0x00ff00) >> 8; in aty128_timings()
933 M = x_mpll_ref_fb_div & 0x0000ff; in aty128_timings()
943 par->constants.ref_divider = 0x3b; in aty128_timings()
945 aty_st_pll(X_MPLL_REF_FB_DIV, 0x004c4c1e); in aty128_timings()
957 par->constants.xclk = 0x1d4d; /* same as mclk */ in aty128_timings()
962 switch (aty_ld_le32(MEM_CNTL) & 0x3) { in aty128_timings()
963 case 0: in aty128_timings()
996 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~(0x00030000)); in aty128_set_crtc()
1009 u8 mode_bytpp[7] = { 0, 0, 1, 2, 2, 3, 4 }; in aty128_var_to_crtc()
1066 h_total = (((xres + right + hslen + left) >> 3) - 1) & 0xFFFFL; in aty128_var_to_crtc()
1069 v_total = (yres + upper + vslen + lower - 1) & 0xFFFFL; in aty128_var_to_crtc()
1072 if (((h_total >> 3) - 1) > 0x1ff || (v_total - 1) > 0x7FF) { in aty128_var_to_crtc()
1078 if (h_sync_wid == 0) in aty128_var_to_crtc()
1080 else if (h_sync_wid > 0x3f) /* 0x3f = max hwidth */ in aty128_var_to_crtc()
1081 h_sync_wid = 0x3f; in aty128_var_to_crtc()
1086 if (v_sync_wid == 0) in aty128_var_to_crtc()
1088 else if (v_sync_wid > 0x1f) /* 0x1f = max vwidth */ in aty128_var_to_crtc()
1089 v_sync_wid = 0x1f; in aty128_var_to_crtc()
1093 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1; in aty128_var_to_crtc()
1094 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1; in aty128_var_to_crtc()
1096 c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0; in aty128_var_to_crtc()
1098 crtc->gen_cntl = 0x3000000L | c_sync | (dst << 8); in aty128_var_to_crtc()
1110 crtc->offset = 0; in aty128_var_to_crtc()
1113 crtc->offset_cntl = 0x00010000; in aty128_var_to_crtc()
1115 crtc->offset_cntl = 0; in aty128_var_to_crtc()
1124 return 0; in aty128_var_to_crtc()
1132 var->red.msb_right = 0; in aty128_pix_width_to_var()
1133 var->green.msb_right = 0; in aty128_pix_width_to_var()
1134 var->blue.offset = 0; in aty128_pix_width_to_var()
1135 var->blue.msb_right = 0; in aty128_pix_width_to_var()
1136 var->transp.offset = 0; in aty128_pix_width_to_var()
1137 var->transp.length = 0; in aty128_pix_width_to_var()
1138 var->transp.msb_right = 0; in aty128_pix_width_to_var()
1142 var->red.offset = 0; in aty128_pix_width_to_var()
1144 var->green.offset = 0; in aty128_pix_width_to_var()
1187 return 0; in aty128_pix_width_to_var()
1200 h_total = crtc->h_total & 0x1ff; in aty128_crtc_to_var()
1201 h_disp = (crtc->h_total >> 16) & 0xff; in aty128_crtc_to_var()
1202 h_sync_strt = (crtc->h_sync_strt_wid >> 3) & 0x1ff; in aty128_crtc_to_var()
1203 h_sync_dly = crtc->h_sync_strt_wid & 0x7; in aty128_crtc_to_var()
1204 h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x3f; in aty128_crtc_to_var()
1205 h_sync_pol = (crtc->h_sync_strt_wid >> 23) & 0x1; in aty128_crtc_to_var()
1206 v_total = crtc->v_total & 0x7ff; in aty128_crtc_to_var()
1207 v_disp = (crtc->v_total >> 16) & 0x7ff; in aty128_crtc_to_var()
1208 v_sync_strt = crtc->v_sync_strt_wid & 0x7ff; in aty128_crtc_to_var()
1209 v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f; in aty128_crtc_to_var()
1210 v_sync_pol = (crtc->v_sync_strt_wid >> 23) & 0x1; in aty128_crtc_to_var()
1211 c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0; in aty128_crtc_to_var()
1223 sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) | in aty128_crtc_to_var()
1224 (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) | in aty128_crtc_to_var()
1225 (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0); in aty128_crtc_to_var()
1244 return 0; in aty128_crtc_to_var()
1289 { 2, 0, 1, 4, 2, 2, 6, 2, 3, 2, 2, 2, 7 }; in aty128_set_pll()
1300 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider & 0x3ff); in aty128_set_pll()
1315 aty_st_pll(HTOTAL_CNTL, 0); /* no horiz crtc adjustment */ in aty128_set_pll()
1330 int i = 0; in aty128_var_to_pll()
1342 for (i = 0; i < ARRAY_SIZE(post_dividers); i++) { in aty128_var_to_pll()
1365 return 0; in aty128_var_to_pll()
1373 return 0; in aty128_pll_to_var()
1405 3 * ((m->Trcd - 2 > 0) ? m->Trcd - 2 : 0) + in aty128_ddafifo()
1414 b = 0; in aty128_ddafifo()
1438 return 0; in aty128_ddafifo()
1451 if ((err = aty128_decode_var(&info->var, par)) != 0) in aty128fb_set_par()
1458 aty_st_le32(OVR_CLR, 0); in aty128fb_set_par()
1459 aty_st_le32(OVR_WID_LEFT_RIGHT, 0); in aty128fb_set_par()
1460 aty_st_le32(OVR_WID_TOP_BOTTOM, 0); in aty128fb_set_par()
1461 aty_st_le32(OV0_SCALE_CNTL, 0); in aty128fb_set_par()
1462 aty_st_le32(MPP_TB_CONFIG, 0); in aty128fb_set_par()
1463 aty_st_le32(MPP_GP_CONFIG, 0); in aty128fb_set_par()
1464 aty_st_le32(SUBPIC_CNTL, 0); in aty128fb_set_par()
1465 aty_st_le32(VIPH_CONTROL, 0); in aty128fb_set_par()
1466 aty_st_le32(I2C_CNTL_1, 0); /* turn off i2c */ in aty128fb_set_par()
1467 aty_st_le32(GEN_INT_CNTL, 0); /* turn off interrupts */ in aty128fb_set_par()
1468 aty_st_le32(CAP0_TRIG_CNTL, 0); in aty128fb_set_par()
1469 aty_st_le32(CAP1_TRIG_CNTL, 0); in aty128fb_set_par()
1487 aty_st_8(CRTC_EXT_CNTL + 1, 0); /* turn the video back on */ in aty128fb_set_par()
1502 (((par->crtc.h_total>>16) & 0xff)+1)*8, in aty128fb_set_par()
1503 ((par->crtc.v_total>>16) & 0x7ff)+1, in aty128fb_set_par()
1508 return 0; in aty128fb_set_par()
1536 return 0; in aty128_decode_var()
1551 var->nonstd = 0; in aty128_encode_var()
1552 var->activate = 0; in aty128_encode_var()
1558 return 0; in aty128_encode_var()
1568 if ((err = aty128_decode_var(var, &par)) != 0) in aty128fb_check_var()
1571 return 0; in aty128fb_check_var()
1585 xres = (((par->crtc.h_total >> 16) & 0xff) + 1) << 3; in aty128fb_pan_display()
1586 yres = ((par->crtc.v_total >> 16) & 0x7ff) + 1; in aty128fb_pan_display()
1604 return 0; in aty128fb_pan_display()
1615 #if 0 in aty128_st_pal()
1640 return 0; in aty128fb_sync()
1649 return 0; in aty128fb_setup()
1653 default_lcd_on = simple_strtoul(this_opt+4, NULL, 0); in aty128fb_setup()
1656 default_crt_on = simple_strtoul(this_opt+4, NULL, 0); in aty128fb_setup()
1659 backlight = simple_strtoul(this_opt+10, NULL, 0); in aty128fb_setup()
1664 mtrr = 0; in aty128fb_setup()
1671 unsigned int vmode = simple_strtoul(this_opt+6, NULL, 0); in aty128fb_setup()
1672 if (vmode > 0 && vmode <= VMODE_MAX) in aty128fb_setup()
1676 unsigned int cmode = simple_strtoul(this_opt+6, NULL, 0); in aty128fb_setup()
1678 case 0: in aty128fb_setup()
1696 return 0; in aty128fb_setup()
1702 #define MAX_LEVEL 0xFF
1715 if (atylevel < 0) in aty128_bl_get_level_brightness()
1716 atylevel = 0; in aty128_bl_get_level_brightness()
1740 level = 0; in aty128_bl_update_status()
1745 if (level > 0) { in aty128_bl_update_status()
1767 reg |= (aty128_bl_get_level_brightness(par, 0) << LVDS_BL_MOD_LEVEL_SHIFT); in aty128_bl_update_status()
1781 return 0; in aty128_bl_update_status()
1820 memset(&props, 0, sizeof(struct backlight_properties)); in aty128_bl_init()
1832 fb_bl_default_curve(info, 0, in aty128_bl_init()
1882 chip_rev = (aty_ld_le32(CNFG_CNTL) >> 16) & 0x1F; in aty128_init()
1886 video_card[9] = ent->device & 0xFF; in aty128_init()
1892 printk(KERN_INFO "aty128fb: %s [chip rev 0x%x] ", video_card, chip_rev); in aty128_init()
1894 if (par->vram_size % (1024 * 1024) == 0) in aty128_init()
1913 pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, NULL, 0, 1); in aty128_init()
1914 #if 0 /* Disable the early video resume hack for now as it's causing problems, among in aty128_init()
1929 if (default_vmode <= 0 || default_vmode > VMODE_MAX) in aty128_init()
1970 0, &defaultmode, 8) == 0) in aty128_init()
1979 return 0; in aty128_init()
1994 fb_alloc_cmap(&info->cmap, 256, 0); in aty128_init()
2002 par->asleep = 0; in aty128_init()
2003 par->lock_blank = 0; in aty128_init()
2010 if (register_framebuffer(info) < 0) in aty128_init()
2011 return 0; in aty128_init()
2038 fb_addr = pci_resource_start(pdev, 0); in aty128_probe()
2039 if (!request_mem_region(fb_addr, pci_resource_len(pdev, 0), in aty128_probe()
2071 par->vram_size = aty_ld_le32(CNFG_MEMSIZE) & 0x03FFFFFF; in aty128_probe()
2120 return 0; in aty128_probe()
2132 release_mem_region(pci_resource_start(pdev, 0), in aty128_probe()
2133 pci_resource_len(pdev, 0)); in aty128_probe()
2161 release_mem_region(pci_resource_start(pdev, 0), in aty128_remove()
2162 pci_resource_len(pdev, 0)); in aty128_remove()
2180 return 0; in aty128fb_blank()
2197 state = 0; in aty128fb_blank()
2207 return 0; in aty128fb_blank()
2213 * entries in the var structure). Return != 0 for invalid regno.
2250 if (par->crtc.depth == 16 && regno > 0) { in aty128fb_setcolreg()
2272 return 0; in aty128fb_setcolreg()
2275 #define ATY_MIRROR_LCD_ON 0x00000001
2276 #define ATY_MIRROR_CRT_ON 0x00000002
2278 /* out param: u32* backlight value: 0 to 15 */
2280 /* in param: u32* backlight value: 0 to 15 */
2296 par->lcd_on = (value & 0x01) != 0; in aty128fb_ioctl()
2297 par->crt_on = (value & 0x02) != 0; in aty128fb_ioctl()
2302 return 0; in aty128fb_ioctl()
2312 #if 0
2374 #endif /* 0 */
2400 pmgt = 0x0c005407; in aty128_set_suspend()
2403 aty_st_le32(BUS_CNTL1, 0x00000010); in aty128_set_suspend()
2404 aty_st_le32(MEM_POWER_MISC, 0x0c830000); in aty128_set_suspend()
2423 /* We don't do anything but D2, for now we return 0, but in aty128_pci_suspend()
2434 return 0; in aty128_pci_suspend()
2438 return 0; in aty128_pci_suspend()
2478 return 0; in aty128_pci_suspend()
2487 return 0; in aty128_do_resume()
2495 aty128_set_suspend(par, 0); in aty128_do_resume()
2496 par->asleep = 0; in aty128_do_resume()
2506 fb_set_suspend(info, 0); in aty128_do_resume()
2509 par->lock_blank = 0; in aty128_do_resume()
2510 aty128fb_blank(0, info); in aty128_do_resume()
2524 return 0; in aty128_do_resume()
2564 module_param(mode_option, charp, 0);
2567 module_param_named(nomtrr, mtrr, invbool, 0);
2568 MODULE_PARM_DESC(nomtrr, "bool: Disable MTRR support (0 or 1=disabled) (default=0)");