Lines Matching +full:fpga +full:- +full:bridge
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
20 * 02110-1301 USA
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
40 * in the works. These are normal Linux-USB controller drivers which
54 * - Lack of host-side transaction scheduling, for all transfer types.
60 * includes DaVinci EVM in a common non-OTG mode.
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific informarion
105 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
109 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
115 #define MUSB_DRIVER_NAME "musb-hdrc"
124 /*-------------------------------------------------------------------------*/
131 /*-------------------------------------------------------------------------*/
136 void __iomem *addr = otg->io_priv; in musb_ulpi_read()
158 return -ETIMEDOUT; in musb_ulpi_read()
171 void __iomem *addr = otg->io_priv; in musb_ulpi_write()
189 return -ETIMEDOUT; in musb_ulpi_write()
208 /*-------------------------------------------------------------------------*/
217 struct musb *musb = hw_ep->musb; in musb_write_fifo()
218 void __iomem *fifo = hw_ep->fifo; in musb_write_fifo()
222 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", in musb_write_fifo()
223 'T', hw_ep->epnum, fifo, len, src); in musb_write_fifo()
229 /* best case is 32bit-aligned source address */ in musb_write_fifo()
259 struct musb *musb = hw_ep->musb; in musb_read_fifo()
260 void __iomem *fifo = hw_ep->fifo; in musb_read_fifo()
262 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", in musb_read_fifo()
263 'R', hw_ep->epnum, fifo, len, dst); in musb_read_fifo()
269 /* best case is 32bit-aligned destination address */ in musb_read_fifo()
297 /*-------------------------------------------------------------------------*/
321 void __iomem *regs = musb->endpoints[0].regs; in musb_load_testpacket()
323 musb_ep_select(musb->mregs, 0); in musb_load_testpacket()
324 musb_write_fifo(musb->control_ep, in musb_load_testpacket()
329 /*-------------------------------------------------------------------------*/
339 spin_lock_irqsave(&musb->lock, flags); in musb_otg_timer_func()
340 switch (musb->xceiv->state) { in musb_otg_timer_func()
342 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n"); in musb_otg_timer_func()
344 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; in musb_otg_timer_func()
345 musb->is_active = 0; in musb_otg_timer_func()
349 dev_dbg(musb->controller, "HNP: %s timeout\n", in musb_otg_timer_func()
350 otg_state_string(musb->xceiv->state)); in musb_otg_timer_func()
352 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL; in musb_otg_timer_func()
355 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n", in musb_otg_timer_func()
356 otg_state_string(musb->xceiv->state)); in musb_otg_timer_func()
358 musb->ignore_disconnect = 0; in musb_otg_timer_func()
359 spin_unlock_irqrestore(&musb->lock, flags); in musb_otg_timer_func()
368 void __iomem *mbase = musb->mregs; in musb_hnp_stop()
371 dev_dbg(musb->controller, "HNP: stop from %s\n", otg_state_string(musb->xceiv->state)); in musb_hnp_stop()
373 switch (musb->xceiv->state) { in musb_hnp_stop()
376 dev_dbg(musb->controller, "HNP: back to %s\n", in musb_hnp_stop()
377 otg_state_string(musb->xceiv->state)); in musb_hnp_stop()
380 dev_dbg(musb->controller, "HNP: Disabling HR\n"); in musb_hnp_stop()
381 hcd->self.is_b_host = 0; in musb_hnp_stop()
382 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; in musb_hnp_stop()
390 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n", in musb_hnp_stop()
391 otg_state_string(musb->xceiv->state)); in musb_hnp_stop()
399 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16); in musb_hnp_stop()
419 dev_dbg(musb->controller, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl, in musb_stage0_irq()
428 dev_dbg(musb->controller, "RESUME (%s)\n", otg_state_string(musb->xceiv->state)); in musb_stage0_irq()
431 void __iomem *mbase = musb->mregs; in musb_stage0_irq()
433 switch (musb->xceiv->state) { in musb_stage0_irq()
441 musb->int_usb &= ~MUSB_INTR_SUSPEND; in musb_stage0_irq()
442 dev_dbg(musb->controller, "Spurious SUSPENDM\n"); in musb_stage0_irq()
450 musb->port1_status |= in musb_stage0_irq()
453 musb->rh_timer = jiffies in musb_stage0_irq()
456 musb->xceiv->state = OTG_STATE_A_HOST; in musb_stage0_irq()
457 musb->is_active = 1; in musb_stage0_irq()
461 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; in musb_stage0_irq()
462 musb->is_active = 1; in musb_stage0_irq()
468 otg_state_string(musb->xceiv->state)); in musb_stage0_irq()
471 switch (musb->xceiv->state) { in musb_stage0_irq()
474 musb->xceiv->state = OTG_STATE_A_HOST; in musb_stage0_irq()
485 musb->int_usb |= MUSB_INTR_DISCONNECT; in musb_stage0_irq()
486 musb->int_usb &= ~MUSB_INTR_SUSPEND; in musb_stage0_irq()
492 musb->int_usb &= ~MUSB_INTR_SUSPEND; in musb_stage0_irq()
497 otg_state_string(musb->xceiv->state)); in musb_stage0_irq()
504 void __iomem *mbase = musb->mregs; in musb_stage0_irq()
508 dev_dbg(musb->controller, "SessReq while on B state\n"); in musb_stage0_irq()
512 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n", in musb_stage0_irq()
513 otg_state_string(musb->xceiv->state)); in musb_stage0_irq()
517 * - turn on VBUS (with silicon-specific mechanism) in musb_stage0_irq()
518 * - go through A_WAIT_VRISE in musb_stage0_irq()
519 * - ... to A_WAIT_BCON. in musb_stage0_irq()
523 musb->ep0_stage = MUSB_EP0_START; in musb_stage0_irq()
524 musb->xceiv->state = OTG_STATE_A_IDLE; in musb_stage0_irq()
534 /* During connection as an A-Device, we may see a short in musb_stage0_irq()
537 * (So: less common with truly self-powered devices, where in musb_stage0_irq()
545 * (b) software: ignore non-repeated VBUS errors. in musb_stage0_irq()
550 switch (musb->xceiv->state) { in musb_stage0_irq()
560 if (musb->vbuserr_retry) { in musb_stage0_irq()
561 void __iomem *mbase = musb->mregs; in musb_stage0_irq()
563 musb->vbuserr_retry--; in musb_stage0_irq()
568 musb->port1_status |= in musb_stage0_irq()
577 dev_dbg(musb->controller, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n", in musb_stage0_irq()
578 otg_state_string(musb->xceiv->state), in musb_stage0_irq()
592 VBUSERR_RETRY_COUNT - musb->vbuserr_retry, in musb_stage0_irq()
593 musb->port1_status); in musb_stage0_irq()
602 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x power %02x\n", in musb_stage0_irq()
603 otg_state_string(musb->xceiv->state), devctl, power); in musb_stage0_irq()
606 switch (musb->xceiv->state) { in musb_stage0_irq()
609 * this silicon doesn't report ID-no-longer-grounded. in musb_stage0_irq()
619 + msecs_to_jiffies(musb->a_wait_bcon in musb_stage0_irq()
624 if (!musb->is_active) in musb_stage0_irq()
628 musb->is_active = is_otg_enabled(musb) in musb_stage0_irq()
629 && musb->xceiv->gadget->b_hnp_enable; in musb_stage0_irq()
630 if (musb->is_active) { in musb_stage0_irq()
631 musb->xceiv->state = OTG_STATE_B_WAIT_ACON; in musb_stage0_irq()
632 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n"); in musb_stage0_irq()
633 mod_timer(&musb->otg_timer, jiffies in musb_stage0_irq()
639 if (musb->a_wait_bcon != 0) in musb_stage0_irq()
641 + msecs_to_jiffies(musb->a_wait_bcon)); in musb_stage0_irq()
644 musb->xceiv->state = OTG_STATE_A_SUSPEND; in musb_stage0_irq()
645 musb->is_active = is_otg_enabled(musb) in musb_stage0_irq()
646 && musb->xceiv->host->b_hnp_enable; in musb_stage0_irq()
650 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n"); in musb_stage0_irq()
654 musb->is_active = 0; in musb_stage0_irq()
663 musb->is_active = 1; in musb_stage0_irq()
665 musb->ep0_stage = MUSB_EP0_START; in musb_stage0_irq()
671 musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask); in musb_stage0_irq()
672 musb_writew(musb->mregs, MUSB_INTRRXE, musb->epmask & 0xfffe); in musb_stage0_irq()
673 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7); in musb_stage0_irq()
674 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED in musb_stage0_irq()
678 musb->port1_status |= USB_PORT_STAT_CONNECTION in musb_stage0_irq()
683 musb->port1_status |= USB_PORT_STAT_LOW_SPEED; in musb_stage0_irq()
686 switch (musb->xceiv->state) { in musb_stage0_irq()
689 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n"); in musb_stage0_irq()
693 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n"); in musb_stage0_irq()
696 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n"); in musb_stage0_irq()
698 musb->xceiv->state = OTG_STATE_B_HOST; in musb_stage0_irq()
699 hcd->self.is_b_host = 1; in musb_stage0_irq()
700 musb->ignore_disconnect = 0; in musb_stage0_irq()
701 del_timer(&musb->otg_timer); in musb_stage0_irq()
706 musb->xceiv->state = OTG_STATE_A_HOST; in musb_stage0_irq()
707 hcd->self.is_b_host = 0; in musb_stage0_irq()
714 if (hcd->status_urb) in musb_stage0_irq()
719 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n", in musb_stage0_irq()
720 otg_state_string(musb->xceiv->state), devctl); in musb_stage0_irq()
723 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) { in musb_stage0_irq()
724 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n", in musb_stage0_irq()
725 otg_state_string(musb->xceiv->state), in musb_stage0_irq()
729 switch (musb->xceiv->state) { in musb_stage0_irq()
734 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb)) in musb_stage0_irq()
736 + msecs_to_jiffies(musb->a_wait_bcon)); in musb_stage0_irq()
745 musb_to_hcd(musb)->self.is_b_host = 0; in musb_stage0_irq()
746 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; in musb_stage0_irq()
762 otg_state_string(musb->xceiv->state)); in musb_stage0_irq()
774 * Looks like non-HS BABBLE can be ignored, but in musb_stage0_irq()
781 dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl); in musb_stage0_irq()
783 ERR("Stopping host session -- babble\n"); in musb_stage0_irq()
784 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); in musb_stage0_irq()
787 dev_dbg(musb->controller, "BUS RESET as %s\n", in musb_stage0_irq()
788 otg_state_string(musb->xceiv->state)); in musb_stage0_irq()
789 switch (musb->xceiv->state) { in musb_stage0_irq()
795 musb->ignore_disconnect = 1; in musb_stage0_irq()
798 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */ in musb_stage0_irq()
800 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n", in musb_stage0_irq()
801 otg_state_string(musb->xceiv->state), in musb_stage0_irq()
803 mod_timer(&musb->otg_timer, jiffies in musb_stage0_irq()
807 musb->ignore_disconnect = 0; in musb_stage0_irq()
808 del_timer(&musb->otg_timer); in musb_stage0_irq()
812 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n", in musb_stage0_irq()
813 otg_state_string(musb->xceiv->state)); in musb_stage0_irq()
814 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; in musb_stage0_irq()
818 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; in musb_stage0_irq()
824 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n", in musb_stage0_irq()
825 otg_state_string(musb->xceiv->state)); in musb_stage0_irq()
843 void __iomem *mbase = musb->mregs; in musb_stage0_irq()
848 dev_dbg(musb->controller, "START_OF_FRAME\n"); in musb_stage0_irq()
853 ep = musb->endpoints; in musb_stage0_irq()
854 for (epnum = 1; (epnum < musb->nr_endpoints) in musb_stage0_irq()
855 && (musb->epmask >= (1 << epnum)); in musb_stage0_irq()
861 if (ep->dwWaitFrame >= frame) { in musb_stage0_irq()
862 ep->dwWaitFrame = 0; in musb_stage0_irq()
863 pr_debug("SOF --> periodic TX%s on %d\n", in musb_stage0_irq()
864 ep->tx_channel ? " DMA" : "", in musb_stage0_irq()
866 if (!ep->tx_channel) in musb_stage0_irq()
875 schedule_work(&musb->irq_work); in musb_stage0_irq()
880 /*-------------------------------------------------------------------------*/
887 void __iomem *regs = musb->mregs; in musb_start()
890 dev_dbg(musb->controller, "<== devctl %02x\n", devctl); in musb_start()
893 musb_writew(regs, MUSB_INTRTXE, musb->epmask); in musb_start()
894 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe); in musb_start()
906 musb->is_active = 0; in musb_start()
912 * (a) ID-grounded irq, host mode; in musb_start()
917 musb->is_active = 1; in musb_start()
922 /* assume ID pin is hard-wired to ground */ in musb_start()
927 musb->is_active = 1; in musb_start()
936 void __iomem *mbase = musb->mregs; in musb_generic_disable()
966 dev_dbg(musb->controller, "HDRC disabled\n"); in musb_stop()
969 * - mark host and/or peripheral drivers unusable/inactive in musb_stop()
970 * - disable DMA (and enable it in HdrcStart) in musb_stop()
971 * - make sure we can musb_start() after musb_stop(); with in musb_stop()
973 * - ... in musb_stop()
980 struct musb *musb = dev_to_musb(&pdev->dev); in musb_shutdown()
983 pm_runtime_get_sync(musb->controller); in musb_shutdown()
987 spin_lock_irqsave(&musb->lock, flags); in musb_shutdown()
990 spin_unlock_irqrestore(&musb->lock, flags); in musb_shutdown()
994 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); in musb_shutdown()
997 pm_runtime_put(musb->controller); in musb_shutdown()
1002 /*-------------------------------------------------------------------------*/
1005 * The silicon either has hard-wired endpoint configurations, or else
1008 * away from compile-time hardware parameters, we can no longer rely on
1037 /* mode 0 - fits in 2KB */
1046 /* mode 1 - fits in 4KB */
1055 /* mode 2 - fits in 4KB */
1065 /* mode 3 - fits in 4KB */
1075 /* mode 4 - fits in 16KB */
1106 /* mode 5 - fits in 8KB */
1138 * configure a fifo; for non-shared endpoints, this may be called
1147 void __iomem *mbase = musb->mregs; in fifo_setup()
1149 u16 maxpacket = cfg->maxpacket; in fifo_setup()
1153 /* expect hw_ep has already been zero-initialized */ in fifo_setup()
1155 size = ffs(max(maxpacket, (u16) 8)) - 1; in fifo_setup()
1158 c_size = size - 3; in fifo_setup()
1159 if (cfg->mode == BUF_DOUBLE) { in fifo_setup()
1161 (1 << (musb->config->ram_bits + 2))) in fifo_setup()
1162 return -EMSGSIZE; in fifo_setup()
1165 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2))) in fifo_setup()
1166 return -EMSGSIZE; in fifo_setup()
1170 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum); in fifo_setup()
1175 if (hw_ep->epnum == 1) in fifo_setup()
1176 musb->bulk_ep = hw_ep; in fifo_setup()
1178 switch (cfg->style) { in fifo_setup()
1182 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); in fifo_setup()
1183 hw_ep->max_packet_sz_tx = maxpacket; in fifo_setup()
1188 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); in fifo_setup()
1189 hw_ep->max_packet_sz_rx = maxpacket; in fifo_setup()
1194 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); in fifo_setup()
1195 hw_ep->max_packet_sz_rx = maxpacket; in fifo_setup()
1199 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered; in fifo_setup()
1200 hw_ep->max_packet_sz_tx = maxpacket; in fifo_setup()
1202 hw_ep->is_shared_fifo = true; in fifo_setup()
1209 musb->epmask |= (1 << hw_ep->epnum); in fifo_setup()
1223 struct musb_hw_ep *hw_ep = musb->endpoints; in ep_config_from_table()
1225 if (musb->config->fifo_cfg) { in ep_config_from_table()
1226 cfg = musb->config->fifo_cfg; in ep_config_from_table()
1227 n = musb->config->fifo_cfg_size; in ep_config_from_table()
1270 * be better than static musb->config->num_eps and DYN_FIFO_SIZE... in ep_config_from_table()
1274 u8 epn = cfg->hw_ep_num; in ep_config_from_table()
1276 if (epn >= musb->config->num_eps) { in ep_config_from_table()
1279 return -EINVAL; in ep_config_from_table()
1285 return -EINVAL; in ep_config_from_table()
1288 musb->nr_endpoints = max(epn, musb->nr_endpoints); in ep_config_from_table()
1293 n + 1, musb->config->num_eps * 2 - 1, in ep_config_from_table()
1294 offset, (1 << (musb->config->ram_bits + 2))); in ep_config_from_table()
1296 if (!musb->bulk_ep) { in ep_config_from_table()
1298 return -EINVAL; in ep_config_from_table()
1306 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1313 void *mbase = musb->mregs; in ep_config_from_hw()
1316 dev_dbg(musb->controller, "<== static silicon ep config\n"); in ep_config_from_hw()
1320 for (epnum = 1; epnum < musb->config->num_eps; epnum++) { in ep_config_from_hw()
1322 hw_ep = musb->endpoints + epnum; in ep_config_from_hw()
1328 /* FIXME set up hw_ep->{rx,tx}_double_buffered */ in ep_config_from_hw()
1331 if (hw_ep->max_packet_sz_tx < 512 in ep_config_from_hw()
1332 || hw_ep->max_packet_sz_rx < 512) in ep_config_from_hw()
1338 if (musb->bulk_ep) in ep_config_from_hw()
1340 musb->bulk_ep = hw_ep; in ep_config_from_hw()
1343 if (!musb->bulk_ep) { in ep_config_from_hw()
1345 return -EINVAL; in ep_config_from_hw()
1361 void __iomem *mbase = musb->mregs; in musb_core_init()
1368 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8"); in musb_core_init()
1371 musb->dyn_fifo = true; in musb_core_init()
1375 musb->bulk_combine = true; in musb_core_init()
1379 musb->bulk_split = true; in musb_core_init()
1382 strcat(aInfo, ", HB-ISO Rx"); in musb_core_init()
1383 musb->hb_iso_rx = true; in musb_core_init()
1386 strcat(aInfo, ", HB-ISO Tx"); in musb_core_init()
1387 musb->hb_iso_tx = true; in musb_core_init()
1397 musb->is_multipoint = 1; in musb_core_init()
1400 musb->is_multipoint = 0; in musb_core_init()
1410 musb->hwvers = musb_read_hwvers(mbase); in musb_core_init()
1411 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers), in musb_core_init()
1412 MUSB_HWVERS_MINOR(musb->hwvers), in musb_core_init()
1413 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : ""); in musb_core_init()
1421 musb->nr_endpoints = 1; in musb_core_init()
1422 musb->epmask = 1; in musb_core_init()
1424 if (musb->dyn_fifo) in musb_core_init()
1433 for (i = 0; i < musb->nr_endpoints; i++) { in musb_core_init()
1434 struct musb_hw_ep *hw_ep = musb->endpoints + i; in musb_core_init()
1436 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase; in musb_core_init()
1438 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i); in musb_core_init()
1439 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i); in musb_core_init()
1440 hw_ep->fifo_sync_va = in musb_core_init()
1441 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i); in musb_core_init()
1444 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF; in musb_core_init()
1446 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2); in musb_core_init()
1449 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase; in musb_core_init()
1450 hw_ep->target_regs = musb_read_target_reg_base(i, mbase); in musb_core_init()
1451 hw_ep->rx_reinit = 1; in musb_core_init()
1452 hw_ep->tx_reinit = 1; in musb_core_init()
1454 if (hw_ep->max_packet_sz_tx) { in musb_core_init()
1455 dev_dbg(musb->controller, in musb_core_init()
1458 hw_ep->is_shared_fifo ? "shared" : "tx", in musb_core_init()
1459 hw_ep->tx_double_buffered in musb_core_init()
1461 hw_ep->max_packet_sz_tx); in musb_core_init()
1463 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) { in musb_core_init()
1464 dev_dbg(musb->controller, in musb_core_init()
1468 hw_ep->rx_double_buffered in musb_core_init()
1470 hw_ep->max_packet_sz_rx); in musb_core_init()
1472 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx)) in musb_core_init()
1473 dev_dbg(musb->controller, "hw_ep %d not configured\n", i); in musb_core_init()
1479 /*-------------------------------------------------------------------------*/
1490 spin_lock_irqsave(&musb->lock, flags); in generic_interrupt()
1492 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB); in generic_interrupt()
1493 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX); in generic_interrupt()
1494 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX); in generic_interrupt()
1496 if (musb->int_usb || musb->int_tx || musb->int_rx) in generic_interrupt()
1499 spin_unlock_irqrestore(&musb->lock, flags); in generic_interrupt()
1510 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1522 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); in musb_interrupt()
1523 power = musb_readb(musb->mregs, MUSB_POWER); in musb_interrupt()
1525 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n", in musb_interrupt()
1527 musb->int_usb, musb->int_tx, musb->int_rx); in musb_interrupt()
1532 if (musb->int_usb) in musb_interrupt()
1533 retval |= musb_stage0_irq(musb, musb->int_usb, in musb_interrupt()
1539 if (musb->int_tx & 1) { in musb_interrupt()
1546 /* RX on endpoints 1-15 */ in musb_interrupt()
1547 reg = musb->int_rx >> 1; in musb_interrupt()
1551 /* musb_ep_select(musb->mregs, ep_num); */ in musb_interrupt()
1552 /* REVISIT just retval = ep->rx_irq(...) */ in musb_interrupt()
1567 /* TX on endpoints 1-15 */ in musb_interrupt()
1568 reg = musb->int_tx >> 1; in musb_interrupt()
1572 /* musb_ep_select(musb->mregs, ep_num); */ in musb_interrupt()
1573 /* REVISIT just retval |= ep->tx_irq(...) */ in musb_interrupt()
1600 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); in musb_dma_completion()
1642 /*-------------------------------------------------------------------------*/
1651 int ret = -EINVAL; in musb_mode_show()
1653 spin_lock_irqsave(&musb->lock, flags); in musb_mode_show()
1654 ret = sprintf(buf, "%s\n", otg_state_string(musb->xceiv->state)); in musb_mode_show()
1655 spin_unlock_irqrestore(&musb->lock, flags); in musb_mode_show()
1668 spin_lock_irqsave(&musb->lock, flags); in musb_mode_store()
1676 status = -EINVAL; in musb_mode_store()
1677 spin_unlock_irqrestore(&musb->lock, flags); in musb_mode_store()
1693 return -EINVAL; in musb_vbus_store()
1696 spin_lock_irqsave(&musb->lock, flags); in musb_vbus_store()
1698 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ; in musb_vbus_store()
1699 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON) in musb_vbus_store()
1700 musb->is_active = 0; in musb_vbus_store()
1702 spin_unlock_irqrestore(&musb->lock, flags); in musb_vbus_store()
1715 spin_lock_irqsave(&musb->lock, flags); in musb_vbus_show()
1716 val = musb->a_wait_bcon; in musb_vbus_show()
1718 * and is effectively TUSB-specific. in musb_vbus_show()
1721 spin_unlock_irqrestore(&musb->lock, flags); in musb_vbus_show()
1741 return -EINVAL; in musb_srp_store()
1770 if (musb->xceiv->state != old_state) { in musb_irq_work()
1771 old_state = musb->xceiv->state; in musb_irq_work()
1772 sysfs_notify(&musb->controller->kobj, NULL, "mode"); in musb_irq_work()
1776 /* --------------------------------------------------------------------------
1792 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */ in allocate_instance()
1795 INIT_LIST_HEAD(&musb->control); in allocate_instance()
1796 INIT_LIST_HEAD(&musb->in_bulk); in allocate_instance()
1797 INIT_LIST_HEAD(&musb->out_bulk); in allocate_instance()
1799 hcd->uses_new_polling = 1; in allocate_instance()
1800 hcd->has_tt = 1; in allocate_instance()
1802 musb->vbuserr_retry = VBUSERR_RETRY_COUNT; in allocate_instance()
1803 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON; in allocate_instance()
1805 musb->mregs = mbase; in allocate_instance()
1806 musb->ctrl_base = mbase; in allocate_instance()
1807 musb->nIrq = -ENODEV; in allocate_instance()
1808 musb->config = config; in allocate_instance()
1809 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS); in allocate_instance()
1810 for (epnum = 0, ep = musb->endpoints; in allocate_instance()
1811 epnum < musb->config->num_eps; in allocate_instance()
1813 ep->musb = musb; in allocate_instance()
1814 ep->epnum = epnum; in allocate_instance()
1817 musb->controller = dev; in allocate_instance()
1826 * cleanup after everything's been de-activated. in musb_free()
1830 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group); in musb_free()
1833 if (musb->nIrq >= 0) { in musb_free()
1834 if (musb->irq_wake) in musb_free()
1835 disable_irq_wake(musb->nIrq); in musb_free()
1836 free_irq(musb->nIrq, musb); in musb_free()
1838 if (is_dma_capable() && musb->dma_controller) { in musb_free()
1839 struct dma_controller *c = musb->dma_controller; in musb_free()
1841 (void) c->stop(c); in musb_free()
1849 * Perform generic per-controller initialization.
1854 * not yet corrected for platform-specific offsets
1861 struct musb_hdrc_platform_data *plat = dev->platform_data; in musb_init_controller()
1868 status = -ENODEV; in musb_init_controller()
1873 musb = allocate_instance(dev, plat->config, ctrl); in musb_init_controller()
1875 status = -ENOMEM; in musb_init_controller()
1879 pm_runtime_use_autosuspend(musb->controller); in musb_init_controller()
1880 pm_runtime_set_autosuspend_delay(musb->controller, 200); in musb_init_controller()
1881 pm_runtime_enable(musb->controller); in musb_init_controller()
1883 spin_lock_init(&musb->lock); in musb_init_controller()
1884 musb->board_mode = plat->mode; in musb_init_controller()
1885 musb->board_set_power = plat->set_power; in musb_init_controller()
1886 musb->min_power = plat->min_power; in musb_init_controller()
1887 musb->ops = plat->platform_ops; in musb_init_controller()
1890 * - adjusts musb->mregs and musb->isr if needed, in musb_init_controller()
1891 * - may initialize an integrated tranceiver in musb_init_controller()
1892 * - initializes musb->xceiv, usually by otg_get_transceiver() in musb_init_controller()
1893 * - stops powering VBUS in musb_init_controller()
1898 * isp1504, non-OTG, etc) mostly hooking up through ULPI. in musb_init_controller()
1900 musb->isr = generic_interrupt; in musb_init_controller()
1905 if (!musb->isr) { in musb_init_controller()
1906 status = -ENODEV; in musb_init_controller()
1910 if (!musb->xceiv->io_ops) { in musb_init_controller()
1911 musb->xceiv->io_priv = musb->mregs; in musb_init_controller()
1912 musb->xceiv->io_ops = &musb_ulpi_access; in musb_init_controller()
1916 if (use_dma && dev->dma_mask) { in musb_init_controller()
1919 c = dma_controller_create(musb, musb->mregs); in musb_init_controller()
1920 musb->dma_controller = c; in musb_init_controller()
1922 (void) c->start(c); in musb_init_controller()
1926 if (!is_dma_capable() || !musb->dma_controller) in musb_init_controller()
1927 dev->dma_mask = NULL; in musb_init_controller()
1934 status = musb_core_init(plat->config->multipoint in musb_init_controller()
1940 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb); in musb_init_controller()
1943 INIT_WORK(&musb->irq_work, musb_irq_work); in musb_init_controller()
1946 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) { in musb_init_controller()
1948 status = -ENODEV; in musb_init_controller()
1951 musb->nIrq = nIrq; in musb_init_controller()
1954 musb->irq_wake = 1; in musb_init_controller()
1957 musb->irq_wake = 0; in musb_init_controller()
1964 otg_set_host(musb->xceiv, &hcd->self); in musb_init_controller()
1967 hcd->self.otg_port = 1; in musb_init_controller()
1968 musb->xceiv->host = &hcd->self; in musb_init_controller()
1969 hcd->power_budget = 2 * (plat->power ? : 250); in musb_init_controller()
1972 if (plat->extvbus) { in musb_init_controller()
1973 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs); in musb_init_controller()
1975 musb_write_ulpi_buscontrol(musb->mregs, busctl); in musb_init_controller()
1979 /* For the host-only role, we can activate right away. in musb_init_controller()
1987 musb->xceiv->default_a = 1; in musb_init_controller()
1988 musb->xceiv->state = OTG_STATE_A_IDLE; in musb_init_controller()
1990 status = usb_add_hcd(musb_to_hcd(musb), -1, 0); in musb_init_controller()
1992 hcd->self.uses_pio_for_control = 1; in musb_init_controller()
1993 dev_dbg(musb->controller, "%s mode, status %d, devctl %02x %c\n", in musb_init_controller()
1995 musb_readb(musb->mregs, MUSB_DEVCTL), in musb_init_controller()
1996 (musb_readb(musb->mregs, MUSB_DEVCTL) in musb_init_controller()
2002 musb->xceiv->default_a = 0; in musb_init_controller()
2003 musb->xceiv->state = OTG_STATE_B_IDLE; in musb_init_controller()
2007 dev_dbg(musb->controller, "%s mode, status %d, dev%02x\n", in musb_init_controller()
2010 musb_readb(musb->mregs, MUSB_DEVCTL)); in musb_init_controller()
2021 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group); in musb_init_controller()
2028 switch (musb->board_mode) { in musb_init_controller()
2034 (is_dma_capable() && musb->dma_controller) in musb_init_controller()
2036 musb->nIrq); in musb_init_controller()
2050 if (musb->irq_wake) in musb_init_controller()
2055 dev_err(musb->controller, in musb_init_controller()
2066 /*-------------------------------------------------------------------------*/
2068 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2069 * bridge to a platform device; this driver then suffices.
2078 struct device *dev = &pdev->dev; in musb_probe()
2086 return -ENODEV; in musb_probe()
2088 base = ioremap(iomem->start, resource_size(iomem)); in musb_probe()
2091 return -ENOMEM; in musb_probe()
2096 orig_dma_mask = dev->dma_mask; in musb_probe()
2107 struct musb *musb = dev_to_musb(&pdev->dev); in musb_remove()
2108 void __iomem *ctrl_base = musb->ctrl_base; in musb_remove()
2111 * - Host mode: host may still be active in musb_remove()
2112 * - Peripheral mode: peripheral is deactivated (or never-activated) in musb_remove()
2113 * - OTG mode: both roles are deactivated (or never-activated) in musb_remove()
2115 pm_runtime_get_sync(musb->controller); in musb_remove()
2119 pm_runtime_put(musb->controller); in musb_remove()
2122 device_init_wakeup(&pdev->dev, 0); in musb_remove()
2124 pdev->dev.dma_mask = orig_dma_mask; in musb_remove()
2134 void __iomem *musb_base = musb->mregs; in musb_save_context()
2138 musb->context.frame = musb_readw(musb_base, MUSB_FRAME); in musb_save_context()
2139 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE); in musb_save_context()
2140 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs); in musb_save_context()
2142 musb->context.power = musb_readb(musb_base, MUSB_POWER); in musb_save_context()
2143 musb->context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE); in musb_save_context()
2144 musb->context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE); in musb_save_context()
2145 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE); in musb_save_context()
2146 musb->context.index = musb_readb(musb_base, MUSB_INDEX); in musb_save_context()
2147 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL); in musb_save_context()
2149 for (i = 0; i < musb->config->num_eps; ++i) { in musb_save_context()
2152 hw_ep = &musb->endpoints[i]; in musb_save_context()
2156 epio = hw_ep->regs; in musb_save_context()
2161 musb->context.index_regs[i].txmaxp = in musb_save_context()
2163 musb->context.index_regs[i].txcsr = in musb_save_context()
2165 musb->context.index_regs[i].rxmaxp = in musb_save_context()
2167 musb->context.index_regs[i].rxcsr = in musb_save_context()
2170 if (musb->dyn_fifo) { in musb_save_context()
2171 musb->context.index_regs[i].txfifoadd = in musb_save_context()
2173 musb->context.index_regs[i].rxfifoadd = in musb_save_context()
2175 musb->context.index_regs[i].txfifosz = in musb_save_context()
2177 musb->context.index_regs[i].rxfifosz = in musb_save_context()
2181 musb->context.index_regs[i].txtype = in musb_save_context()
2183 musb->context.index_regs[i].txinterval = in musb_save_context()
2185 musb->context.index_regs[i].rxtype = in musb_save_context()
2187 musb->context.index_regs[i].rxinterval = in musb_save_context()
2190 musb->context.index_regs[i].txfunaddr = in musb_save_context()
2192 musb->context.index_regs[i].txhubaddr = in musb_save_context()
2194 musb->context.index_regs[i].txhubport = in musb_save_context()
2197 musb->context.index_regs[i].rxfunaddr = in musb_save_context()
2199 musb->context.index_regs[i].rxhubaddr = in musb_save_context()
2201 musb->context.index_regs[i].rxhubport = in musb_save_context()
2210 void __iomem *musb_base = musb->mregs; in musb_restore_context()
2215 musb_writew(musb_base, MUSB_FRAME, musb->context.frame); in musb_restore_context()
2216 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode); in musb_restore_context()
2217 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl); in musb_restore_context()
2219 musb_writeb(musb_base, MUSB_POWER, musb->context.power); in musb_restore_context()
2220 musb_writew(musb_base, MUSB_INTRTXE, musb->context.intrtxe); in musb_restore_context()
2221 musb_writew(musb_base, MUSB_INTRRXE, musb->context.intrrxe); in musb_restore_context()
2222 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe); in musb_restore_context()
2223 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl); in musb_restore_context()
2225 for (i = 0; i < musb->config->num_eps; ++i) { in musb_restore_context()
2228 hw_ep = &musb->endpoints[i]; in musb_restore_context()
2232 epio = hw_ep->regs; in musb_restore_context()
2238 musb->context.index_regs[i].txmaxp); in musb_restore_context()
2240 musb->context.index_regs[i].txcsr); in musb_restore_context()
2242 musb->context.index_regs[i].rxmaxp); in musb_restore_context()
2244 musb->context.index_regs[i].rxcsr); in musb_restore_context()
2246 if (musb->dyn_fifo) { in musb_restore_context()
2248 musb->context.index_regs[i].txfifosz); in musb_restore_context()
2250 musb->context.index_regs[i].rxfifosz); in musb_restore_context()
2252 musb->context.index_regs[i].txfifoadd); in musb_restore_context()
2254 musb->context.index_regs[i].rxfifoadd); in musb_restore_context()
2259 musb->context.index_regs[i].txtype); in musb_restore_context()
2261 musb->context.index_regs[i].txinterval); in musb_restore_context()
2263 musb->context.index_regs[i].rxtype); in musb_restore_context()
2266 musb->context.index_regs[i].rxinterval); in musb_restore_context()
2268 musb->context.index_regs[i].txfunaddr); in musb_restore_context()
2270 musb->context.index_regs[i].txhubaddr); in musb_restore_context()
2272 musb->context.index_regs[i].txhubport); in musb_restore_context()
2278 musb->context.index_regs[i].rxfunaddr); in musb_restore_context()
2280 musb->context.index_regs[i].rxhubaddr); in musb_restore_context()
2282 musb->context.index_regs[i].rxhubport); in musb_restore_context()
2285 musb_writeb(musb_base, MUSB_INDEX, musb->context.index); in musb_restore_context()
2293 spin_lock_irqsave(&musb->lock, flags); in musb_suspend()
2301 * they will even be wakeup-enabled. in musb_suspend()
2305 spin_unlock_irqrestore(&musb->lock, flags); in musb_suspend()
2371 /*-------------------------------------------------------------------------*/
2387 * and before usb gadget and host-side drivers start to register