45 #define ep_dir(ep)	(((ep)->ep_num == 0) ? \
72 /* for endpoint 0 operations */
76 	.bEndpointAddress =	0,
85 	int i = 0;  in ep0_reset()
88 	for (i = 0; i < 2; i++) {  in ep0_reset()
102 		epctrlx = readl(&udc->op_regs->epctrlx[0]);  in ep0_reset()
114 		writel(epctrlx, &udc->op_regs->epctrlx[0]);  in ep0_reset()
124 	epctrlx = readl(&udc->op_regs->epctrlx[0]);  in ep0_stall()
126 	writel(epctrlx, &udc->op_regs->epctrlx[0]);  in ep0_stall()
140 	int retval = 0;  in process_ep_req()
148 	td_complete = 0;  in process_ep_req()
151 	for (i = 0; i < curr_req->dtd_count; i++) {  in process_ep_req()
176 				"complete_tr error: ep=%d %s: error = 0x%x\n",  in process_ep_req()
211 	return 0;  in process_ep_req()
238 	for (j = 0; j < req->dtd_count; j++) {  in done()
251 		req->mapped = 0;  in done()
284 	int retval = 0;  in queue_dtd()
289 	bit_pos = 1 << (((direction == EP_DIR_OUT) ? 0 : 16) + ep->ep_num);  in queue_dtd()
325 			if (loops == 0) {  in queue_dtd()
343 	/* Write dQH next pointer and terminate bit to 0 */  in queue_dtd()
386 	temp &= ~0xFFF;  in build_dtd()
387 	dtd->buff_ptr1 = cpu_to_le32(temp + 0x1000);  in build_dtd()
388 	dtd->buff_ptr2 = cpu_to_le32(temp + 0x2000);  in build_dtd()
389 	dtd->buff_ptr3 = cpu_to_le32(temp + 0x3000);  in build_dtd()
390 	dtd->buff_ptr4 = cpu_to_le32(temp + 0x4000);  in build_dtd()
396 		if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)  in build_dtd()
399 			*is_last = 0;  in build_dtd()
403 		*is_last = 0;  in build_dtd()
436 			is_first = 0;  in req_to_dtd()
451 	return 0;  in req_to_dtd()
460 	u16 max = 0;  in mv_ep_enable()
462 	unsigned char zlt = 0, ios = 0, mult = 0;  in mv_ep_enable()
484 	bit_pos = 1 << ((direction == EP_DIR_OUT ? 0 : 16) + ep->ep_num);  in mv_ep_enable()
490 			"ep=%d %s: Init ERROR: ENDPTPRIME=0x%x,"  in mv_ep_enable()
491 			" ENDPTSTATUS=0x%x, bit_pos=0x%x\n",  in mv_ep_enable()
502 		mult = 0;  in mv_ep_enable()
507 		mult = 0;  in mv_ep_enable()
511 		mult = (unsigned char)(1 + ((max >> 11) & 0x03));  in mv_ep_enable()
512 		max = max & 0x7ff;	/* bit 0~10 */  in mv_ep_enable()
526 		| (zlt ? EP_QUEUE_HEAD_ZLT_SEL : 0)  in mv_ep_enable()
527 		| (ios ? EP_QUEUE_HEAD_IOS : 0);  in mv_ep_enable()
529 	dqh->size_ioc_int_sts = 0;  in mv_ep_enable()
533 	ep->stopped = 0;  in mv_ep_enable()
555 	if ((epctrlx & EPCTRL_RX_ENABLE) == 0) {  in mv_ep_enable()
562 	if ((epctrlx & EPCTRL_TX_ENABLE) == 0) {  in mv_ep_enable()
570 	return 0;  in mv_ep_enable()
595 	bit_pos = 1 << ((direction == EP_DIR_OUT ? 0 : 16) + ep->ep_num);  in mv_ep_disable()
598 	dqh->max_packet_length = 0;  in mv_ep_disable()
615 	return 0;  in mv_ep_disable()
660 	if (ep->ep_num == 0)  in mv_ep_fifo_flush()
671 		if (loops == 0) {  in mv_ep_fifo_flush()
673 				"TIMEOUT for ENDPTSTATUS=0x%x, bit_pos=0x%x\n",  in mv_ep_fifo_flush()
688 			if (inter_loops == 0) {  in mv_ep_fifo_flush()
690 					"TIMEOUT for ENDPTFLUSH=0x%x,"  in mv_ep_fifo_flush()
691 					"bit_pos=0x%x\n",  in mv_ep_fifo_flush()
747 		req->mapped = 0;  in mv_ep_queue()
751 	req->req.actual = 0;  in mv_ep_queue()
752 	req->dtd_count = 0;  in mv_ep_queue()
770 	if (ep->ep_num == 0)  in mv_ep_queue()
778 	return 0;  in mv_ep_queue()
786 	/* Write dQH next pointer and terminate bit to 0 */  in mv_prime_ep()
796 	bit_pos = 1 << (((ep_dir(ep) == EP_DIR_OUT) ? 0 : 16) + ep->ep_num);  in mv_prime_ep()
809 	int stopped, ret = 0;  in mv_ep_dequeue()
856 			qh->size_ioc_int_sts = 0;  in mv_ep_dequeue()
915 		return (epctrlx & EPCTRL_RX_EP_STALL) ? 1 : 0;  in ep_is_stall()
917 		return (epctrlx & EPCTRL_TX_EP_STALL) ? 1 : 0;  in ep_is_stall()
923 	unsigned long flags = 0;  in mv_ep_set_halt_wedge()
924 	int status = 0;  in mv_ep_set_halt_wedge()
953 		ep->wedge = 0;  in mv_ep_set_halt_wedge()
956 	if (ep->ep_num == 0) {  in mv_ep_set_halt_wedge()
966 	return mv_ep_set_halt_wedge(_ep, halt, 0);  in mv_ep_set_halt()
993 	for (i = 0; i < udc->clknum; i++)  in udc_clock_enable()
1001 	for (i = 0; i < udc->clknum; i++)  in udc_clock_disable()
1033 	udc->stopped = 0;  in udc_start()
1055 		if (loops == 0) {  in udc_reset()
1073 	writel(0x0, &udc->op_regs->epsetupstat);  in udc_reset()
1079 	portsc = readl(&udc->op_regs->portsc[0]);  in udc_reset()
1088 	writel(portsc, &udc->op_regs->portsc[0]);  in udc_reset()
1090 	tmp = readl(&udc->op_regs->epctrlx[0]);  in udc_reset()
1092 	writel(tmp, &udc->op_regs->epctrlx[0]);  in udc_reset()
1094 	return 0;  in udc_reset()
1102 		return 0;  in mv_udc_enable_internal()
1117 	return 0;  in mv_udc_enable_internal()
1125 	return 0;  in mv_udc_enable()
1135 		udc->active = 0;  in mv_udc_disable_internal()
1173 		return 0;  in mv_udc_wakeup()
1176 	writel(portsc, &udc->op_regs->portsc[0]);  in mv_udc_wakeup()
1177 	return 0;  in mv_udc_wakeup()
1184 	int retval = 0;  in mv_udc_vbus_session()
1189 	udc->vbus_active = (is_active != 0);  in mv_udc_vbus_session()
1196 		if (retval == 0) {  in mv_udc_vbus_session()
1217 	int retval = 0;  in mv_udc_pullup()
1222 	udc->softconnect = (is_on != 0);  in mv_udc_pullup()
1229 		if (retval == 0) {  in mv_udc_pullup()
1274 	ep = &udc->eps[0];  in eps_init()
1279 	ep->wedge = 0;  in eps_init()
1280 	ep->stopped = 0;  in eps_init()
1282 	ep->ep_num = 0;  in eps_init()
1303 		ep->stopped = 0;  in eps_init()
1304 		ep->ep.maxpacket = (unsigned short) ~0;  in eps_init()
1313 	return 0;  in eps_init()
1337 	nuke(&udc->eps[0], -ESHUTDOWN);  in stop_activity()
1355 	int retval = 0;  in mv_udc_start()
1407 	return 0;  in mv_udc_start()
1435 	return 0;  in mv_udc_stop()
1442 	portsc = readl(&udc->op_regs->portsc[0]);  in mv_set_ptc()
1444 	writel(portsc, &udc->op_regs->portsc[0]);  in mv_set_ptc()
1458 		req->test_mode = 0;  in prime_status_complete()
1466 	int retval = 0;  in udc_prime_status()
1470 	ep = &udc->eps[0];  in udc_prime_status()
1481 		req->req.length = 0;  in udc_prime_status()
1485 	req->req.actual = 0;  in udc_prime_status()
1489 		udc->test_mode = 0;  in udc_prime_status()
1492 	req->dtd_count = 0;  in udc_prime_status()
1516 	return 0;  in udc_prime_status()
1525 		if (udc_prime_status(udc, EP_DIR_IN, 0, true))  in mv_udc_testmode()
1539 	if (udc_prime_status(udc, EP_DIR_IN, 0, true))  in ch9setaddress()
1546 	u16 status = 0;  in ch9getstatus()
1559 		status = 0;  in ch9getstatus()
1588 			udc->remote_wakeup = 0;  in ch9clearfeature()
1600 			if (setup->wValue != 0 || setup->wLength != 0  in ch9clearfeature()
1607 			ep_set_stall(udc, ep_num, direction, 0);  in ch9clearfeature()
1616 	if (udc_prime_status(udc, EP_DIR_IN, 0, true))  in ch9clearfeature()
1634 			if (setup->wIndex & 0xFF  in ch9setfeature()
1655 			if (setup->wValue != 0 || setup->wLength != 0  in ch9setfeature()
1668 	if (udc_prime_status(udc, EP_DIR_IN, 0, true))  in ch9setfeature()
1718 				&udc->local_setup_buff) < 0)  in handle_setup_packet()
1728 				&udc->local_setup_buff) < 0)  in handle_setup_packet()
1749 	done(ep0, req, 0);  in ep0_req_complete()
1754 		if (udc_prime_status(udc, EP_DIR_OUT, 0, true))  in ep0_req_complete()
1759 		if (udc_prime_status(udc, EP_DIR_IN, 0 , true))  in ep0_req_complete()
1802 	int i, ep_num = 0, direction = 0;  in irq_process_tr_complete()
1816 		for (i = 0; i < udc->max_eps; i++) {  in irq_process_tr_complete()
1838 	for (i = 0; i < udc->max_eps * 2; i++) {  in irq_process_tr_complete()
1848 			curr_ep = &udc->eps[0];  in irq_process_tr_complete()
1862 			if (ep_num == 0) {  in irq_process_tr_complete()
1879 	udc->remote_wakeup = 0;		/* default to 0 on reset */  in irq_process_reset()
1896 	while (readl(&udc->op_regs->epprime) & 0xFFFFFFFF) {  in irq_process_reset()
1897 		if (loops == 0) {  in irq_process_reset()
1899 				"Timeout for ENDPTPRIME = 0x%x\n",  in irq_process_reset()
1908 	writel((u32)~0, &udc->op_regs->epflush);  in irq_process_reset()
1910 	if (readl(&udc->op_regs->portsc[0]) & PORTSCX_PORT_RESET) {  in irq_process_reset()
1916 		dev_info(&udc->dev->dev, "USB reset portsc 0x%x\n",  in irq_process_reset()
1941 	udc->resume_state = 0;  in handle_bus_resume()
1969 	portsc = readl(&udc->op_regs->portsc[0]);  in irq_process_port_change()
2029 	if (status == 0) {  in mv_udc_irq()
2083 		mv_udc_vbus_session(&udc->gadget, 0);  in mv_udc_vbus_work()
2140 	for (clk_i = 0; clk_i <= udc->clknum; clk_i++)  in mv_udc_remove()
2151 	return 0;  in mv_udc_remove()
2158 	int retval = 0;  in mv_udc_probe()
2159 	int clk_i = 0;  in mv_udc_probe()
2188 	for (clk_i = 0; clk_i < udc->clknum; clk_i++) {  in mv_udc_probe()
2241 	writel(0xFFFFFFFF, &udc->op_regs->usbsts);  in mv_udc_probe()
2291 	udc->remote_wakeup = 0;  in mv_udc_probe()
2293 	r = platform_get_resource(udc->dev, IORESOURCE_IRQ, 0);  in mv_udc_probe()
2310 	udc->gadget.ep0 = &udc->eps[0].ep;	/* gadget ep0 */  in mv_udc_probe()
2339 			udc->clock_gating = 0;  in mv_udc_probe()
2369 	return 0;  in mv_udc_probe()
2395 	for (clk_i--; clk_i >= 0; clk_i--)  in mv_udc_probe()
2409 		return 0;  in mv_udc_suspend()
2432 	return 0;  in mv_udc_suspend()
2442 		return 0;  in mv_udc_resume()
2456 	return 0;  in mv_udc_resume()