Lines Matching defs:mgsl_struct

180 struct mgsl_struct {  struct
200 struct mgsl_struct *next_device; /* device list link */ argument
202 spinlock_t irq_spinlock; /* spinlock for synchronizing with ISR */
203 struct work_struct task; /* task structure for scheduling bh */
205 u32 EventMask; /* event trigger mask */
206 u32 RecordedEvents; /* pending events */
208 u32 max_frame_size; /* as set by device config */
210 u32 pending_bh;
212 bool bh_running; /* Protection from multiple */
213 int isr_overflow;
214 bool bh_requested;
216 int dcd_chkcount; /* check counts to prevent */
217 int cts_chkcount; /* too many IRQs if a signal */
218 int dsr_chkcount; /* is floating */
219 int ri_chkcount;
221 char *buffer_list; /* virtual address of Rx & Tx buffer lists */
222 u32 buffer_list_phys;
223 dma_addr_t buffer_list_dma_addr;
225 unsigned int rx_buffer_count; /* count of total allocated Rx buffers */
226 DMABUFFERENTRY *rx_buffer_list; /* list of receive buffer entries */
227 unsigned int current_rx_buffer;
229 int num_tx_dma_buffers; /* number of tx dma frames required */
230 int tx_dma_buffers_used;
231 unsigned int tx_buffer_count; /* count of total allocated Tx buffers */
232 DMABUFFERENTRY *tx_buffer_list; /* list of transmit buffer entries */
233 int start_tx_dma_buffer; /* tx dma buffer to start tx dma operation */
234 int current_tx_buffer; /* next tx dma buffer to be loaded */
236 unsigned char *intermediate_rxbuffer;
238 int num_tx_holding_buffers; /* number of tx holding buffer allocated */
239 int get_tx_holding_index; /* next tx holding buffer for adapter to load */
240 int put_tx_holding_index; /* next tx holding buffer to store user request */
241 int tx_holding_count; /* number of tx holding buffers waiting */
242 struct tx_holding_buffer tx_holding_buffers[MAX_TX_HOLDING_BUFFERS];
244 bool rx_enabled;
245 bool rx_overflow;
246 bool rx_rcc_underrun;
248 bool tx_enabled;
249 bool tx_active;
250 u32 idle_mode;
252 u16 cmr_value;
253 u16 tcsr_value;
255 char device_name[25]; /* device instance name */
257 unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
258 unsigned char bus; /* expansion bus number (zero based) */
259 unsigned char function; /* PCI device number */
261 unsigned int io_base; /* base I/O address of adapter */
262 unsigned int io_addr_size; /* size of the I/O address range */
263 bool io_addr_requested; /* true if I/O address requested */
265 unsigned int irq_level; /* interrupt level */
266 unsigned long irq_flags;
267 bool irq_requested; /* true if IRQ requested */
269 unsigned int dma_level; /* DMA channel */
270 bool dma_requested; /* true if dma channel requested */
272 u16 mbre_bit;
273 u16 loopback_bits;
274 u16 usc_idle_mode;
276 MGSL_PARAMS params; /* communications parameters */
278 unsigned char serial_signals; /* current serial signal states */
280 bool irq_occurred; /* for diagnostics use */
281 unsigned int init_error; /* Initialization startup error (DIAGS) */
282 int fDiagnosticsmode; /* Driver in Diagnostic mode? (DIAGS) */
284 u32 last_mem_alloc;
285 unsigned char* memory_base; /* shared memory address (PCI only) */
286 u32 phys_memory_base;
287 bool shared_mem_requested;
289 unsigned char* lcr_base; /* local config registers (PCI only) */
290 u32 phys_lcr_base;
291 u32 lcr_offset;
292 bool lcr_mem_requested;
294 u32 misc_ctrl_value;
295 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
296 char char_buf[MAX_ASYNC_BUFFER_SIZE];
297 bool drop_rts_on_tx_done;
299 bool loopmode_insert_requested;
300 bool loopmode_send_done_requested;
302 struct _input_signal_events input_signal_events;
305 int netcount;
306 spinlock_t netlock;
309 struct net_device *netdev;