tty/serial/max3107.h

2  * max3107.h - spi uart protocol driver header for Maxim 3107
24 /* GPIO definitions */
29 /* GPIO connected to chip's reset pin */
47 /* Definitions for register access with SPI transfers
49  * SPI transfer format:
62 /* SPI speed */
68 /* SPI TX data mask */
71 /* SPI RX data mask */
100 #define MAX3107_GPIOCFG_REG		(0x1800) /* GPIO config */
101 #define MAX3107_GPIODATA_REG		(0x1900) /* GPIO data */
135 #define MAX3107_SPCHR_MULTIDROP_BIT	(1 << 5) /* 9-bit multidrop addr char */
140 #define MAX3107_STS_GPIO0_BIT		(1 << 0) /* GPIO 0 interrupt */
141 #define MAX3107_STS_GPIO1_BIT		(1 << 1) /* GPIO 1 interrupt */
142 #define MAX3107_STS_GPIO2_BIT		(1 << 2) /* GPIO 2 interrupt */
143 #define MAX3107_STS_GPIO3_BIT		(1 << 3) /* GPIO 3 interrupt */
152 #define MAX3107_MODE1_TXHIZ_BIT		(1 << 2) /* TX pin three-state */
153 #define MAX3107_MODE1_RTSHIZ_BIT	(1 << 3) /* RTS pin three-state */
166 #define MAX3107_MODE2_MULTIDROP_BIT	(1 << 6) /* 9-bit multidrop enable */
174 						  * 00 -> 5 bit words
175 						  * 01 -> 6 bit words
176 						  * 10 -> 7 bit words
177 						  * 11 -> 8 bit words
182 						  * 0 -> 1 stop bit
183 						  * 1 -> 1-1.5 stop bits if
189 #define MAX3107_LCR_FORCEPARITY_BIT	(1 << 5) /* 9-bit multidrop parity */
223 #define MAX3107_FLOWCTRL_GPIADDR_BIT	(1 << 2) /* Enables that GPIO inputs
232 						  * 00 -> no transmitter flow
234 						  * 01 -> receiver compares
238 						  * 10 -> receiver compares
242 						  * 11 -> receiver compares
251 						  * 00 -> no received flow
253 						  * 01 -> transmitter generates
255 						  * 10 -> transmitter generates
257 						  * 11 -> transmitter generates
262 /* GPIO configuration register bits */
263 #define MAX3107_GPIOCFG_GP0OUT_BIT	(1 << 0) /* GPIO 0 output enable */
264 #define MAX3107_GPIOCFG_GP1OUT_BIT	(1 << 1) /* GPIO 1 output enable */
265 #define MAX3107_GPIOCFG_GP2OUT_BIT	(1 << 2) /* GPIO 2 output enable */
266 #define MAX3107_GPIOCFG_GP3OUT_BIT	(1 << 3) /* GPIO 3 output enable */
267 #define MAX3107_GPIOCFG_GP0OD_BIT	(1 << 4) /* GPIO 0 open-drain enable */
268 #define MAX3107_GPIOCFG_GP1OD_BIT	(1 << 5) /* GPIO 1 open-drain enable */
269 #define MAX3107_GPIOCFG_GP2OD_BIT	(1 << 6) /* GPIO 2 open-drain enable */
270 #define MAX3107_GPIOCFG_GP3OD_BIT	(1 << 7) /* GPIO 3 open-drain enable */
272 /* GPIO DATA register bits */
273 #define MAX3107_GPIODATA_GP0OUT_BIT	(1 << 0) /* GPIO 0 output value */
274 #define MAX3107_GPIODATA_GP1OUT_BIT	(1 << 1) /* GPIO 1 output value */
275 #define MAX3107_GPIODATA_GP2OUT_BIT	(1 << 2) /* GPIO 2 output value */
276 #define MAX3107_GPIODATA_GP3OUT_BIT	(1 << 3) /* GPIO 3 output value */
277 #define MAX3107_GPIODATA_GP0IN_BIT	(1 << 4) /* GPIO 0 input value */
278 #define MAX3107_GPIODATA_GP1IN_BIT	(1 << 5) /* GPIO 1 input value */
279 #define MAX3107_GPIODATA_GP2IN_BIT	(1 << 6) /* GPIO 2 input value */
280 #define MAX3107_GPIODATA_GP3IN_BIT	(1 << 7) /* GPIO 3 input value */
368 	/* SPI device structure */
369 	struct spi_device *spi;  member
372 	/* GPIO chip structure */
436 extern int max3107_probe(struct spi_device *spi, struct max3107_plat *pdata);
437 extern int max3107_remove(struct spi_device *spi);
438 extern int max3107_suspend(struct spi_device *spi, pm_message_t state);
439 extern int max3107_resume(struct spi_device *spi);