21 int ssb_watchdog_timer_set(struct ssb_bus *bus, u32 ticks)  in ssb_watchdog_timer_set()  argument
23 	if (ssb_chipco_available(&bus->chipco)) {  in ssb_watchdog_timer_set()
24 		ssb_chipco_watchdog_timer_set(&bus->chipco, ticks);  in ssb_watchdog_timer_set()
27 	if (ssb_extif_available(&bus->extif)) {  in ssb_watchdog_timer_set()
28 		ssb_extif_watchdog_timer_set(&bus->extif, ticks);  in ssb_watchdog_timer_set()
35 u32 ssb_gpio_in(struct ssb_bus *bus, u32 mask)  in ssb_gpio_in()  argument
40 	spin_lock_irqsave(&bus->gpio_lock, flags);  in ssb_gpio_in()
41 	if (ssb_chipco_available(&bus->chipco))  in ssb_gpio_in()
42 		res = ssb_chipco_gpio_in(&bus->chipco, mask);  in ssb_gpio_in()
43 	else if (ssb_extif_available(&bus->extif))  in ssb_gpio_in()
44 		res = ssb_extif_gpio_in(&bus->extif, mask);  in ssb_gpio_in()
47 	spin_unlock_irqrestore(&bus->gpio_lock, flags);  in ssb_gpio_in()
53 u32 ssb_gpio_out(struct ssb_bus *bus, u32 mask, u32 value)  in ssb_gpio_out()  argument
58 	spin_lock_irqsave(&bus->gpio_lock, flags);  in ssb_gpio_out()
59 	if (ssb_chipco_available(&bus->chipco))  in ssb_gpio_out()
60 		res = ssb_chipco_gpio_out(&bus->chipco, mask, value);  in ssb_gpio_out()
61 	else if (ssb_extif_available(&bus->extif))  in ssb_gpio_out()
62 		res = ssb_extif_gpio_out(&bus->extif, mask, value);  in ssb_gpio_out()
65 	spin_unlock_irqrestore(&bus->gpio_lock, flags);  in ssb_gpio_out()
71 u32 ssb_gpio_outen(struct ssb_bus *bus, u32 mask, u32 value)  in ssb_gpio_outen()  argument
76 	spin_lock_irqsave(&bus->gpio_lock, flags);  in ssb_gpio_outen()
77 	if (ssb_chipco_available(&bus->chipco))  in ssb_gpio_outen()
78 		res = ssb_chipco_gpio_outen(&bus->chipco, mask, value);  in ssb_gpio_outen()
79 	else if (ssb_extif_available(&bus->extif))  in ssb_gpio_outen()
80 		res = ssb_extif_gpio_outen(&bus->extif, mask, value);  in ssb_gpio_outen()
83 	spin_unlock_irqrestore(&bus->gpio_lock, flags);  in ssb_gpio_outen()
89 u32 ssb_gpio_control(struct ssb_bus *bus, u32 mask, u32 value)  in ssb_gpio_control()  argument
94 	spin_lock_irqsave(&bus->gpio_lock, flags);  in ssb_gpio_control()
95 	if (ssb_chipco_available(&bus->chipco))  in ssb_gpio_control()
96 		res = ssb_chipco_gpio_control(&bus->chipco, mask, value);  in ssb_gpio_control()
97 	spin_unlock_irqrestore(&bus->gpio_lock, flags);  in ssb_gpio_control()
103 u32 ssb_gpio_intmask(struct ssb_bus *bus, u32 mask, u32 value)  in ssb_gpio_intmask()  argument
108 	spin_lock_irqsave(&bus->gpio_lock, flags);  in ssb_gpio_intmask()
109 	if (ssb_chipco_available(&bus->chipco))  in ssb_gpio_intmask()
110 		res = ssb_chipco_gpio_intmask(&bus->chipco, mask, value);  in ssb_gpio_intmask()
111 	else if (ssb_extif_available(&bus->extif))  in ssb_gpio_intmask()
112 		res = ssb_extif_gpio_intmask(&bus->extif, mask, value);  in ssb_gpio_intmask()
115 	spin_unlock_irqrestore(&bus->gpio_lock, flags);  in ssb_gpio_intmask()
121 u32 ssb_gpio_polarity(struct ssb_bus *bus, u32 mask, u32 value)  in ssb_gpio_polarity()  argument
126 	spin_lock_irqsave(&bus->gpio_lock, flags);  in ssb_gpio_polarity()
127 	if (ssb_chipco_available(&bus->chipco))  in ssb_gpio_polarity()
128 		res = ssb_chipco_gpio_polarity(&bus->chipco, mask, value);  in ssb_gpio_polarity()
129 	else if (ssb_extif_available(&bus->extif))  in ssb_gpio_polarity()
130 		res = ssb_extif_gpio_polarity(&bus->extif, mask, value);  in ssb_gpio_polarity()
133 	spin_unlock_irqrestore(&bus->gpio_lock, flags);  in ssb_gpio_polarity()
140 static int gige_pci_init_callback(struct ssb_bus *bus, unsigned long data)  in gige_pci_init_callback()  argument
147 	for (i = 0; i < bus->nr_devices; i++) {  in gige_pci_init_callback()
148 		dev = &(bus->devices[i]);  in gige_pci_init_callback()
182 static int gige_map_irq_callback(struct ssb_bus *bus, unsigned long data)  in gige_map_irq_callback()  argument
189 	for (i = 0; i < bus->nr_devices; i++) {  in gige_map_irq_callback()
190 		dev = &(bus->devices[i]);  in gige_map_irq_callback()
210 	/* Check if this PCI device is a device on a SSB bus or device  in ssb_pcibios_map_irq()