Lines Matching +full:spi +full:- +full:tx +full:- +full:bus +full:- +full:width
2 * A driver for the ARM PL022 PrimeCell SSP/SPI bus master.
4 * Copyright (C) 2008-2009 ST-Ericsson AB
10 * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
31 #include <linux/spi/spi.h>
36 #include <linux/amba/bus.h>
41 #include <linux/dma-mapping.h>
99 * SSP Control Register 0 - SSP_CR0
117 * SSP Control Register 0 - SSP_CR1
137 * SSP Status Register - SSP_SR
146 * SSP Clock Prescale Register - SSP_CPSR
151 * SSP Interrupt Mask Set/Clear Register - SSP_IMSC
159 * SSP Raw Interrupt Status Register - SSP_RIS
171 * SSP Masked Interrupt Status Register - SSP_MIS
183 * SSP Interrupt Clear Register - SSP_ICR
191 * SSP DMA Control Register - SSP_DMACR
199 * SSP Integration Test control Register - SSP_ITCR
205 * SSP Integration Test Input Register - SSP_ITIP
215 * SSP Integration Test output Register - SSP_ITOP
233 * SSP Test Data Register - SSP_TDR
246 #define STATE_ERROR ((void *) -1)
249 * SSP State - Whether Enabled or Disabled
255 * SSP DMA State - Whether DMA Enabled or Disabled
306 * struct vendor_data - vendor-specific config parameters
325 * struct pl022 - This is the private SSP driver data structure
330 * @clk: outgoing clock "SPICLK" for the SPI bus
331 * @master: SPI framework hookup
332 * @master_info: controller-specific data from machine setup
347 * @tx: current position in TX buffer to be read
348 * @tx_end: end position in TX buffer to be read
355 * @dma_tx_channel: optional channel for TX DMA
357 * @sgt_tx: scattertable for the TX transfer
358 * @dummypage: a dummy page used for driving data on the bus with DMA
381 void *tx; member
401 * struct chip_data - To maintain runtime state of SSP for each client chip
402 * @cr0: Value of control register CR0 of SSP - on later ST variants this
407 * @n_bytes: how many bytes(power of 2) reqd for a given data width of client
431 * null_cs_control - Dummy chip select function
443 * giveback - current spi_message is over, schedule next message and call
445 * set message->status; dma and pio irqs are blocked
453 pl022->next_msg_cs_active = false; in giveback()
455 last_transfer = list_entry(pl022->cur_msg->transfers.prev, in giveback()
460 if (last_transfer->delay_usecs) in giveback()
465 udelay(last_transfer->delay_usecs); in giveback()
467 if (!last_transfer->cs_change) { in giveback()
473 * for the same spi device. in giveback()
476 * after calling msg->complete (below) the driver that in giveback()
482 spin_lock_irqsave(&pl022->queue_lock, flags); in giveback()
483 if (list_empty(&pl022->queue)) in giveback()
486 next_msg = list_entry(pl022->queue.next, in giveback()
488 spin_unlock_irqrestore(&pl022->queue_lock, flags); in giveback()
492 * to the same spi device. in giveback()
494 if (next_msg && next_msg->spi != pl022->cur_msg->spi) in giveback()
496 if (!next_msg || pl022->cur_msg->state == STATE_ERROR) in giveback()
497 pl022->cur_chip->cs_control(SSP_CHIP_DESELECT); in giveback()
499 pl022->next_msg_cs_active = true; in giveback()
502 spin_lock_irqsave(&pl022->queue_lock, flags); in giveback()
503 msg = pl022->cur_msg; in giveback()
504 pl022->cur_msg = NULL; in giveback()
505 pl022->cur_transfer = NULL; in giveback()
506 pl022->cur_chip = NULL; in giveback()
507 queue_work(pl022->workqueue, &pl022->pump_messages); in giveback()
508 spin_unlock_irqrestore(&pl022->queue_lock, flags); in giveback()
510 msg->state = NULL; in giveback()
511 if (msg->complete) in giveback()
512 msg->complete(msg->context); in giveback()
516 * flush - flush the FIFO to reach a clean state
523 dev_dbg(&pl022->adev->dev, "flush\n"); in flush()
525 while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) in flush()
526 readw(SSP_DR(pl022->virtbase)); in flush()
527 } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--); in flush()
529 pl022->exp_fifo_level = 0; in flush()
535 * restore_state - Load configuration of current chip
540 struct chip_data *chip = pl022->cur_chip; in restore_state()
542 if (pl022->vendor->extended_cr) in restore_state()
543 writel(chip->cr0, SSP_CR0(pl022->virtbase)); in restore_state()
545 writew(chip->cr0, SSP_CR0(pl022->virtbase)); in restore_state()
546 writew(chip->cr1, SSP_CR1(pl022->virtbase)); in restore_state()
547 writew(chip->dmacr, SSP_DMACR(pl022->virtbase)); in restore_state()
548 writew(chip->cpsr, SSP_CPSR(pl022->virtbase)); in restore_state()
549 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); in restore_state()
550 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); in restore_state()
625 * load_ssp_default_config - Load default configuration for SSP
630 if (pl022->vendor->pl023) { in load_ssp_default_config()
631 writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase)); in load_ssp_default_config()
632 writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase)); in load_ssp_default_config()
633 } else if (pl022->vendor->extended_cr) { in load_ssp_default_config()
634 writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase)); in load_ssp_default_config()
635 writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase)); in load_ssp_default_config()
637 writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase)); in load_ssp_default_config()
638 writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase)); in load_ssp_default_config()
640 writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase)); in load_ssp_default_config()
641 writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase)); in load_ssp_default_config()
642 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); in load_ssp_default_config()
643 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); in load_ssp_default_config()
647 * This will write to TX and read from RX according to the parameters
659 * To prevent this issue, the TX FIFO is only filled to the in readwriter()
660 * unused RX FIFO fill length, regardless of what the TX in readwriter()
663 dev_dbg(&pl022->adev->dev, in readwriter()
664 "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n", in readwriter()
665 __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end); in readwriter()
668 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) in readwriter()
669 && (pl022->rx < pl022->rx_end)) { in readwriter()
670 switch (pl022->read) { in readwriter()
672 readw(SSP_DR(pl022->virtbase)); in readwriter()
675 *(u8 *) (pl022->rx) = in readwriter()
676 readw(SSP_DR(pl022->virtbase)) & 0xFFU; in readwriter()
679 *(u16 *) (pl022->rx) = in readwriter()
680 (u16) readw(SSP_DR(pl022->virtbase)); in readwriter()
683 *(u32 *) (pl022->rx) = in readwriter()
684 readl(SSP_DR(pl022->virtbase)); in readwriter()
687 pl022->rx += (pl022->cur_chip->n_bytes); in readwriter()
688 pl022->exp_fifo_level--; in readwriter()
693 while ((pl022->exp_fifo_level < pl022->vendor->fifodepth) in readwriter()
694 && (pl022->tx < pl022->tx_end)) { in readwriter()
695 switch (pl022->write) { in readwriter()
697 writew(0x0, SSP_DR(pl022->virtbase)); in readwriter()
700 writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase)); in readwriter()
703 writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase)); in readwriter()
706 writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase)); in readwriter()
709 pl022->tx += (pl022->cur_chip->n_bytes); in readwriter()
710 pl022->exp_fifo_level++; in readwriter()
714 * clock starts running when you put things into the TX FIFO, in readwriter()
717 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) in readwriter()
718 && (pl022->rx < pl022->rx_end)) { in readwriter()
719 switch (pl022->read) { in readwriter()
721 readw(SSP_DR(pl022->virtbase)); in readwriter()
724 *(u8 *) (pl022->rx) = in readwriter()
725 readw(SSP_DR(pl022->virtbase)) & 0xFFU; in readwriter()
728 *(u16 *) (pl022->rx) = in readwriter()
729 (u16) readw(SSP_DR(pl022->virtbase)); in readwriter()
732 *(u32 *) (pl022->rx) = in readwriter()
733 readl(SSP_DR(pl022->virtbase)); in readwriter()
736 pl022->rx += (pl022->cur_chip->n_bytes); in readwriter()
737 pl022->exp_fifo_level--; in readwriter()
741 * When we exit here the TX FIFO should be full and the RX FIFO in readwriter()
747 * next_transfer - Move to the Next transfer in the current spi message
750 * This function moves though the linked list of spi transfers in the
751 * current spi message and returns with the state of current spi
757 struct spi_message *msg = pl022->cur_msg; in next_transfer()
758 struct spi_transfer *trans = pl022->cur_transfer; in next_transfer()
761 if (trans->transfer_list.next != &msg->transfers) { in next_transfer()
762 pl022->cur_transfer = in next_transfer()
763 list_entry(trans->transfer_list.next, in next_transfer()
778 dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl, in unmap_free_dma_scatter()
779 pl022->sgt_tx.nents, DMA_TO_DEVICE); in unmap_free_dma_scatter()
780 dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl, in unmap_free_dma_scatter()
781 pl022->sgt_rx.nents, DMA_FROM_DEVICE); in unmap_free_dma_scatter()
782 sg_free_table(&pl022->sgt_rx); in unmap_free_dma_scatter()
783 sg_free_table(&pl022->sgt_tx); in unmap_free_dma_scatter()
789 struct spi_message *msg = pl022->cur_msg; in dma_callback()
791 BUG_ON(!pl022->sgt_rx.sgl); in dma_callback()
804 dma_sync_sg_for_cpu(&pl022->adev->dev, in dma_callback()
805 pl022->sgt_rx.sgl, in dma_callback()
806 pl022->sgt_rx.nents, in dma_callback()
809 for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) { in dma_callback()
810 dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i); in dma_callback()
811 print_hex_dump(KERN_ERR, "SPI RX: ", in dma_callback()
819 for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) { in dma_callback()
820 dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i); in dma_callback()
821 print_hex_dump(KERN_ERR, "SPI TX: ", in dma_callback()
835 msg->actual_length += pl022->cur_transfer->len; in dma_callback()
836 if (pl022->cur_transfer->cs_change) in dma_callback()
837 pl022->cur_chip-> in dma_callback()
841 msg->state = next_transfer(pl022); in dma_callback()
842 tasklet_schedule(&pl022->pump_transfers); in dma_callback()
857 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { in setup_dma_scatter()
864 if (bytesleft < (PAGE_SIZE - offset_in_page(bufp))) in setup_dma_scatter()
867 mapbytes = PAGE_SIZE - offset_in_page(bufp); in setup_dma_scatter()
871 bytesleft -= mapbytes; in setup_dma_scatter()
872 dev_dbg(&pl022->adev->dev, in setup_dma_scatter()
873 "set RX/TX target page @ %p, %d bytes, %d left\n", in setup_dma_scatter()
878 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { in setup_dma_scatter()
883 sg_set_page(sg, virt_to_page(pl022->dummypage), in setup_dma_scatter()
885 bytesleft -= mapbytes; in setup_dma_scatter()
886 dev_dbg(&pl022->adev->dev, in setup_dma_scatter()
887 "set RX/TX to dummy page %d bytes, %d left\n", in setup_dma_scatter()
896 * configure_dma - configures the channels for the next transfer
902 .src_addr = SSP_DR(pl022->phybase), in configure_dma()
906 .dst_addr = SSP_DR(pl022->phybase), in configure_dma()
912 struct dma_chan *rxchan = pl022->dma_rx_channel; in configure_dma()
913 struct dma_chan *txchan = pl022->dma_tx_channel; in configure_dma()
919 return -ENODEV; in configure_dma()
923 * Notice that the DMA engine uses one-to-one mapping. Since we can in configure_dma()
927 switch (pl022->rx_lev_trig) { in configure_dma()
944 rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1; in configure_dma()
948 switch (pl022->tx_lev_trig) { in configure_dma()
965 tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1; in configure_dma()
969 switch (pl022->read) { in configure_dma()
985 switch (pl022->write) { in configure_dma()
1001 /* SPI pecularity: we need to read and write the same width */ in configure_dma()
1012 pages = DIV_ROUND_UP(pl022->cur_transfer->len, PAGE_SIZE); in configure_dma()
1013 dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages); in configure_dma()
1015 ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_ATOMIC); in configure_dma()
1019 ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_ATOMIC); in configure_dma()
1023 /* Fill in the scatterlists for the RX+TX buffers */ in configure_dma()
1024 setup_dma_scatter(pl022, pl022->rx, in configure_dma()
1025 pl022->cur_transfer->len, &pl022->sgt_rx); in configure_dma()
1026 setup_dma_scatter(pl022, pl022->tx, in configure_dma()
1027 pl022->cur_transfer->len, &pl022->sgt_tx); in configure_dma()
1030 rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl, in configure_dma()
1031 pl022->sgt_rx.nents, DMA_FROM_DEVICE); in configure_dma()
1035 tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl, in configure_dma()
1036 pl022->sgt_tx.nents, DMA_TO_DEVICE); in configure_dma()
1041 rxdesc = rxchan->device->device_prep_slave_sg(rxchan, in configure_dma()
1042 pl022->sgt_rx.sgl, in configure_dma()
1049 txdesc = txchan->device->device_prep_slave_sg(txchan, in configure_dma()
1050 pl022->sgt_tx.sgl, in configure_dma()
1058 rxdesc->callback = dma_callback; in configure_dma()
1059 rxdesc->callback_param = pl022; in configure_dma()
1061 /* Submit and fire RX and TX with TX last so we're ready to read! */ in configure_dma()
1073 dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl, in configure_dma()
1074 pl022->sgt_tx.nents, DMA_TO_DEVICE); in configure_dma()
1076 dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl, in configure_dma()
1077 pl022->sgt_tx.nents, DMA_FROM_DEVICE); in configure_dma()
1079 sg_free_table(&pl022->sgt_tx); in configure_dma()
1081 sg_free_table(&pl022->sgt_rx); in configure_dma()
1083 return -ENOMEM; in configure_dma()
1094 * We need both RX and TX channels to do DMA, else do none in pl022_dma_probe()
1097 pl022->dma_rx_channel = dma_request_channel(mask, in pl022_dma_probe()
1098 pl022->master_info->dma_filter, in pl022_dma_probe()
1099 pl022->master_info->dma_rx_param); in pl022_dma_probe()
1100 if (!pl022->dma_rx_channel) { in pl022_dma_probe()
1101 dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n"); in pl022_dma_probe()
1105 pl022->dma_tx_channel = dma_request_channel(mask, in pl022_dma_probe()
1106 pl022->master_info->dma_filter, in pl022_dma_probe()
1107 pl022->master_info->dma_tx_param); in pl022_dma_probe()
1108 if (!pl022->dma_tx_channel) { in pl022_dma_probe()
1109 dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n"); in pl022_dma_probe()
1113 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL); in pl022_dma_probe()
1114 if (!pl022->dummypage) { in pl022_dma_probe()
1115 dev_dbg(&pl022->adev->dev, "no DMA dummypage!\n"); in pl022_dma_probe()
1119 dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n", in pl022_dma_probe()
1120 dma_chan_name(pl022->dma_rx_channel), in pl022_dma_probe()
1121 dma_chan_name(pl022->dma_tx_channel)); in pl022_dma_probe()
1126 dma_release_channel(pl022->dma_tx_channel); in pl022_dma_probe()
1128 dma_release_channel(pl022->dma_rx_channel); in pl022_dma_probe()
1129 pl022->dma_rx_channel = NULL; in pl022_dma_probe()
1131 dev_err(&pl022->adev->dev, in pl022_dma_probe()
1133 return -ENODEV; in pl022_dma_probe()
1138 struct dma_chan *rxchan = pl022->dma_rx_channel; in terminate_dma()
1139 struct dma_chan *txchan = pl022->dma_tx_channel; in terminate_dma()
1148 if (pl022->busy) in pl022_dma_remove()
1150 if (pl022->dma_tx_channel) in pl022_dma_remove()
1151 dma_release_channel(pl022->dma_tx_channel); in pl022_dma_remove()
1152 if (pl022->dma_rx_channel) in pl022_dma_remove()
1153 dma_release_channel(pl022->dma_rx_channel); in pl022_dma_remove()
1154 kfree(pl022->dummypage); in pl022_dma_remove()
1160 return -ENODEV; in configure_dma()
1174 * pl022_interrupt_handler - Interrupt handler for SSP controller
1181 * more data, and writes data in TX FIFO till it is not full. If we complete
1187 struct spi_message *msg = pl022->cur_msg; in pl022_interrupt_handler()
1192 dev_err(&pl022->adev->dev, in pl022_interrupt_handler()
1199 irq_status = readw(SSP_MIS(pl022->virtbase)); in pl022_interrupt_handler()
1211 * Overrun interrupt - bail out since our Data has been in pl022_interrupt_handler()
1214 dev_err(&pl022->adev->dev, "FIFO overrun\n"); in pl022_interrupt_handler()
1215 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF) in pl022_interrupt_handler()
1216 dev_err(&pl022->adev->dev, in pl022_interrupt_handler()
1218 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_TNF) in pl022_interrupt_handler()
1219 dev_err(&pl022->adev->dev, in pl022_interrupt_handler()
1228 SSP_IMSC(pl022->virtbase)); in pl022_interrupt_handler()
1229 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); in pl022_interrupt_handler()
1230 writew((readw(SSP_CR1(pl022->virtbase)) & in pl022_interrupt_handler()
1231 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); in pl022_interrupt_handler()
1232 msg->state = STATE_ERROR; in pl022_interrupt_handler()
1235 tasklet_schedule(&pl022->pump_transfers); in pl022_interrupt_handler()
1241 if ((pl022->tx == pl022->tx_end) && (flag == 0)) { in pl022_interrupt_handler()
1244 writew((readw(SSP_IMSC(pl022->virtbase)) & in pl022_interrupt_handler()
1246 SSP_IMSC(pl022->virtbase)); in pl022_interrupt_handler()
1252 * At this point, all TX will always be finished. in pl022_interrupt_handler()
1254 if (pl022->rx >= pl022->rx_end) { in pl022_interrupt_handler()
1256 SSP_IMSC(pl022->virtbase)); in pl022_interrupt_handler()
1257 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); in pl022_interrupt_handler()
1258 if (unlikely(pl022->rx > pl022->rx_end)) { in pl022_interrupt_handler()
1259 dev_warn(&pl022->adev->dev, "read %u surplus " in pl022_interrupt_handler()
1261 "number of bytes on a 16bit bus?)\n", in pl022_interrupt_handler()
1262 (u32) (pl022->rx - pl022->rx_end)); in pl022_interrupt_handler()
1265 msg->actual_length += pl022->cur_transfer->len; in pl022_interrupt_handler()
1266 if (pl022->cur_transfer->cs_change) in pl022_interrupt_handler()
1267 pl022->cur_chip-> in pl022_interrupt_handler()
1270 msg->state = next_transfer(pl022); in pl022_interrupt_handler()
1271 tasklet_schedule(&pl022->pump_transfers); in pl022_interrupt_handler()
1280 * send out on the SPI bus.
1287 /* Sanity check the message for this bus width */ in set_up_next_transfer()
1288 residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes; in set_up_next_transfer()
1290 dev_err(&pl022->adev->dev, in set_up_next_transfer()
1292 "chip bus has a data width of %u bytes!\n", in set_up_next_transfer()
1293 pl022->cur_transfer->len, in set_up_next_transfer()
1294 pl022->cur_chip->n_bytes); in set_up_next_transfer()
1295 dev_err(&pl022->adev->dev, "skipping this message\n"); in set_up_next_transfer()
1296 return -EIO; in set_up_next_transfer()
1298 pl022->tx = (void *)transfer->tx_buf; in set_up_next_transfer()
1299 pl022->tx_end = pl022->tx + pl022->cur_transfer->len; in set_up_next_transfer()
1300 pl022->rx = (void *)transfer->rx_buf; in set_up_next_transfer()
1301 pl022->rx_end = pl022->rx + pl022->cur_transfer->len; in set_up_next_transfer()
1302 pl022->write = in set_up_next_transfer()
1303 pl022->tx ? pl022->cur_chip->write : WRITING_NULL; in set_up_next_transfer()
1304 pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL; in set_up_next_transfer()
1309 * pump_transfers - Tasklet function which schedules next transfer
1322 message = pl022->cur_msg; in pump_transfers()
1323 transfer = pl022->cur_transfer; in pump_transfers()
1326 if (message->state == STATE_ERROR) { in pump_transfers()
1327 message->status = -EIO; in pump_transfers()
1333 if (message->state == STATE_DONE) { in pump_transfers()
1334 message->status = 0; in pump_transfers()
1340 if (message->state == STATE_RUNNING) { in pump_transfers()
1341 previous = list_entry(transfer->transfer_list.prev, in pump_transfers()
1344 if (previous->delay_usecs) in pump_transfers()
1349 udelay(previous->delay_usecs); in pump_transfers()
1352 if (previous->cs_change) in pump_transfers()
1353 pl022->cur_chip->cs_control(SSP_CHIP_SELECT); in pump_transfers()
1356 message->state = STATE_RUNNING; in pump_transfers()
1360 message->state = STATE_ERROR; in pump_transfers()
1361 message->status = -EIO; in pump_transfers()
1368 if (pl022->cur_chip->enable_dma) { in pump_transfers()
1370 dev_dbg(&pl022->adev->dev, in pump_transfers()
1379 writew(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase)); in pump_transfers()
1385 * Default is to enable all interrupts except RX - in do_interrupt_dma_transfer()
1386 * this will be enabled once TX is complete in do_interrupt_dma_transfer()
1391 if (!pl022->next_msg_cs_active) in do_interrupt_dma_transfer()
1392 pl022->cur_chip->cs_control(SSP_CHIP_SELECT); in do_interrupt_dma_transfer()
1394 if (set_up_next_transfer(pl022, pl022->cur_transfer)) { in do_interrupt_dma_transfer()
1396 pl022->cur_msg->state = STATE_ERROR; in do_interrupt_dma_transfer()
1397 pl022->cur_msg->status = -EIO; in do_interrupt_dma_transfer()
1402 if (pl022->cur_chip->enable_dma) { in do_interrupt_dma_transfer()
1405 dev_dbg(&pl022->adev->dev, in do_interrupt_dma_transfer()
1414 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), in do_interrupt_dma_transfer()
1415 SSP_CR1(pl022->virtbase)); in do_interrupt_dma_transfer()
1416 writew(irqflags, SSP_IMSC(pl022->virtbase)); in do_interrupt_dma_transfer()
1427 chip = pl022->cur_chip; in do_polling_transfer()
1428 message = pl022->cur_msg; in do_polling_transfer()
1430 while (message->state != STATE_DONE) { in do_polling_transfer()
1432 if (message->state == STATE_ERROR) in do_polling_transfer()
1434 transfer = pl022->cur_transfer; in do_polling_transfer()
1437 if (message->state == STATE_RUNNING) { in do_polling_transfer()
1439 list_entry(transfer->transfer_list.prev, in do_polling_transfer()
1441 if (previous->delay_usecs) in do_polling_transfer()
1442 udelay(previous->delay_usecs); in do_polling_transfer()
1443 if (previous->cs_change) in do_polling_transfer()
1444 pl022->cur_chip->cs_control(SSP_CHIP_SELECT); in do_polling_transfer()
1447 message->state = STATE_RUNNING; in do_polling_transfer()
1448 if (!pl022->next_msg_cs_active) in do_polling_transfer()
1449 pl022->cur_chip->cs_control(SSP_CHIP_SELECT); in do_polling_transfer()
1455 message->state = STATE_ERROR; in do_polling_transfer()
1460 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), in do_polling_transfer()
1461 SSP_CR1(pl022->virtbase)); in do_polling_transfer()
1463 dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n"); in do_polling_transfer()
1466 while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) { in do_polling_transfer()
1470 dev_warn(&pl022->adev->dev, in do_polling_transfer()
1472 message->state = STATE_ERROR; in do_polling_transfer()
1479 message->actual_length += pl022->cur_transfer->len; in do_polling_transfer()
1480 if (pl022->cur_transfer->cs_change) in do_polling_transfer()
1481 pl022->cur_chip->cs_control(SSP_CHIP_DESELECT); in do_polling_transfer()
1483 message->state = next_transfer(pl022); in do_polling_transfer()
1487 if (message->state == STATE_DONE) in do_polling_transfer()
1488 message->status = 0; in do_polling_transfer()
1490 message->status = -EIO; in do_polling_transfer()
1497 * pump_messages - Workqueue function which processes spi message queue
1500 * This function checks if there is any spi message in the queue that
1514 spin_lock_irqsave(&pl022->queue_lock, flags); in pump_messages()
1515 if (list_empty(&pl022->queue) || !pl022->running) { in pump_messages()
1516 if (pl022->busy) { in pump_messages()
1517 /* nothing more to do - disable spi/ssp and power off */ in pump_messages()
1518 writew((readw(SSP_CR1(pl022->virtbase)) & in pump_messages()
1519 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); in pump_messages()
1521 if (pl022->master_info->autosuspend_delay > 0) { in pump_messages()
1522 pm_runtime_mark_last_busy(&pl022->adev->dev); in pump_messages()
1523 pm_runtime_put_autosuspend(&pl022->adev->dev); in pump_messages()
1525 pm_runtime_put(&pl022->adev->dev); in pump_messages()
1528 pl022->busy = false; in pump_messages()
1529 spin_unlock_irqrestore(&pl022->queue_lock, flags); in pump_messages()
1534 if (pl022->cur_msg) { in pump_messages()
1535 spin_unlock_irqrestore(&pl022->queue_lock, flags); in pump_messages()
1539 pl022->cur_msg = in pump_messages()
1540 list_entry(pl022->queue.next, struct spi_message, queue); in pump_messages()
1542 list_del_init(&pl022->cur_msg->queue); in pump_messages()
1543 if (pl022->busy) in pump_messages()
1546 pl022->busy = true; in pump_messages()
1547 spin_unlock_irqrestore(&pl022->queue_lock, flags); in pump_messages()
1550 pl022->cur_msg->state = STATE_START; in pump_messages()
1551 pl022->cur_transfer = list_entry(pl022->cur_msg->transfers.next, in pump_messages()
1554 /* Setup the SPI using the per chip configuration */ in pump_messages()
1555 pl022->cur_chip = spi_get_ctldata(pl022->cur_msg->spi); in pump_messages()
1562 pm_runtime_get_sync(&pl022->adev->dev); in pump_messages()
1567 if (pl022->cur_chip->xfer_type == POLLING_TRANSFER) in pump_messages()
1575 INIT_LIST_HEAD(&pl022->queue); in init_queue()
1576 spin_lock_init(&pl022->queue_lock); in init_queue()
1578 pl022->running = false; in init_queue()
1579 pl022->busy = false; in init_queue()
1581 tasklet_init(&pl022->pump_transfers, pump_transfers, in init_queue()
1584 INIT_WORK(&pl022->pump_messages, pump_messages); in init_queue()
1585 pl022->workqueue = create_singlethread_workqueue( in init_queue()
1586 dev_name(pl022->master->dev.parent)); in init_queue()
1587 if (pl022->workqueue == NULL) in init_queue()
1588 return -EBUSY; in init_queue()
1597 spin_lock_irqsave(&pl022->queue_lock, flags); in start_queue()
1599 if (pl022->running || pl022->busy) { in start_queue()
1600 spin_unlock_irqrestore(&pl022->queue_lock, flags); in start_queue()
1601 return -EBUSY; in start_queue()
1604 pl022->running = true; in start_queue()
1605 pl022->cur_msg = NULL; in start_queue()
1606 pl022->cur_transfer = NULL; in start_queue()
1607 pl022->cur_chip = NULL; in start_queue()
1608 pl022->next_msg_cs_active = false; in start_queue()
1609 spin_unlock_irqrestore(&pl022->queue_lock, flags); in start_queue()
1611 queue_work(pl022->workqueue, &pl022->pump_messages); in start_queue()
1622 spin_lock_irqsave(&pl022->queue_lock, flags); in stop_queue()
1625 * A wait_queue on the pl022->busy could be used, but then the common in stop_queue()
1627 * friends on every SPI message. Do this instead */ in stop_queue()
1628 while ((!list_empty(&pl022->queue) || pl022->busy) && limit--) { in stop_queue()
1629 spin_unlock_irqrestore(&pl022->queue_lock, flags); in stop_queue()
1631 spin_lock_irqsave(&pl022->queue_lock, flags); in stop_queue()
1634 if (!list_empty(&pl022->queue) || pl022->busy) in stop_queue()
1635 status = -EBUSY; in stop_queue()
1637 pl022->running = false; in stop_queue()
1639 spin_unlock_irqrestore(&pl022->queue_lock, flags); in stop_queue()
1658 destroy_workqueue(pl022->workqueue); in destroy_queue()
1666 if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI) in verify_controller_parameters()
1667 || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) { in verify_controller_parameters()
1668 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1670 return -EINVAL; in verify_controller_parameters()
1672 if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) && in verify_controller_parameters()
1673 (!pl022->vendor->unidir)) { in verify_controller_parameters()
1674 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1677 return -EINVAL; in verify_controller_parameters()
1679 if ((chip_info->hierarchy != SSP_MASTER) in verify_controller_parameters()
1680 && (chip_info->hierarchy != SSP_SLAVE)) { in verify_controller_parameters()
1681 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1683 return -EINVAL; in verify_controller_parameters()
1685 if ((chip_info->com_mode != INTERRUPT_TRANSFER) in verify_controller_parameters()
1686 && (chip_info->com_mode != DMA_TRANSFER) in verify_controller_parameters()
1687 && (chip_info->com_mode != POLLING_TRANSFER)) { in verify_controller_parameters()
1688 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1690 return -EINVAL; in verify_controller_parameters()
1692 switch (chip_info->rx_lev_trig) { in verify_controller_parameters()
1699 if (pl022->vendor->fifodepth < 16) { in verify_controller_parameters()
1700 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1702 return -EINVAL; in verify_controller_parameters()
1706 if (pl022->vendor->fifodepth < 32) { in verify_controller_parameters()
1707 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1709 return -EINVAL; in verify_controller_parameters()
1713 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1715 return -EINVAL; in verify_controller_parameters()
1718 switch (chip_info->tx_lev_trig) { in verify_controller_parameters()
1725 if (pl022->vendor->fifodepth < 16) { in verify_controller_parameters()
1726 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1727 "TX FIFO Trigger Level is configured incorrectly\n"); in verify_controller_parameters()
1728 return -EINVAL; in verify_controller_parameters()
1732 if (pl022->vendor->fifodepth < 32) { in verify_controller_parameters()
1733 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1734 "TX FIFO Trigger Level is configured incorrectly\n"); in verify_controller_parameters()
1735 return -EINVAL; in verify_controller_parameters()
1739 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1740 "TX FIFO Trigger Level is configured incorrectly\n"); in verify_controller_parameters()
1741 return -EINVAL; in verify_controller_parameters()
1744 if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) { in verify_controller_parameters()
1745 if ((chip_info->ctrl_len < SSP_BITS_4) in verify_controller_parameters()
1746 || (chip_info->ctrl_len > SSP_BITS_32)) { in verify_controller_parameters()
1747 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1749 return -EINVAL; in verify_controller_parameters()
1751 if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO) in verify_controller_parameters()
1752 && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) { in verify_controller_parameters()
1753 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1755 return -EINVAL; in verify_controller_parameters()
1758 if (pl022->vendor->extended_cr) { in verify_controller_parameters()
1759 if ((chip_info->duplex != in verify_controller_parameters()
1761 && (chip_info->duplex != in verify_controller_parameters()
1763 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1765 return -EINVAL; in verify_controller_parameters()
1768 if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) in verify_controller_parameters()
1769 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1773 return -EINVAL; in verify_controller_parameters()
1780 * pl022_transfer - transfer function registered to SPI master framework
1781 * @spi: spi device which is requesting transfer
1782 * @msg: spi message which is to handled is queued to driver queue
1784 * This function is registered to the SPI framework for this SPI master
1788 static int pl022_transfer(struct spi_device *spi, struct spi_message *msg) in pl022_transfer() argument
1790 struct pl022 *pl022 = spi_master_get_devdata(spi->master); in pl022_transfer()
1793 spin_lock_irqsave(&pl022->queue_lock, flags); in pl022_transfer()
1795 if (!pl022->running) { in pl022_transfer()
1796 spin_unlock_irqrestore(&pl022->queue_lock, flags); in pl022_transfer()
1797 return -ESHUTDOWN; in pl022_transfer()
1799 msg->actual_length = 0; in pl022_transfer()
1800 msg->status = -EINPROGRESS; in pl022_transfer()
1801 msg->state = STATE_START; in pl022_transfer()
1803 list_add_tail(&msg->queue, &pl022->queue); in pl022_transfer()
1804 if (pl022->running && !pl022->busy) in pl022_transfer()
1805 queue_work(pl022->workqueue, &pl022->pump_messages); in pl022_transfer()
1807 spin_unlock_irqrestore(&pl022->queue_lock, flags); in pl022_transfer()
1824 rate = clk_get_rate(pl022->clk); in calculate_effective_freq()
1831 dev_err(&pl022->adev->dev, in calculate_effective_freq()
1833 return -EINVAL; in calculate_effective_freq()
1864 clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF); in calculate_effective_freq()
1865 clk_freq->scr = (u8) (best_scr & 0xFF); in calculate_effective_freq()
1866 dev_dbg(&pl022->adev->dev, in calculate_effective_freq()
1869 dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n", in calculate_effective_freq()
1870 clk_freq->cpsdvsr, clk_freq->scr); in calculate_effective_freq()
1893 * pl022_setup - setup function registered to SPI master framework
1894 * @spi: spi device which is requesting setup
1896 * This function is registered to the SPI framework for this SPI master
1904 static int pl022_setup(struct spi_device *spi) in pl022_setup() argument
1910 struct pl022 *pl022 = spi_master_get_devdata(spi->master); in pl022_setup()
1911 unsigned int bits = spi->bits_per_word; in pl022_setup()
1914 if (!spi->max_speed_hz) in pl022_setup()
1915 return -EINVAL; in pl022_setup()
1918 chip = spi_get_ctldata(spi); in pl022_setup()
1923 dev_err(&spi->dev, in pl022_setup()
1925 return -ENOMEM; in pl022_setup()
1927 dev_dbg(&spi->dev, in pl022_setup()
1932 chip_info = spi->controller_data; in pl022_setup()
1937 dev_dbg(&spi->dev, in pl022_setup()
1940 dev_dbg(&spi->dev, in pl022_setup()
1947 if ((0 == chip_info->clk_freq.cpsdvsr) in pl022_setup()
1948 && (0 == chip_info->clk_freq.scr)) { in pl022_setup()
1950 spi->max_speed_hz, in pl022_setup()
1955 memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq)); in pl022_setup()
1958 clk_freq.cpsdvsr - 1; in pl022_setup()
1962 status = -EINVAL; in pl022_setup()
1963 dev_err(&spi->dev, in pl022_setup()
1970 dev_err(&spi->dev, "controller data is incorrect"); in pl022_setup()
1974 pl022->rx_lev_trig = chip_info->rx_lev_trig; in pl022_setup()
1975 pl022->tx_lev_trig = chip_info->tx_lev_trig; in pl022_setup()
1978 chip->xfer_type = chip_info->com_mode; in pl022_setup()
1979 if (!chip_info->cs_control) { in pl022_setup()
1980 chip->cs_control = null_cs_control; in pl022_setup()
1981 dev_warn(&spi->dev, in pl022_setup()
1984 chip->cs_control = chip_info->cs_control; in pl022_setup()
1987 /* PL022 doesn't support less than 4-bits */ in pl022_setup()
1988 status = -ENOTSUPP; in pl022_setup()
1991 dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n"); in pl022_setup()
1992 chip->n_bytes = 1; in pl022_setup()
1993 chip->read = READING_U8; in pl022_setup()
1994 chip->write = WRITING_U8; in pl022_setup()
1996 dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n"); in pl022_setup()
1997 chip->n_bytes = 2; in pl022_setup()
1998 chip->read = READING_U16; in pl022_setup()
1999 chip->write = WRITING_U16; in pl022_setup()
2001 if (pl022->vendor->max_bpw >= 32) { in pl022_setup()
2002 dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n"); in pl022_setup()
2003 chip->n_bytes = 4; in pl022_setup()
2004 chip->read = READING_U32; in pl022_setup()
2005 chip->write = WRITING_U32; in pl022_setup()
2007 dev_err(&spi->dev, in pl022_setup()
2009 dev_err(&spi->dev, in pl022_setup()
2012 status = -ENOTSUPP; in pl022_setup()
2018 chip->cr0 = 0; in pl022_setup()
2019 chip->cr1 = 0; in pl022_setup()
2020 chip->dmacr = 0; in pl022_setup()
2021 chip->cpsr = 0; in pl022_setup()
2022 if ((chip_info->com_mode == DMA_TRANSFER) in pl022_setup()
2023 && ((pl022->master_info)->enable_dma)) { in pl022_setup()
2024 chip->enable_dma = true; in pl022_setup()
2025 dev_dbg(&spi->dev, "DMA mode set in controller state\n"); in pl022_setup()
2026 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, in pl022_setup()
2028 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, in pl022_setup()
2031 chip->enable_dma = false; in pl022_setup()
2032 dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n"); in pl022_setup()
2033 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, in pl022_setup()
2035 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, in pl022_setup()
2039 chip->cpsr = clk_freq.cpsdvsr; in pl022_setup()
2042 if (pl022->vendor->extended_cr) { in pl022_setup()
2045 if (pl022->vendor->pl023) { in pl022_setup()
2047 SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay, in pl022_setup()
2051 SSP_WRITE_BITS(chip->cr0, chip_info->duplex, in pl022_setup()
2053 SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len, in pl022_setup()
2055 SSP_WRITE_BITS(chip->cr0, chip_info->iface, in pl022_setup()
2057 SSP_WRITE_BITS(chip->cr1, chip_info->wait_state, in pl022_setup()
2060 SSP_WRITE_BITS(chip->cr0, bits - 1, in pl022_setup()
2063 if (spi->mode & SPI_LSB_FIRST) { in pl022_setup()
2070 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4); in pl022_setup()
2071 SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5); in pl022_setup()
2072 SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig, in pl022_setup()
2074 SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig, in pl022_setup()
2077 SSP_WRITE_BITS(chip->cr0, bits - 1, in pl022_setup()
2079 SSP_WRITE_BITS(chip->cr0, chip_info->iface, in pl022_setup()
2084 if (spi->mode & SPI_CPOL) in pl022_setup()
2088 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6); in pl022_setup()
2090 if (spi->mode & SPI_CPHA) in pl022_setup()
2094 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7); in pl022_setup()
2096 SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8); in pl022_setup()
2098 if (pl022->vendor->loopback) { in pl022_setup()
2099 if (spi->mode & SPI_LOOP) in pl022_setup()
2103 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0); in pl022_setup()
2105 SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1); in pl022_setup()
2106 SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2); in pl022_setup()
2107 SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD, in pl022_setup()
2111 spi_set_ctldata(spi, chip); in pl022_setup()
2114 spi_set_ctldata(spi, NULL); in pl022_setup()
2120 * pl022_cleanup - cleanup function registered to SPI master framework
2121 * @spi: spi device which is requesting cleanup
2123 * This function is registered to the SPI framework for this SPI master
2126 static void pl022_cleanup(struct spi_device *spi) in pl022_cleanup() argument
2128 struct chip_data *chip = spi_get_ctldata(spi); in pl022_cleanup()
2130 spi_set_ctldata(spi, NULL); in pl022_cleanup()
2137 struct device *dev = &adev->dev; in pl022_probe()
2138 struct pl022_ssp_controller *platform_info = adev->dev.platform_data; in pl022_probe()
2143 dev_info(&adev->dev, in pl022_probe()
2144 "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid); in pl022_probe()
2146 dev_err(&adev->dev, "probe - no platform data supplied\n"); in pl022_probe()
2147 status = -ENODEV; in pl022_probe()
2154 dev_err(&adev->dev, "probe - cannot alloc SPI master\n"); in pl022_probe()
2155 status = -ENOMEM; in pl022_probe()
2160 pl022->master = master; in pl022_probe()
2161 pl022->master_info = platform_info; in pl022_probe()
2162 pl022->adev = adev; in pl022_probe()
2163 pl022->vendor = id->data; in pl022_probe()
2166 * Bus Number Which has been Assigned to this SSP controller in pl022_probe()
2169 master->bus_num = platform_info->bus_id; in pl022_probe()
2170 master->num_chipselect = platform_info->num_chipselect; in pl022_probe()
2171 master->cleanup = pl022_cleanup; in pl022_probe()
2172 master->setup = pl022_setup; in pl022_probe()
2173 master->transfer = pl022_transfer; in pl022_probe()
2176 * Supports mode 0-3, loopback, and active low CS. Transfers are in pl022_probe()
2179 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; in pl022_probe()
2180 if (pl022->vendor->extended_cr) in pl022_probe()
2181 master->mode_bits |= SPI_LSB_FIRST; in pl022_probe()
2183 dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num); in pl022_probe()
2189 pl022->phybase = adev->res.start; in pl022_probe()
2190 pl022->virtbase = ioremap(adev->res.start, resource_size(&adev->res)); in pl022_probe()
2191 if (pl022->virtbase == NULL) { in pl022_probe()
2192 status = -ENOMEM; in pl022_probe()
2196 adev->res.start, pl022->virtbase); in pl022_probe()
2198 pl022->clk = clk_get(&adev->dev, NULL); in pl022_probe()
2199 if (IS_ERR(pl022->clk)) { in pl022_probe()
2200 status = PTR_ERR(pl022->clk); in pl022_probe()
2201 dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n"); in pl022_probe()
2205 status = clk_prepare(pl022->clk); in pl022_probe()
2207 dev_err(&adev->dev, "could not prepare SSP/SPI bus clock\n"); in pl022_probe()
2211 status = clk_enable(pl022->clk); in pl022_probe()
2213 dev_err(&adev->dev, "could not enable SSP/SPI bus clock\n"); in pl022_probe()
2218 writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)), in pl022_probe()
2219 SSP_CR1(pl022->virtbase)); in pl022_probe()
2222 status = request_irq(adev->irq[0], pl022_interrupt_handler, 0, "pl022", in pl022_probe()
2225 dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status); in pl022_probe()
2230 if (platform_info->enable_dma) { in pl022_probe()
2233 platform_info->enable_dma = 0; in pl022_probe()
2239 dev_err(&adev->dev, "probe - problem initializing queue\n"); in pl022_probe()
2244 dev_err(&adev->dev, "probe - problem starting queue\n"); in pl022_probe()
2247 /* Register with the SPI framework */ in pl022_probe()
2251 dev_err(&adev->dev, in pl022_probe()
2252 "probe - problem registering spi master\n"); in pl022_probe()
2258 if (platform_info->autosuspend_delay > 0) { in pl022_probe()
2259 dev_info(&adev->dev, in pl022_probe()
2261 platform_info->autosuspend_delay); in pl022_probe()
2263 platform_info->autosuspend_delay); in pl022_probe()
2275 if (platform_info->enable_dma) in pl022_probe()
2278 free_irq(adev->irq[0], pl022); in pl022_probe()
2280 clk_disable(pl022->clk); in pl022_probe()
2282 clk_unprepare(pl022->clk); in pl022_probe()
2284 clk_put(pl022->clk); in pl022_probe()
2286 iounmap(pl022->virtbase); in pl022_probe()
2308 pm_runtime_get_noresume(&adev->dev); in pl022_remove()
2312 dev_err(&adev->dev, "queue remove failed\n"); in pl022_remove()
2314 if (pl022->master_info->enable_dma) in pl022_remove()
2317 free_irq(adev->irq[0], pl022); in pl022_remove()
2318 clk_disable(pl022->clk); in pl022_remove()
2319 clk_unprepare(pl022->clk); in pl022_remove()
2320 clk_put(pl022->clk); in pl022_remove()
2321 iounmap(pl022->virtbase); in pl022_remove()
2323 tasklet_disable(&pl022->pump_transfers); in pl022_remove()
2324 spi_unregister_master(pl022->master); in pl022_remove()
2325 spi_master_put(pl022->master); in pl022_remove()
2367 clk_disable(pl022->clk); in pl022_runtime_suspend()
2368 amba_vcore_disable(pl022->adev); in pl022_runtime_suspend()
2377 amba_vcore_enable(pl022->adev); in pl022_runtime_resume()
2378 clk_enable(pl022->clk); in pl022_runtime_resume()
2429 * and 8 locations deep TX/RX FIFO
2438 * and 32 locations deep TX/RX FIFO
2446 * ST-Ericsson derivative "PL023" (this is not
2448 * stripped to SPI mode only, it has 32bit wide
2449 * and 32 locations deep TX/RX FIFO but no extended
2468 .name = "ssp-pl022",