Lines Matching full:latency

37 	u32 l0s;			/* L0s latency (nsec) */
38 	u32 l1;				/* L1 latency (nsec) */
52 	u32 aspm_capable:3;		/* Capable ASPM state with latency */
62 	struct aspm_latency latency_up;	/* Upstream direction exit latency */
63 	struct aspm_latency latency_dw;	/* Downstream direction exit latency */
181  *   common clock. That will reduce the ASPM state exit latency.
258 /* Convert L0s latency encoding to ns */
266 /* Convert L0s acceptable latency encoding to ns */
274 /* Convert L1 latency encoding to ns */
282 /* Convert L1 acceptable latency encoding to ns */
315 	u32 latency, l1_switch_latency = 0;  in pcie_aspm_check_latency()  local
319 	/* Device not in D0 doesn't need latency check */  in pcie_aspm_check_latency()
328 		/* Check upstream direction L0s latency */  in pcie_aspm_check_latency()
333 		/* Check downstream direction L0s latency */  in pcie_aspm_check_latency()
338 		 * Check L1 latency.  in pcie_aspm_check_latency()
342 		latency = max_t(u32, link->latency_up.l1, link->latency_dw.l1);  in pcie_aspm_check_latency()
344 		    (latency + l1_switch_latency > acceptable->l1))  in pcie_aspm_check_latency()
426 		/* Calculate endpoint L0s acceptable latency */  in pcie_aspm_cap_init()
429 		/* Calculate endpoint L1 acceptable latency */  in pcie_aspm_cap_init()
696 	 * Devices changed PM state, we should recheck if latency  in pcie_aspm_pm_state_change()