41 struct pcie_link_state {  struct
43 	struct pcie_link_state *root;	/* pointer to the root port link */  argument
44 	struct pcie_link_state *parent;	/* pointer to the parent Link state */  argument
45 	struct list_head sibling;	/* node in link_list */
46 	struct list_head children;	/* list of child link states */
47 	struct list_head link;		/* node in parent's children list */
50 	u32 aspm_support:3;		/* Supported ASPM state */
51 	u32 aspm_enabled:3;		/* Enabled ASPM state */
52 	u32 aspm_capable:3;		/* Capable ASPM state with latency */
53 	u32 aspm_default:3;		/* Default ASPM state by BIOS */
54 	u32 aspm_disable:3;		/* Disabled ASPM state */
57 	u32 clkpm_capable:1;		/* Clock PM capable? */
58 	u32 clkpm_enabled:1;		/* Current Clock PM state */
59 	u32 clkpm_default:1;		/* Default Clock PM state by BIOS */
62 	struct aspm_latency latency_up;	/* Upstream direction exit latency */
63 	struct aspm_latency latency_dw;	/* Downstream direction exit latency */
88 static int policy_to_aspm_state(struct pcie_link_state *link)  in policy_to_aspm_state()  argument