brcm80211/brcmsmac/nicpci.c

174 struct sbpcieregs {  struct
175 	u32 control;		/* host mode only */
176 	u32 PAD[2];
177 	u32 biststatus;		/* bist Status: 0x00C */
178 	u32 gpiosel;		/* PCIE gpio sel: 0x010 */
179 	u32 gpioouten;		/* PCIE gpio outen: 0x14 */
180 	u32 PAD[2];
181 	u32 intstatus;		/* Interrupt status: 0x20 */
182 	u32 intmask;		/* Interrupt mask: 0x24 */
183 	u32 sbtopcimailbox;	/* sb to pcie mailbox: 0x028 */
184 	u32 PAD[53];
185 	u32 sbtopcie0;		/* sb to pcie translation 0: 0x100 */
186 	u32 sbtopcie1;		/* sb to pcie translation 1: 0x104 */
187 	u32 sbtopcie2;		/* sb to pcie translation 2: 0x108 */
188 	u32 PAD[5];
191 	u32 configaddr;	/* pcie config space access: Address field: 0x120 */
192 	u32 configdata;	/* pcie config space access: Data field: 0x124 */
195 	u32 mdiocontrol;	/* controls the mdio access: 0x128 */
196 	u32 mdiodata;		/* Data to the mdio access: 0x12c */
199 	u32 pcieindaddr;	/* indirect access to
202 	u32 pcieinddata;	/* Data to/from the internal regsiter: 0x134 */
204 	u32 clkreqenctrl;	/* >= rev 6, Clkreq rdma control : 0x138 */
205 	u32 PAD[177];
206 	u32 pciecfg[4][64];	/* 0x400 - 0x7FF, PCIE Cfg Space */
207 	u16 sprom[64];		/* SPROM shadow Area */