Lines Matching defs:modal_eep_4k_header
379 struct modal_eep_4k_header { struct
380 u32 antCtrlChain[AR5416_EEP4K_MAX_CHAINS];
381 u32 antCtrlCommon;
382 u8 antennaGainCh[AR5416_EEP4K_MAX_CHAINS];
383 u8 switchSettling;
384 u8 txRxAttenCh[AR5416_EEP4K_MAX_CHAINS];
385 u8 rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS];
386 u8 adcDesiredSize;
387 u8 pgaDesiredSize;
388 u8 xlnaGainCh[AR5416_EEP4K_MAX_CHAINS];
389 u8 txEndToXpaOff;
390 u8 txEndToRxOn;
391 u8 txFrameToXpaOn;
392 u8 thresh62;
393 u8 noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS];
394 u8 xpdGain;
395 u8 xpd;
396 u8 iqCalICh[AR5416_EEP4K_MAX_CHAINS];
397 u8 iqCalQCh[AR5416_EEP4K_MAX_CHAINS];
398 u8 pdGainOverlap;
400 u8 ob_1:4, ob_0:4;
401 u8 db1_1:4, db1_0:4;
403 u8 ob_0:4, ob_1:4;
404 u8 db1_0:4, db1_1:4;
406 u8 xpaBiasLvl;
407 u8 txFrameToDataStart;
408 u8 txFrameToPaOn;
409 u8 ht40PowerIncForPdadc;
410 u8 bswAtten[AR5416_EEP4K_MAX_CHAINS];
411 u8 bswMargin[AR5416_EEP4K_MAX_CHAINS];
412 u8 swSettleHt40;
413 u8 xatten2Db[AR5416_EEP4K_MAX_CHAINS];
414 u8 xatten2Margin[AR5416_EEP4K_MAX_CHAINS];
416 u8 db2_1:4, db2_0:4;
418 u8 db2_0:4, db2_1:4;
420 u8 version;
422 u8 ob_3:4, ob_2:4;
423 u8 antdiv_ctl1:4, ob_4:4;
424 u8 db1_3:4, db1_2:4;
425 u8 antdiv_ctl2:4, db1_4:4;
426 u8 db2_2:4, db2_3:4;
427 u8 reserved:4, db2_4:4;
429 u8 ob_2:4, ob_3:4;
430 u8 ob_4:4, antdiv_ctl1:4;
431 u8 db1_2:4, db1_3:4;
432 u8 db1_4:4, antdiv_ctl2:4;
433 u8 db2_2:4, db2_3:4;
434 u8 db2_4:4, reserved:4;
436 u8 tx_diversity;
437 u8 flc_pwr_thresh;
438 u8 bb_scale_smrt_antenna;
440 u8 futureModal[1];
441 struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS];