1252 struct ath5k_hw {  struct
1253 	struct ath_common       common;
1255 	struct pci_dev		*pdev;
1256 	struct device		*dev;		/* for dma mapping */
1257 	int irq;
1258 	u16 devid;
1259 	void __iomem		*iobase;	/* address of the device */
1260 	struct mutex		lock;		/* dev-level lock */
1261 	struct ieee80211_hw	*hw;		/* IEEE 802.11 common */
1262 	struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
1263 	struct ieee80211_channel channels[ATH_CHAN_MAX];
1264 	struct ieee80211_rate	rates[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
1265 	s8			rate_idx[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
1266 	enum nl80211_iftype	opmode;
1269 	struct ath5k_dbg_info	debug;		/* debug info */
1272 	struct ath5k_buf	*bufptr;	/* allocated buffer ptr */
1273 	struct ath5k_desc	*desc;		/* TX/RX descriptors */
1274 	dma_addr_t		desc_daddr;	/* DMA (physical) address */
1275 	size_t			desc_len;	/* size of TX/RX descriptors */
1283 	unsigned int		filter_flags;	/* HW flags, AR5K_RX_FILTER_* */
1284 	struct ieee80211_channel *curchan;	/* current h/w channel */
1286 	u16			nvifs;
1288 	enum ath5k_int		imask;		/* interrupt mask copy */
1290 	spinlock_t		irqlock;
1291 	bool			rx_pending;	/* rx tasklet pending */
1292 	bool			tx_pending;	/* tx tasklet pending */
1294 	u8			bssidmask[ETH_ALEN];
1296 	unsigned int		led_pin,	/* GPIO pin for driving LED */
1297 				led_on;		/* pin setting for LED on */
1299 	struct work_struct	reset_work;	/* deferred chip reset */
1300 	struct work_struct	calib_work;	/* deferred phy calibration */
1302 	struct list_head	rxbuf;		/* receive buffer */
1303 	spinlock_t		rxbuflock;
1304 	u32			*rxlink;	/* link ptr in last RX desc */
1305 	struct tasklet_struct	rxtq;		/* rx intr tasklet */
1306 	struct ath5k_led	rx_led;		/* rx led */
1308 	struct list_head	txbuf;		/* transmit buffer */
1309 	spinlock_t		txbuflock;
1310 	unsigned int		txbuf_len;	/* buf count in txbuf list */
1311 	struct ath5k_txq	txqs[AR5K_NUM_TX_QUEUES];	/* tx queues */
1312 	struct tasklet_struct	txtq;		/* tx intr tasklet */
1313 	struct ath5k_led	tx_led;		/* tx led */
1315 	struct ath5k_rfkill	rf_kill;
1317 	spinlock_t		block;		/* protects beacon */
1318 	struct tasklet_struct	beacontq;	/* beacon intr tasklet */
1319 	struct list_head	bcbuf;		/* beacon buffer */
1320 	struct ieee80211_vif	*bslot[ATH_BCBUF];
1321 	u16			num_ap_vifs;
1322 	u16			num_adhoc_vifs;
1323 	unsigned int		bhalq,		/* SW q for outgoing beacons */
1324 				bmisscount,	/* missed beacon transmits */
1325 				bintval,	/* beacon interval in TU */
1326 				bsent;
1327 	unsigned int		nexttbtt;	/* next beacon time in TU */
1328 	struct ath5k_txq	*cabq;		/* content after beacon */
1330 	int			power_level;	/* Requested tx power in dBm */
1331 	bool			assoc;		/* associate state */
1332 	bool			enable_beacon;	/* true if beacons are on */
1334 	struct ath5k_statistics	stats;
1336 	struct ath5k_ani_state	ani_state;
1337 	struct tasklet_struct	ani_tasklet;	/* ANI calibration */
1339 	struct delayed_work	tx_complete_work;
1341 	struct survey_info	survey;		/* collected survey info */
1343 	enum ath5k_int		ah_imr;
1345 	struct ieee80211_channel *ah_current_channel;
1346 	bool			ah_iq_cal_needed;
1347 	bool			ah_single_chip;
1349 	enum ath5k_version	ah_version;
1350 	enum ath5k_radio	ah_radio;
1351 	u32			ah_mac_srev;
1352 	u16			ah_mac_version;
1353 	u16			ah_phy_revision;
1354 	u16			ah_radio_5ghz_revision;
1355 	u16			ah_radio_2ghz_revision;
1360 	u8			ah_retry_long;
1361 	u8			ah_retry_short;
1363 	u32			ah_use_32khz_clock;
1365 	u8			ah_coverage_class;
1366 	bool			ah_ack_bitrate_high;
1367 	u8			ah_bwmode;
1368 	bool			ah_short_slot;
1371 	u32			ah_ant_ctl[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
1372 	u8			ah_ant_mode;
1373 	u8			ah_tx_ant;
1374 	u8			ah_def_ant;
1376 	struct ath5k_capabilities ah_capabilities;
1378 	struct ath5k_txq_info	ah_txq[AR5K_NUM_TX_QUEUES];
1379 	u32			ah_txq_status;
1380 	u32			ah_txq_imr_txok;
1381 	u32			ah_txq_imr_txerr;
1382 	u32			ah_txq_imr_txurn;
1383 	u32			ah_txq_imr_txdesc;
1384 	u32			ah_txq_imr_txeol;
1385 	u32			ah_txq_imr_cbrorn;
1386 	u32			ah_txq_imr_cbrurn;
1387 	u32			ah_txq_imr_qtrig;
1388 	u32			ah_txq_imr_nofrm;
1390 	u32			ah_txq_isr_txok_all;
1391 	u32			ah_txq_isr_txurn;
1392 	u32			ah_txq_isr_qcborn;
1393 	u32			ah_txq_isr_qcburn;
1394 	u32			ah_txq_isr_qtrig;
1396 	u32			*ah_rf_banks;
1397 	size_t			ah_rf_banks_size;
1398 	size_t			ah_rf_regs_count;
1399 	struct ath5k_gain	ah_gain;
1400 	u8			ah_offset[AR5K_MAX_RF_BANKS];
1403 	struct {
1445 	int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,  argument
1449 	int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,  argument
1451 	int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *,  argument