2753 struct cas {  struct
2774 	struct cas_init_block *init_block;  argument
2775 	struct cas_tx_desc *init_txds[MAX_TX_RINGS];  argument
2776 	struct cas_rx_desc *init_rxds[MAX_RX_DESC_RINGS];  argument
2777 	struct cas_rx_comp *init_rxcs[MAX_RX_COMP_RINGS];  argument
2783 	cas_page_t          *rx_pages[N_RX_DESC_RINGS][RX_DESC_RING_SIZE];  argument
2789 	struct cas_tiny_count tx_tiny_use[N_TX_RINGS][TX_DESC_RING_SIZE];  argument
2813 	u32                     cas_flags;  argument
2814 	int                     packet_min; /* minimum packet size */
2815 	int			tx_fifo_size;
2816 	int			rx_fifo_size;
2817 	int			rx_pause_off;
2818 	int			rx_pause_on;
2819 	int                     crc_size;      /* 4 if half-duplex */
2821 	int                     pci_irq_INTC;
2822 	int                     min_frame_size; /* for tx fifo workaround */
2825 	int                     page_size;
2826 	int                     page_order;
2827 	int                     mtu_stride;
2829 	u32			mac_rx_cfg;
2832 	int			link_cntl;
2833 	int			link_fcntl;
2834 	enum link_state		lstate;
2835 	struct timer_list	link_timer;
2836 	int			timer_ticks;
2837 	struct work_struct	reset_task;
2864 	int 			casreg_len; /* reg-space size for dumping */  argument
2865 	u64			pause_entered;
2866 	u16			pause_last_time_recvd;
2868 	dma_addr_t block_dvma, tx_tiny_dvma[N_TX_RINGS];
2869 	struct pci_dev *pdev;
2870 	struct net_device *dev;
2872 	struct device_node	*of_node;
2876 	u16			fw_load_addr;
2877 	u32			fw_size;
2878 	u8			*fw_data;