Lines Matching +full:0 +full:x3fffc000
56 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
58 #define assert(expr) do {} while (0)
59 #define dprintk(fmt, args...) do {} while (0)
74 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
75 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
88 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
89 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
90 #define RTL_EEPROM_SIG_ADDR 0x0000
101 RTL_GIGA_MAC_VER_01 = 0,
137 RTL_GIGA_MAC_NONE = 0xff,
141 RTL_TD_0 = 0,
253 RTL_CFG_0 = 0x00,
263 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
264 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
265 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
266 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
267 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
268 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
269 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
270 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
271 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
272 { PCI_VENDOR_ID_LINKSYS, 0x1032,
273 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
274 { 0x0001, 0x8168,
275 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
276 {0,},
288 MAC0 = 0, /* Ethernet hardware address. */
291 CounterAddrLow = 0x10,
292 CounterAddrHigh = 0x14,
293 TxDescStartAddrLow = 0x20,
294 TxDescStartAddrHigh = 0x24,
295 TxHDescStartAddrLow = 0x28,
296 TxHDescStartAddrHigh = 0x2c,
297 FLASH = 0x30,
298 ERSR = 0x36,
299 ChipCmd = 0x37,
300 TxPoll = 0x38,
301 IntrMask = 0x3c,
302 IntrStatus = 0x3e,
304 TxConfig = 0x40,
308 RxConfig = 0x44,
318 RxMissed = 0x4c,
319 Cfg9346 = 0x50,
320 Config0 = 0x51,
321 Config1 = 0x52,
322 Config2 = 0x53,
323 Config3 = 0x54,
324 Config4 = 0x55,
325 Config5 = 0x56,
326 MultiIntr = 0x5c,
327 PHYAR = 0x60,
328 PHYstatus = 0x6c,
329 RxMaxSize = 0xda,
330 CPlusCmd = 0xe0,
331 IntrMitigate = 0xe2,
332 RxDescAddrLow = 0xe4,
333 RxDescAddrHigh = 0xe8,
334 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
336 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
338 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
341 #define EarlySize 0x27
343 FuncEvent = 0xf0,
344 FuncEventMask = 0xf4,
345 FuncPresetState = 0xf8,
346 FuncForceEvent = 0xfc,
350 TBICSR = 0x64,
351 TBI_ANAR = 0x68,
352 TBI_LPAR = 0x6a,
356 CSIDR = 0x64,
357 CSIAR = 0x68,
358 #define CSIAR_FLAG 0x80000000
359 #define CSIAR_WRITE_CMD 0x80000000
360 #define CSIAR_BYTE_ENABLE 0x0f
362 #define CSIAR_ADDR_MASK 0x0fff
363 PMCH = 0x6f,
364 EPHYAR = 0x80,
365 #define EPHYAR_FLAG 0x80000000
366 #define EPHYAR_WRITE_CMD 0x80000000
367 #define EPHYAR_REG_MASK 0x1f
369 #define EPHYAR_DATA_MASK 0xffff
370 DLLPR = 0xd0,
372 DBG_REG = 0xd1,
375 TWSI = 0xd2,
376 MCU = 0xd3,
380 EFUSEAR = 0xdc,
381 #define EFUSEAR_FLAG 0x80000000
382 #define EFUSEAR_WRITE_CMD 0x80000000
383 #define EFUSEAR_READ_CMD 0x00000000
384 #define EFUSEAR_REG_MASK 0x03ff
386 #define EFUSEAR_DATA_MASK 0xff
390 LED_FREQ = 0x1a,
391 EEE_LED = 0x1b,
392 ERIDR = 0x70,
393 ERIAR = 0x74,
394 #define ERIAR_FLAG 0x80000000
395 #define ERIAR_WRITE_CMD 0x80000000
396 #define ERIAR_READ_CMD 0x00000000
399 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
400 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
401 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
403 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
404 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
405 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
406 EPHY_RXER_NUM = 0x7c,
407 OCPDR = 0xb0, /* OCP GPHY access */
408 #define OCPDR_WRITE_CMD 0x80000000
409 #define OCPDR_READ_CMD 0x00000000
410 #define OCPDR_REG_MASK 0x7f
412 #define OCPDR_DATA_MASK 0xffff
413 OCPAR = 0xb4,
414 #define OCPAR_FLAG 0x80000000
415 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
416 #define OCPAR_GPHY_READ_CMD 0x0000f060
417 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
418 MISC = 0xf0, /* 8168e only. */
425 SYSErr = 0x8000,
426 PCSTimeout = 0x4000,
427 SWInt = 0x0100,
428 TxDescUnavail = 0x0080,
429 RxFIFOOver = 0x0040,
430 LinkChg = 0x0020,
431 RxOverflow = 0x0010,
432 TxErr = 0x0008,
433 TxOK = 0x0004,
434 RxErr = 0x0002,
435 RxOK = 0x0001,
446 StopReq = 0x80,
447 CmdReset = 0x10,
448 CmdRxEnb = 0x08,
449 CmdTxEnb = 0x04,
450 RxBufEmpty = 0x01,
453 HPQ = 0x80, /* Poll cmd on the high prio queue */
454 NPQ = 0x40, /* Poll cmd on the low prio queue */
455 FSWInt = 0x01, /* Forced software interrupt */
458 Cfg9346_Lock = 0x00,
459 Cfg9346_Unlock = 0xc0,
462 AcceptErr = 0x20,
463 AcceptRunt = 0x10,
464 AcceptBroadcast = 0x08,
465 AcceptMulticast = 0x04,
466 AcceptMyPhys = 0x02,
467 AcceptAllPhys = 0x01,
468 #define RX_CONFIG_ACCEPT_MASK 0x3f
472 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
481 PMEnable = (1 << 0), /* Power Management Enable */
485 PCI_Clock_66MHz = 0x01,
486 PCI_Clock_33MHz = 0x00,
492 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
503 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
506 TBIReset = 0x80000000,
507 TBILoopback = 0x40000000,
508 TBINwEnable = 0x20000000,
509 TBINwRestart = 0x10000000,
510 TBILinkOk = 0x02000000,
511 TBINwComplete = 0x01000000,
523 Mac_dbgo_sel = 0x001c, // 8168
528 INTT_0 = 0x0000, // 8168
529 INTT_1 = 0x0001, // 8168
530 INTT_2 = 0x0002, // 8168
531 INTT_3 = 0x0003, // 8168
534 TBI_Enable = 0x80,
535 TxFlowCtrl = 0x40,
536 RxFlowCtrl = 0x20,
537 _1000bpsF = 0x10,
538 _100bps = 0x08,
539 _10bps = 0x04,
540 LinkStatus = 0x02,
541 FullDup = 0x01,
544 TBILinkOK = 0x02000000,
547 CounterDump = 0x8,
562 #define TD_MSS_MAX 0x07ffu /* MSS value */
600 .opts_offset = 0
628 #define RsvdMask 0x3fffc000
649 RTL_FEATURE_WOL = (1 << 0),
742 module_param(use_dac, int, 0);
744 module_param_named(debug, debug.msg_enable, int, 0);
745 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
792 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); in ocp_read()
793 for (i = 0; i < 20; i++) { in ocp_read()
807 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); in ocp_write()
808 for (i = 0; i < 20; i++) { in ocp_write()
810 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0) in ocp_write()
821 RTL_W32(ERIAR, 0x800010e8); in rtl8168_oob_notify()
823 for (i = 0; i < 5; i++) { in rtl8168_oob_notify()
829 ocp_write(tp, 0x1, 0x30, 0x00000001); in rtl8168_oob_notify()
832 #define OOB_CMD_RESET 0x00
833 #define OOB_CMD_DRIVER_START 0x05
834 #define OOB_CMD_DRIVER_STOP 0x06
838 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; in rtl8168_get_ocp_reg()
850 for (i = 0; i < 10; i++) { in rtl8168_driver_start()
852 if (ocp_read(tp, 0x0f, reg) & 0x00000800) in rtl8168_driver_start()
866 for (i = 0; i < 10; i++) { in rtl8168_driver_stop()
868 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0) in rtl8168_driver_stop()
877 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0; in r8168dp_check_dash()
884 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff)); in r8169_mdio_write()
886 for (i = 20; i > 0; i--) { in r8169_mdio_write()
891 if (!(RTL_R32(PHYAR) & 0x80000000)) in r8169_mdio_write()
906 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16); in r8169_mdio_read()
908 for (i = 20; i > 0; i--) { in r8169_mdio_read()
913 if (RTL_R32(PHYAR) & 0x80000000) { in r8169_mdio_read()
914 value = RTL_R32(PHYAR) & 0xffff; in r8169_mdio_read()
935 RTL_W32(EPHY_RXER_NUM, 0); in r8168dp_1_mdio_access()
937 for (i = 0; i < 100; i++) { in r8168dp_1_mdio_access()
958 RTL_W32(EPHY_RXER_NUM, 0); in r8168dp_1_mdio_read()
960 for (i = 0; i < 100; i++) { in r8168dp_1_mdio_read()
969 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
973 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); in r8168dp_2_mdio_start()
978 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT); in r8168dp_2_mdio_stop()
1048 for (i = 0; i < 100; i++) { in rtl_ephy_write()
1057 u16 value = 0xffff; in rtl_ephy_read()
1062 for (i = 0; i < 100; i++) { in rtl_ephy_read()
1081 for (i = 0; i < 100; i++) { in rtl_csi_write()
1090 u32 value = ~0x00; in rtl_csi_read()
1096 for (i = 0; i < 100; i++) { in rtl_csi_read()
1112 BUG_ON((addr & 3) || (mask == 0)); in rtl_eri_write()
1116 for (i = 0; i < 100; i++) { in rtl_eri_write()
1125 u32 value = ~0x00; in rtl_eri_read()
1130 for (i = 0; i < 100; i++) { in rtl_eri_read()
1159 while (len-- > 0) { in rtl_write_exgmac_batch()
1167 u8 value = 0xff; in rtl8168d_efuse_read()
1172 for (i = 0; i < 300; i++) { in rtl8168d_efuse_read()
1187 RTL_W16(IntrMask, 0x0000); in rtl8169_irq_mask_and_ack()
1226 rtl_writephy(tp, MII_BMCR, val & 0xffff); in rtl8169_xmii_reset_enable()
1239 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111, in rtl_link_chg_patch()
1240 0x00000011, ERIAR_EXGMAC); in rtl_link_chg_patch()
1241 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111, in rtl_link_chg_patch()
1242 0x00000005, ERIAR_EXGMAC); in rtl_link_chg_patch()
1244 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111, in rtl_link_chg_patch()
1245 0x0000001f, ERIAR_EXGMAC); in rtl_link_chg_patch()
1246 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111, in rtl_link_chg_patch()
1247 0x00000005, ERIAR_EXGMAC); in rtl_link_chg_patch()
1249 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111, in rtl_link_chg_patch()
1250 0x0000001f, ERIAR_EXGMAC); in rtl_link_chg_patch()
1251 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111, in rtl_link_chg_patch()
1252 0x0000003f, ERIAR_EXGMAC); in rtl_link_chg_patch()
1255 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, in rtl_link_chg_patch()
1257 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, in rtl_link_chg_patch()
1262 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111, in rtl_link_chg_patch()
1263 0x00000011, ERIAR_EXGMAC); in rtl_link_chg_patch()
1264 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111, in rtl_link_chg_patch()
1265 0x00000005, ERIAR_EXGMAC); in rtl_link_chg_patch()
1267 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111, in rtl_link_chg_patch()
1268 0x0000001f, ERIAR_EXGMAC); in rtl_link_chg_patch()
1269 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111, in rtl_link_chg_patch()
1270 0x0000003f, ERIAR_EXGMAC); in rtl_link_chg_patch()
1312 u32 wolopts = 0; in __rtl8169_get_wol()
1316 return 0; in __rtl8169_get_wol()
1367 for (i = 0; i < ARRAY_SIZE(cfg); i++) { in __rtl8169_set_wol()
1392 return 0; in rtl8169_set_wol()
1425 int ret = 0; in rtl8169_set_speed_tbi()
1450 rtl_writephy(tp, 0x1f, 0x0000); in rtl8169_set_speed_xmii()
1491 giga_ctrl = 0; in rtl8169_set_speed_xmii()
1494 bmcr = 0; in rtl8169_set_speed_xmii()
1509 rtl_writephy(tp, 0x17, 0x2138); in rtl8169_set_speed_xmii()
1510 rtl_writephy(tp, 0x0e, 0x0260); in rtl8169_set_speed_xmii()
1512 rtl_writephy(tp, 0x17, 0x2108); in rtl8169_set_speed_xmii()
1513 rtl_writephy(tp, 0x0e, 0x0000); in rtl8169_set_speed_xmii()
1517 rc = 0; in rtl8169_set_speed_xmii()
1529 if (ret < 0) in rtl8169_set_speed()
1595 return 0; in rtl8169_set_features()
1602 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00; in rtl8169_tx_vlan_tag()
1610 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff)); in rtl8169_rx_vlan_tag()
1612 desc->opts2 = 0; in rtl8169_rx_vlan_tag()
1627 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0; in rtl8169_gset_tbi()
1633 return 0; in rtl8169_gset_tbi()
1725 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0) in rtl8169_update_counters()
1738 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) { in rtl8169_update_counters()
1745 RTL_W32(CounterAddrLow, 0); in rtl8169_update_counters()
1746 RTL_W32(CounterAddrHigh, 0); in rtl8169_update_counters()
1760 data[0] = le64_to_cpu(tp->counters.tx_packets); in rtl8169_get_ethtool_stats()
1809 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be in rtl8169_get_mac_version()
1813 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec in rtl8169_get_mac_version()
1821 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 }, in rtl8169_get_mac_version()
1822 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 }, in rtl8169_get_mac_version()
1825 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 }, in rtl8169_get_mac_version()
1826 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 }, in rtl8169_get_mac_version()
1827 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 }, in rtl8169_get_mac_version()
1828 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 }, in rtl8169_get_mac_version()
1831 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 }, in rtl8169_get_mac_version()
1832 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 }, in rtl8169_get_mac_version()
1833 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 }, in rtl8169_get_mac_version()
1836 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 }, in rtl8169_get_mac_version()
1837 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 }, in rtl8169_get_mac_version()
1838 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 }, in rtl8169_get_mac_version()
1841 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 }, in rtl8169_get_mac_version()
1842 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 }, in rtl8169_get_mac_version()
1843 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 }, in rtl8169_get_mac_version()
1844 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 }, in rtl8169_get_mac_version()
1845 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 }, in rtl8169_get_mac_version()
1846 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 }, in rtl8169_get_mac_version()
1847 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 }, in rtl8169_get_mac_version()
1848 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 }, in rtl8169_get_mac_version()
1849 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 }, in rtl8169_get_mac_version()
1852 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 }, in rtl8169_get_mac_version()
1853 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 }, in rtl8169_get_mac_version()
1854 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 }, in rtl8169_get_mac_version()
1855 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 }, in rtl8169_get_mac_version()
1858 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 }, in rtl8169_get_mac_version()
1859 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 }, in rtl8169_get_mac_version()
1860 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 }, in rtl8169_get_mac_version()
1861 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 }, in rtl8169_get_mac_version()
1862 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 }, in rtl8169_get_mac_version()
1863 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 }, in rtl8169_get_mac_version()
1864 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 }, in rtl8169_get_mac_version()
1865 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 }, in rtl8169_get_mac_version()
1866 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 }, in rtl8169_get_mac_version()
1867 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 }, in rtl8169_get_mac_version()
1868 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 }, in rtl8169_get_mac_version()
1869 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 }, in rtl8169_get_mac_version()
1870 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 }, in rtl8169_get_mac_version()
1871 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 }, in rtl8169_get_mac_version()
1872 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 }, in rtl8169_get_mac_version()
1873 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 }, in rtl8169_get_mac_version()
1875 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 }, in rtl8169_get_mac_version()
1876 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 }, in rtl8169_get_mac_version()
1879 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 }, in rtl8169_get_mac_version()
1880 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 }, in rtl8169_get_mac_version()
1881 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 }, in rtl8169_get_mac_version()
1882 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 }, in rtl8169_get_mac_version()
1883 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 }, in rtl8169_get_mac_version()
1884 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 }, in rtl8169_get_mac_version()
1887 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE } in rtl8169_get_mac_version()
1906 dprintk("mac_version = 0x%02x\n", tp->mac_version); in rtl8169_print_mac_version()
1917 while (len-- > 0) { in rtl_writephy_batch()
1923 #define PHY_READ 0x00000000
1924 #define PHY_DATA_OR 0x10000000
1925 #define PHY_DATA_AND 0x20000000
1926 #define PHY_BJMPN 0x30000000
1927 #define PHY_READ_EFUSE 0x40000000
1928 #define PHY_READ_MAC_BYTE 0x50000000
1929 #define PHY_WRITE_MAC_BYTE 0x60000000
1930 #define PHY_CLEAR_READCOUNT 0x70000000
1931 #define PHY_WRITE 0x80000000
1932 #define PHY_READCOUNT_EQ_SKIP 0x90000000
1933 #define PHY_COMP_EQ_SKIPN 0xa0000000
1934 #define PHY_COMP_NEQ_SKIPN 0xb0000000
1935 #define PHY_WRITE_PREVIOUS 0xc0000000
1936 #define PHY_SKIPN 0xd0000000
1937 #define PHY_DELAY_MS 0xe0000000
1938 #define PHY_WRITE_ERI_WORD 0xf0000000
1948 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
1963 u8 checksum = 0; in rtl_fw_format_ok()
1968 for (i = 0; i < fw->size; i++) in rtl_fw_format_ok()
1970 if (checksum != 0) in rtl_fw_format_ok()
1994 version[RTL_VER_SIZE - 1] = 0; in rtl_fw_format_ok()
2007 for (index = 0; index < pa->size; index++) { in rtl_fw_data_ok()
2009 u32 regno = (action & 0x0fff0000) >> 16; in rtl_fw_data_ok()
2011 switch(action & 0xf0000000) { in rtl_fw_data_ok()
2051 "Invalid action 0x%08x\n", action); in rtl_fw_data_ok()
2071 rc = 0; in rtl_check_firmware()
2082 predata = count = 0; in rtl_phy_write_fw()
2084 for (index = 0; index < pa->size; ) { in rtl_phy_write_fw()
2086 u32 data = action & 0x0000ffff; in rtl_phy_write_fw()
2087 u32 regno = (action & 0x0fff0000) >> 16; in rtl_phy_write_fw()
2092 switch(action & 0xf0000000) { in rtl_phy_write_fw()
2114 count = 0; in rtl_phy_write_fw()
2184 { 0x1f, 0x0001 }, in rtl8169s_hw_phy_config()
2185 { 0x06, 0x006e }, in rtl8169s_hw_phy_config()
2186 { 0x08, 0x0708 }, in rtl8169s_hw_phy_config()
2187 { 0x15, 0x4000 }, in rtl8169s_hw_phy_config()
2188 { 0x18, 0x65c7 }, in rtl8169s_hw_phy_config()
2190 { 0x1f, 0x0001 }, in rtl8169s_hw_phy_config()
2191 { 0x03, 0x00a1 }, in rtl8169s_hw_phy_config()
2192 { 0x02, 0x0008 }, in rtl8169s_hw_phy_config()
2193 { 0x01, 0x0120 }, in rtl8169s_hw_phy_config()
2194 { 0x00, 0x1000 }, in rtl8169s_hw_phy_config()
2195 { 0x04, 0x0800 }, in rtl8169s_hw_phy_config()
2196 { 0x04, 0x0000 }, in rtl8169s_hw_phy_config()
2198 { 0x03, 0xff41 }, in rtl8169s_hw_phy_config()
2199 { 0x02, 0xdf60 }, in rtl8169s_hw_phy_config()
2200 { 0x01, 0x0140 }, in rtl8169s_hw_phy_config()
2201 { 0x00, 0x0077 }, in rtl8169s_hw_phy_config()
2202 { 0x04, 0x7800 }, in rtl8169s_hw_phy_config()
2203 { 0x04, 0x7000 }, in rtl8169s_hw_phy_config()
2205 { 0x03, 0x802f }, in rtl8169s_hw_phy_config()
2206 { 0x02, 0x4f02 }, in rtl8169s_hw_phy_config()
2207 { 0x01, 0x0409 }, in rtl8169s_hw_phy_config()
2208 { 0x00, 0xf0f9 }, in rtl8169s_hw_phy_config()
2209 { 0x04, 0x9800 }, in rtl8169s_hw_phy_config()
2210 { 0x04, 0x9000 }, in rtl8169s_hw_phy_config()
2212 { 0x03, 0xdf01 }, in rtl8169s_hw_phy_config()
2213 { 0x02, 0xdf20 }, in rtl8169s_hw_phy_config()
2214 { 0x01, 0xff95 }, in rtl8169s_hw_phy_config()
2215 { 0x00, 0xba00 }, in rtl8169s_hw_phy_config()
2216 { 0x04, 0xa800 }, in rtl8169s_hw_phy_config()
2217 { 0x04, 0xa000 }, in rtl8169s_hw_phy_config()
2219 { 0x03, 0xff41 }, in rtl8169s_hw_phy_config()
2220 { 0x02, 0xdf20 }, in rtl8169s_hw_phy_config()
2221 { 0x01, 0x0140 }, in rtl8169s_hw_phy_config()
2222 { 0x00, 0x00bb }, in rtl8169s_hw_phy_config()
2223 { 0x04, 0xb800 }, in rtl8169s_hw_phy_config()
2224 { 0x04, 0xb000 }, in rtl8169s_hw_phy_config()
2226 { 0x03, 0xdf41 }, in rtl8169s_hw_phy_config()
2227 { 0x02, 0xdc60 }, in rtl8169s_hw_phy_config()
2228 { 0x01, 0x6340 }, in rtl8169s_hw_phy_config()
2229 { 0x00, 0x007d }, in rtl8169s_hw_phy_config()
2230 { 0x04, 0xd800 }, in rtl8169s_hw_phy_config()
2231 { 0x04, 0xd000 }, in rtl8169s_hw_phy_config()
2233 { 0x03, 0xdf01 }, in rtl8169s_hw_phy_config()
2234 { 0x02, 0xdf20 }, in rtl8169s_hw_phy_config()
2235 { 0x01, 0x100a }, in rtl8169s_hw_phy_config()
2236 { 0x00, 0xa0ff }, in rtl8169s_hw_phy_config()
2237 { 0x04, 0xf800 }, in rtl8169s_hw_phy_config()
2238 { 0x04, 0xf000 }, in rtl8169s_hw_phy_config()
2240 { 0x1f, 0x0000 }, in rtl8169s_hw_phy_config()
2241 { 0x0b, 0x0000 }, in rtl8169s_hw_phy_config()
2242 { 0x00, 0x9200 } in rtl8169s_hw_phy_config()
2251 { 0x1f, 0x0002 }, in rtl8169sb_hw_phy_config()
2252 { 0x01, 0x90d0 }, in rtl8169sb_hw_phy_config()
2253 { 0x1f, 0x0000 } in rtl8169sb_hw_phy_config()
2264 (pdev->subsystem_device != 0xe000)) in rtl8169scd_hw_phy_config_quirk()
2267 rtl_writephy(tp, 0x1f, 0x0001); in rtl8169scd_hw_phy_config_quirk()
2268 rtl_writephy(tp, 0x10, 0xf01b); in rtl8169scd_hw_phy_config_quirk()
2269 rtl_writephy(tp, 0x1f, 0x0000); in rtl8169scd_hw_phy_config_quirk()
2275 { 0x1f, 0x0001 }, in rtl8169scd_hw_phy_config()
2276 { 0x04, 0x0000 }, in rtl8169scd_hw_phy_config()
2277 { 0x03, 0x00a1 }, in rtl8169scd_hw_phy_config()
2278 { 0x02, 0x0008 }, in rtl8169scd_hw_phy_config()
2279 { 0x01, 0x0120 }, in rtl8169scd_hw_phy_config()
2280 { 0x00, 0x1000 }, in rtl8169scd_hw_phy_config()
2281 { 0x04, 0x0800 }, in rtl8169scd_hw_phy_config()
2282 { 0x04, 0x9000 }, in rtl8169scd_hw_phy_config()
2283 { 0x03, 0x802f }, in rtl8169scd_hw_phy_config()
2284 { 0x02, 0x4f02 }, in rtl8169scd_hw_phy_config()
2285 { 0x01, 0x0409 }, in rtl8169scd_hw_phy_config()
2286 { 0x00, 0xf099 }, in rtl8169scd_hw_phy_config()
2287 { 0x04, 0x9800 }, in rtl8169scd_hw_phy_config()
2288 { 0x04, 0xa000 }, in rtl8169scd_hw_phy_config()
2289 { 0x03, 0xdf01 }, in rtl8169scd_hw_phy_config()
2290 { 0x02, 0xdf20 }, in rtl8169scd_hw_phy_config()
2291 { 0x01, 0xff95 }, in rtl8169scd_hw_phy_config()
2292 { 0x00, 0xba00 }, in rtl8169scd_hw_phy_config()
2293 { 0x04, 0xa800 }, in rtl8169scd_hw_phy_config()
2294 { 0x04, 0xf000 }, in rtl8169scd_hw_phy_config()
2295 { 0x03, 0xdf01 }, in rtl8169scd_hw_phy_config()
2296 { 0x02, 0xdf20 }, in rtl8169scd_hw_phy_config()
2297 { 0x01, 0x101a }, in rtl8169scd_hw_phy_config()
2298 { 0x00, 0xa0ff }, in rtl8169scd_hw_phy_config()
2299 { 0x04, 0xf800 }, in rtl8169scd_hw_phy_config()
2300 { 0x04, 0x0000 }, in rtl8169scd_hw_phy_config()
2301 { 0x1f, 0x0000 }, in rtl8169scd_hw_phy_config()
2303 { 0x1f, 0x0001 }, in rtl8169scd_hw_phy_config()
2304 { 0x10, 0xf41b }, in rtl8169scd_hw_phy_config()
2305 { 0x14, 0xfb54 }, in rtl8169scd_hw_phy_config()
2306 { 0x18, 0xf5c7 }, in rtl8169scd_hw_phy_config()
2307 { 0x1f, 0x0000 }, in rtl8169scd_hw_phy_config()
2309 { 0x1f, 0x0001 }, in rtl8169scd_hw_phy_config()
2310 { 0x17, 0x0cc0 }, in rtl8169scd_hw_phy_config()
2311 { 0x1f, 0x0000 } in rtl8169scd_hw_phy_config()
2322 { 0x1f, 0x0001 }, in rtl8169sce_hw_phy_config()
2323 { 0x04, 0x0000 }, in rtl8169sce_hw_phy_config()
2324 { 0x03, 0x00a1 }, in rtl8169sce_hw_phy_config()
2325 { 0x02, 0x0008 }, in rtl8169sce_hw_phy_config()
2326 { 0x01, 0x0120 }, in rtl8169sce_hw_phy_config()
2327 { 0x00, 0x1000 }, in rtl8169sce_hw_phy_config()
2328 { 0x04, 0x0800 }, in rtl8169sce_hw_phy_config()
2329 { 0x04, 0x9000 }, in rtl8169sce_hw_phy_config()
2330 { 0x03, 0x802f }, in rtl8169sce_hw_phy_config()
2331 { 0x02, 0x4f02 }, in rtl8169sce_hw_phy_config()
2332 { 0x01, 0x0409 }, in rtl8169sce_hw_phy_config()
2333 { 0x00, 0xf099 }, in rtl8169sce_hw_phy_config()
2334 { 0x04, 0x9800 }, in rtl8169sce_hw_phy_config()
2335 { 0x04, 0xa000 }, in rtl8169sce_hw_phy_config()
2336 { 0x03, 0xdf01 }, in rtl8169sce_hw_phy_config()
2337 { 0x02, 0xdf20 }, in rtl8169sce_hw_phy_config()
2338 { 0x01, 0xff95 }, in rtl8169sce_hw_phy_config()
2339 { 0x00, 0xba00 }, in rtl8169sce_hw_phy_config()
2340 { 0x04, 0xa800 }, in rtl8169sce_hw_phy_config()
2341 { 0x04, 0xf000 }, in rtl8169sce_hw_phy_config()
2342 { 0x03, 0xdf01 }, in rtl8169sce_hw_phy_config()
2343 { 0x02, 0xdf20 }, in rtl8169sce_hw_phy_config()
2344 { 0x01, 0x101a }, in rtl8169sce_hw_phy_config()
2345 { 0x00, 0xa0ff }, in rtl8169sce_hw_phy_config()
2346 { 0x04, 0xf800 }, in rtl8169sce_hw_phy_config()
2347 { 0x04, 0x0000 }, in rtl8169sce_hw_phy_config()
2348 { 0x1f, 0x0000 }, in rtl8169sce_hw_phy_config()
2350 { 0x1f, 0x0001 }, in rtl8169sce_hw_phy_config()
2351 { 0x0b, 0x8480 }, in rtl8169sce_hw_phy_config()
2352 { 0x1f, 0x0000 }, in rtl8169sce_hw_phy_config()
2354 { 0x1f, 0x0001 }, in rtl8169sce_hw_phy_config()
2355 { 0x18, 0x67c7 }, in rtl8169sce_hw_phy_config()
2356 { 0x04, 0x2000 }, in rtl8169sce_hw_phy_config()
2357 { 0x03, 0x002f }, in rtl8169sce_hw_phy_config()
2358 { 0x02, 0x4360 }, in rtl8169sce_hw_phy_config()
2359 { 0x01, 0x0109 }, in rtl8169sce_hw_phy_config()
2360 { 0x00, 0x3022 }, in rtl8169sce_hw_phy_config()
2361 { 0x04, 0x2800 }, in rtl8169sce_hw_phy_config()
2362 { 0x1f, 0x0000 }, in rtl8169sce_hw_phy_config()
2364 { 0x1f, 0x0001 }, in rtl8169sce_hw_phy_config()
2365 { 0x17, 0x0cc0 }, in rtl8169sce_hw_phy_config()
2366 { 0x1f, 0x0000 } in rtl8169sce_hw_phy_config()
2375 { 0x10, 0xf41b }, in rtl8168bb_hw_phy_config()
2376 { 0x1f, 0x0000 } in rtl8168bb_hw_phy_config()
2379 rtl_writephy(tp, 0x1f, 0x0001); in rtl8168bb_hw_phy_config()
2380 rtl_patchphy(tp, 0x16, 1 << 0); in rtl8168bb_hw_phy_config()
2388 { 0x1f, 0x0001 }, in rtl8168bef_hw_phy_config()
2389 { 0x10, 0xf41b }, in rtl8168bef_hw_phy_config()
2390 { 0x1f, 0x0000 } in rtl8168bef_hw_phy_config()
2399 { 0x1f, 0x0000 }, in rtl8168cp_1_hw_phy_config()
2400 { 0x1d, 0x0f00 }, in rtl8168cp_1_hw_phy_config()
2401 { 0x1f, 0x0002 }, in rtl8168cp_1_hw_phy_config()
2402 { 0x0c, 0x1ec8 }, in rtl8168cp_1_hw_phy_config()
2403 { 0x1f, 0x0000 } in rtl8168cp_1_hw_phy_config()
2412 { 0x1f, 0x0001 }, in rtl8168cp_2_hw_phy_config()
2413 { 0x1d, 0x3d98 }, in rtl8168cp_2_hw_phy_config()
2414 { 0x1f, 0x0000 } in rtl8168cp_2_hw_phy_config()
2417 rtl_writephy(tp, 0x1f, 0x0000); in rtl8168cp_2_hw_phy_config()
2418 rtl_patchphy(tp, 0x14, 1 << 5); in rtl8168cp_2_hw_phy_config()
2419 rtl_patchphy(tp, 0x0d, 1 << 5); in rtl8168cp_2_hw_phy_config()
2427 { 0x1f, 0x0001 }, in rtl8168c_1_hw_phy_config()
2428 { 0x12, 0x2300 }, in rtl8168c_1_hw_phy_config()
2429 { 0x1f, 0x0002 }, in rtl8168c_1_hw_phy_config()
2430 { 0x00, 0x88d4 }, in rtl8168c_1_hw_phy_config()
2431 { 0x01, 0x82b1 }, in rtl8168c_1_hw_phy_config()
2432 { 0x03, 0x7002 }, in rtl8168c_1_hw_phy_config()
2433 { 0x08, 0x9e30 }, in rtl8168c_1_hw_phy_config()
2434 { 0x09, 0x01f0 }, in rtl8168c_1_hw_phy_config()
2435 { 0x0a, 0x5500 }, in rtl8168c_1_hw_phy_config()
2436 { 0x0c, 0x00c8 }, in rtl8168c_1_hw_phy_config()
2437 { 0x1f, 0x0003 }, in rtl8168c_1_hw_phy_config()
2438 { 0x12, 0xc096 }, in rtl8168c_1_hw_phy_config()
2439 { 0x16, 0x000a }, in rtl8168c_1_hw_phy_config()
2440 { 0x1f, 0x0000 }, in rtl8168c_1_hw_phy_config()
2441 { 0x1f, 0x0000 }, in rtl8168c_1_hw_phy_config()
2442 { 0x09, 0x2000 }, in rtl8168c_1_hw_phy_config()
2443 { 0x09, 0x0000 } in rtl8168c_1_hw_phy_config()
2448 rtl_patchphy(tp, 0x14, 1 << 5); in rtl8168c_1_hw_phy_config()
2449 rtl_patchphy(tp, 0x0d, 1 << 5); in rtl8168c_1_hw_phy_config()
2450 rtl_writephy(tp, 0x1f, 0x0000); in rtl8168c_1_hw_phy_config()
2456 { 0x1f, 0x0001 }, in rtl8168c_2_hw_phy_config()
2457 { 0x12, 0x2300 }, in rtl8168c_2_hw_phy_config()
2458 { 0x03, 0x802f }, in rtl8168c_2_hw_phy_config()
2459 { 0x02, 0x4f02 }, in rtl8168c_2_hw_phy_config()
2460 { 0x01, 0x0409 }, in rtl8168c_2_hw_phy_config()
2461 { 0x00, 0xf099 }, in rtl8168c_2_hw_phy_config()
2462 { 0x04, 0x9800 }, in rtl8168c_2_hw_phy_config()
2463 { 0x04, 0x9000 }, in rtl8168c_2_hw_phy_config()
2464 { 0x1d, 0x3d98 }, in rtl8168c_2_hw_phy_config()
2465 { 0x1f, 0x0002 }, in rtl8168c_2_hw_phy_config()
2466 { 0x0c, 0x7eb8 }, in rtl8168c_2_hw_phy_config()
2467 { 0x06, 0x0761 }, in rtl8168c_2_hw_phy_config()
2468 { 0x1f, 0x0003 }, in rtl8168c_2_hw_phy_config()
2469 { 0x16, 0x0f0a }, in rtl8168c_2_hw_phy_config()
2470 { 0x1f, 0x0000 } in rtl8168c_2_hw_phy_config()
2475 rtl_patchphy(tp, 0x16, 1 << 0); in rtl8168c_2_hw_phy_config()
2476 rtl_patchphy(tp, 0x14, 1 << 5); in rtl8168c_2_hw_phy_config()
2477 rtl_patchphy(tp, 0x0d, 1 << 5); in rtl8168c_2_hw_phy_config()
2478 rtl_writephy(tp, 0x1f, 0x0000); in rtl8168c_2_hw_phy_config()
2484 { 0x1f, 0x0001 }, in rtl8168c_3_hw_phy_config()
2485 { 0x12, 0x2300 }, in rtl8168c_3_hw_phy_config()
2486 { 0x1d, 0x3d98 }, in rtl8168c_3_hw_phy_config()
2487 { 0x1f, 0x0002 }, in rtl8168c_3_hw_phy_config()
2488 { 0x0c, 0x7eb8 }, in rtl8168c_3_hw_phy_config()
2489 { 0x06, 0x5461 }, in rtl8168c_3_hw_phy_config()
2490 { 0x1f, 0x0003 }, in rtl8168c_3_hw_phy_config()
2491 { 0x16, 0x0f0a }, in rtl8168c_3_hw_phy_config()
2492 { 0x1f, 0x0000 } in rtl8168c_3_hw_phy_config()
2497 rtl_patchphy(tp, 0x16, 1 << 0); in rtl8168c_3_hw_phy_config()
2498 rtl_patchphy(tp, 0x14, 1 << 5); in rtl8168c_3_hw_phy_config()
2499 rtl_patchphy(tp, 0x0d, 1 << 5); in rtl8168c_3_hw_phy_config()
2500 rtl_writephy(tp, 0x1f, 0x0000); in rtl8168c_3_hw_phy_config()
2512 { 0x1f, 0x0001 }, in rtl8168d_1_hw_phy_config()
2513 { 0x06, 0x4064 }, in rtl8168d_1_hw_phy_config()
2514 { 0x07, 0x2863 }, in rtl8168d_1_hw_phy_config()
2515 { 0x08, 0x059c }, in rtl8168d_1_hw_phy_config()
2516 { 0x09, 0x26b4 }, in rtl8168d_1_hw_phy_config()
2517 { 0x0a, 0x6a19 }, in rtl8168d_1_hw_phy_config()
2518 { 0x0b, 0xdcc8 }, in rtl8168d_1_hw_phy_config()
2519 { 0x10, 0xf06d }, in rtl8168d_1_hw_phy_config()
2520 { 0x14, 0x7f68 }, in rtl8168d_1_hw_phy_config()
2521 { 0x18, 0x7fd9 }, in rtl8168d_1_hw_phy_config()
2522 { 0x1c, 0xf0ff }, in rtl8168d_1_hw_phy_config()
2523 { 0x1d, 0x3d9c }, in rtl8168d_1_hw_phy_config()
2524 { 0x1f, 0x0003 }, in rtl8168d_1_hw_phy_config()
2525 { 0x12, 0xf49f }, in rtl8168d_1_hw_phy_config()
2526 { 0x13, 0x070b }, in rtl8168d_1_hw_phy_config()
2527 { 0x1a, 0x05ad }, in rtl8168d_1_hw_phy_config()
2528 { 0x14, 0x94c0 }, in rtl8168d_1_hw_phy_config()
2534 { 0x1f, 0x0002 }, in rtl8168d_1_hw_phy_config()
2535 { 0x06, 0x5561 }, in rtl8168d_1_hw_phy_config()
2536 { 0x1f, 0x0005 }, in rtl8168d_1_hw_phy_config()
2537 { 0x05, 0x8332 }, in rtl8168d_1_hw_phy_config()
2538 { 0x06, 0x5561 }, in rtl8168d_1_hw_phy_config()
2544 { 0x1f, 0x0001 }, in rtl8168d_1_hw_phy_config()
2545 { 0x17, 0x0cc0 }, in rtl8168d_1_hw_phy_config()
2547 { 0x1f, 0x0000 }, in rtl8168d_1_hw_phy_config()
2548 { 0x0d, 0xf880 } in rtl8168d_1_hw_phy_config()
2558 rtl_writephy(tp, 0x1f, 0x0002); in rtl8168d_1_hw_phy_config()
2559 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef); in rtl8168d_1_hw_phy_config()
2560 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00); in rtl8168d_1_hw_phy_config()
2562 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) { in rtl8168d_1_hw_phy_config()
2564 { 0x1f, 0x0002 }, in rtl8168d_1_hw_phy_config()
2565 { 0x05, 0x669a }, in rtl8168d_1_hw_phy_config()
2566 { 0x1f, 0x0005 }, in rtl8168d_1_hw_phy_config()
2567 { 0x05, 0x8330 }, in rtl8168d_1_hw_phy_config()
2568 { 0x06, 0x669a }, in rtl8168d_1_hw_phy_config()
2569 { 0x1f, 0x0002 } in rtl8168d_1_hw_phy_config()
2575 val = rtl_readphy(tp, 0x0d); in rtl8168d_1_hw_phy_config()
2577 if ((val & 0x00ff) != 0x006c) { in rtl8168d_1_hw_phy_config()
2579 0x0065, 0x0066, 0x0067, 0x0068, in rtl8168d_1_hw_phy_config()
2580 0x0069, 0x006a, 0x006b, 0x006c in rtl8168d_1_hw_phy_config()
2584 rtl_writephy(tp, 0x1f, 0x0002); in rtl8168d_1_hw_phy_config()
2586 val &= 0xff00; in rtl8168d_1_hw_phy_config()
2587 for (i = 0; i < ARRAY_SIZE(set); i++) in rtl8168d_1_hw_phy_config()
2588 rtl_writephy(tp, 0x0d, val | set[i]); in rtl8168d_1_hw_phy_config()
2592 { 0x1f, 0x0002 }, in rtl8168d_1_hw_phy_config()
2593 { 0x05, 0x6662 }, in rtl8168d_1_hw_phy_config()
2594 { 0x1f, 0x0005 }, in rtl8168d_1_hw_phy_config()
2595 { 0x05, 0x8330 }, in rtl8168d_1_hw_phy_config()
2596 { 0x06, 0x6662 } in rtl8168d_1_hw_phy_config()
2603 rtl_writephy(tp, 0x1f, 0x0002); in rtl8168d_1_hw_phy_config()
2604 rtl_patchphy(tp, 0x0d, 0x0300); in rtl8168d_1_hw_phy_config()
2605 rtl_patchphy(tp, 0x0f, 0x0010); in rtl8168d_1_hw_phy_config()
2608 rtl_writephy(tp, 0x1f, 0x0002); in rtl8168d_1_hw_phy_config()
2609 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600); in rtl8168d_1_hw_phy_config()
2610 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000); in rtl8168d_1_hw_phy_config()
2612 rtl_writephy(tp, 0x1f, 0x0005); in rtl8168d_1_hw_phy_config()
2613 rtl_writephy(tp, 0x05, 0x001b); in rtl8168d_1_hw_phy_config()
2615 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00); in rtl8168d_1_hw_phy_config()
2617 rtl_writephy(tp, 0x1f, 0x0000); in rtl8168d_1_hw_phy_config()
2624 { 0x1f, 0x0001 }, in rtl8168d_2_hw_phy_config()
2625 { 0x06, 0x4064 }, in rtl8168d_2_hw_phy_config()
2626 { 0x07, 0x2863 }, in rtl8168d_2_hw_phy_config()
2627 { 0x08, 0x059c }, in rtl8168d_2_hw_phy_config()
2628 { 0x09, 0x26b4 }, in rtl8168d_2_hw_phy_config()
2629 { 0x0a, 0x6a19 }, in rtl8168d_2_hw_phy_config()
2630 { 0x0b, 0xdcc8 }, in rtl8168d_2_hw_phy_config()
2631 { 0x10, 0xf06d }, in rtl8168d_2_hw_phy_config()
2632 { 0x14, 0x7f68 }, in rtl8168d_2_hw_phy_config()
2633 { 0x18, 0x7fd9 }, in rtl8168d_2_hw_phy_config()
2634 { 0x1c, 0xf0ff }, in rtl8168d_2_hw_phy_config()
2635 { 0x1d, 0x3d9c }, in rtl8168d_2_hw_phy_config()
2636 { 0x1f, 0x0003 }, in rtl8168d_2_hw_phy_config()
2637 { 0x12, 0xf49f }, in rtl8168d_2_hw_phy_config()
2638 { 0x13, 0x070b }, in rtl8168d_2_hw_phy_config()
2639 { 0x1a, 0x05ad }, in rtl8168d_2_hw_phy_config()
2640 { 0x14, 0x94c0 }, in rtl8168d_2_hw_phy_config()
2646 { 0x1f, 0x0002 }, in rtl8168d_2_hw_phy_config()
2647 { 0x06, 0x5561 }, in rtl8168d_2_hw_phy_config()
2648 { 0x1f, 0x0005 }, in rtl8168d_2_hw_phy_config()
2649 { 0x05, 0x8332 }, in rtl8168d_2_hw_phy_config()
2650 { 0x06, 0x5561 }, in rtl8168d_2_hw_phy_config()
2656 { 0x1f, 0x0001 }, in rtl8168d_2_hw_phy_config()
2657 { 0x17, 0x0cc0 }, in rtl8168d_2_hw_phy_config()
2659 { 0x1f, 0x0000 }, in rtl8168d_2_hw_phy_config()
2660 { 0x0d, 0xf880 } in rtl8168d_2_hw_phy_config()
2666 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) { in rtl8168d_2_hw_phy_config()
2668 { 0x1f, 0x0002 }, in rtl8168d_2_hw_phy_config()
2669 { 0x05, 0x669a }, in rtl8168d_2_hw_phy_config()
2670 { 0x1f, 0x0005 }, in rtl8168d_2_hw_phy_config()
2671 { 0x05, 0x8330 }, in rtl8168d_2_hw_phy_config()
2672 { 0x06, 0x669a }, in rtl8168d_2_hw_phy_config()
2674 { 0x1f, 0x0002 } in rtl8168d_2_hw_phy_config()
2680 val = rtl_readphy(tp, 0x0d); in rtl8168d_2_hw_phy_config()
2681 if ((val & 0x00ff) != 0x006c) { in rtl8168d_2_hw_phy_config()
2683 0x0065, 0x0066, 0x0067, 0x0068, in rtl8168d_2_hw_phy_config()
2684 0x0069, 0x006a, 0x006b, 0x006c in rtl8168d_2_hw_phy_config()
2688 rtl_writephy(tp, 0x1f, 0x0002); in rtl8168d_2_hw_phy_config()
2690 val &= 0xff00; in rtl8168d_2_hw_phy_config()
2691 for (i = 0; i < ARRAY_SIZE(set); i++) in rtl8168d_2_hw_phy_config()
2692 rtl_writephy(tp, 0x0d, val | set[i]); in rtl8168d_2_hw_phy_config()
2696 { 0x1f, 0x0002 }, in rtl8168d_2_hw_phy_config()
2697 { 0x05, 0x2642 }, in rtl8168d_2_hw_phy_config()
2698 { 0x1f, 0x0005 }, in rtl8168d_2_hw_phy_config()
2699 { 0x05, 0x8330 }, in rtl8168d_2_hw_phy_config()
2700 { 0x06, 0x2642 } in rtl8168d_2_hw_phy_config()
2707 rtl_writephy(tp, 0x1f, 0x0002); in rtl8168d_2_hw_phy_config()
2708 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600); in rtl8168d_2_hw_phy_config()
2709 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000); in rtl8168d_2_hw_phy_config()
2712 rtl_writephy(tp, 0x1f, 0x0002); in rtl8168d_2_hw_phy_config()
2713 rtl_patchphy(tp, 0x0f, 0x0017); in rtl8168d_2_hw_phy_config()
2715 rtl_writephy(tp, 0x1f, 0x0005); in rtl8168d_2_hw_phy_config()
2716 rtl_writephy(tp, 0x05, 0x001b); in rtl8168d_2_hw_phy_config()
2718 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300); in rtl8168d_2_hw_phy_config()
2720 rtl_writephy(tp, 0x1f, 0x0000); in rtl8168d_2_hw_phy_config()
2726 { 0x1f, 0x0002 }, in rtl8168d_3_hw_phy_config()
2727 { 0x10, 0x0008 }, in rtl8168d_3_hw_phy_config()
2728 { 0x0d, 0x006c }, in rtl8168d_3_hw_phy_config()
2730 { 0x1f, 0x0000 }, in rtl8168d_3_hw_phy_config()
2731 { 0x0d, 0xf880 }, in rtl8168d_3_hw_phy_config()
2733 { 0x1f, 0x0001 }, in rtl8168d_3_hw_phy_config()
2734 { 0x17, 0x0cc0 }, in rtl8168d_3_hw_phy_config()
2736 { 0x1f, 0x0001 }, in rtl8168d_3_hw_phy_config()
2737 { 0x0b, 0xa4d8 }, in rtl8168d_3_hw_phy_config()
2738 { 0x09, 0x281c }, in rtl8168d_3_hw_phy_config()
2739 { 0x07, 0x2883 }, in rtl8168d_3_hw_phy_config()
2740 { 0x0a, 0x6b35 }, in rtl8168d_3_hw_phy_config()
2741 { 0x1d, 0x3da4 }, in rtl8168d_3_hw_phy_config()
2742 { 0x1c, 0xeffd }, in rtl8168d_3_hw_phy_config()
2743 { 0x14, 0x7f52 }, in rtl8168d_3_hw_phy_config()
2744 { 0x18, 0x7fc6 }, in rtl8168d_3_hw_phy_config()
2745 { 0x08, 0x0601 }, in rtl8168d_3_hw_phy_config()
2746 { 0x06, 0x4063 }, in rtl8168d_3_hw_phy_config()
2747 { 0x10, 0xf074 }, in rtl8168d_3_hw_phy_config()
2748 { 0x1f, 0x0003 }, in rtl8168d_3_hw_phy_config()
2749 { 0x13, 0x0789 }, in rtl8168d_3_hw_phy_config()
2750 { 0x12, 0xf4bd }, in rtl8168d_3_hw_phy_config()
2751 { 0x1a, 0x04fd }, in rtl8168d_3_hw_phy_config()
2752 { 0x14, 0x84b0 }, in rtl8168d_3_hw_phy_config()
2753 { 0x1f, 0x0000 }, in rtl8168d_3_hw_phy_config()
2754 { 0x00, 0x9200 }, in rtl8168d_3_hw_phy_config()
2756 { 0x1f, 0x0005 }, in rtl8168d_3_hw_phy_config()
2757 { 0x01, 0x0340 }, in rtl8168d_3_hw_phy_config()
2758 { 0x1f, 0x0001 }, in rtl8168d_3_hw_phy_config()
2759 { 0x04, 0x4000 }, in rtl8168d_3_hw_phy_config()
2760 { 0x03, 0x1d21 }, in rtl8168d_3_hw_phy_config()
2761 { 0x02, 0x0c32 }, in rtl8168d_3_hw_phy_config()
2762 { 0x01, 0x0200 }, in rtl8168d_3_hw_phy_config()
2763 { 0x00, 0x5554 }, in rtl8168d_3_hw_phy_config()
2764 { 0x04, 0x4800 }, in rtl8168d_3_hw_phy_config()
2765 { 0x04, 0x4000 }, in rtl8168d_3_hw_phy_config()
2766 { 0x04, 0xf000 }, in rtl8168d_3_hw_phy_config()
2767 { 0x03, 0xdf01 }, in rtl8168d_3_hw_phy_config()
2768 { 0x02, 0xdf20 }, in rtl8168d_3_hw_phy_config()
2769 { 0x01, 0x101a }, in rtl8168d_3_hw_phy_config()
2770 { 0x00, 0xa0ff }, in rtl8168d_3_hw_phy_config()
2771 { 0x04, 0xf800 }, in rtl8168d_3_hw_phy_config()
2772 { 0x04, 0xf000 }, in rtl8168d_3_hw_phy_config()
2773 { 0x1f, 0x0000 }, in rtl8168d_3_hw_phy_config()
2775 { 0x1f, 0x0007 }, in rtl8168d_3_hw_phy_config()
2776 { 0x1e, 0x0023 }, in rtl8168d_3_hw_phy_config()
2777 { 0x16, 0x0000 }, in rtl8168d_3_hw_phy_config()
2778 { 0x1f, 0x0000 } in rtl8168d_3_hw_phy_config()
2787 { 0x1f, 0x0001 }, in rtl8168d_4_hw_phy_config()
2788 { 0x17, 0x0cc0 }, in rtl8168d_4_hw_phy_config()
2790 { 0x1f, 0x0007 }, in rtl8168d_4_hw_phy_config()
2791 { 0x1e, 0x002d }, in rtl8168d_4_hw_phy_config()
2792 { 0x18, 0x0040 }, in rtl8168d_4_hw_phy_config()
2793 { 0x1f, 0x0000 } in rtl8168d_4_hw_phy_config()
2797 rtl_patchphy(tp, 0x0d, 1 << 5); in rtl8168d_4_hw_phy_config()
2804 { 0x1f, 0x0005 }, in rtl8168e_1_hw_phy_config()
2805 { 0x05, 0x8b80 }, in rtl8168e_1_hw_phy_config()
2806 { 0x06, 0xc896 }, in rtl8168e_1_hw_phy_config()
2807 { 0x1f, 0x0000 }, in rtl8168e_1_hw_phy_config()
2810 { 0x1f, 0x0001 }, in rtl8168e_1_hw_phy_config()
2811 { 0x0b, 0x6c20 }, in rtl8168e_1_hw_phy_config()
2812 { 0x07, 0x2872 }, in rtl8168e_1_hw_phy_config()
2813 { 0x1c, 0xefff }, in rtl8168e_1_hw_phy_config()
2814 { 0x1f, 0x0003 }, in rtl8168e_1_hw_phy_config()
2815 { 0x14, 0x6420 }, in rtl8168e_1_hw_phy_config()
2816 { 0x1f, 0x0000 }, in rtl8168e_1_hw_phy_config()
2819 { 0x1f, 0x0007 }, in rtl8168e_1_hw_phy_config()
2820 { 0x1e, 0x002f }, in rtl8168e_1_hw_phy_config()
2821 { 0x15, 0x1919 }, in rtl8168e_1_hw_phy_config()
2822 { 0x1f, 0x0000 }, in rtl8168e_1_hw_phy_config()
2824 { 0x1f, 0x0007 }, in rtl8168e_1_hw_phy_config()
2825 { 0x1e, 0x00ac }, in rtl8168e_1_hw_phy_config()
2826 { 0x18, 0x0006 }, in rtl8168e_1_hw_phy_config()
2827 { 0x1f, 0x0000 } in rtl8168e_1_hw_phy_config()
2835 rtl_writephy(tp, 0x1f, 0x0007); in rtl8168e_1_hw_phy_config()
2836 rtl_writephy(tp, 0x1e, 0x0023); in rtl8168e_1_hw_phy_config()
2837 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000); in rtl8168e_1_hw_phy_config()
2838 rtl_writephy(tp, 0x1f, 0x0000); in rtl8168e_1_hw_phy_config()
2841 rtl_writephy(tp, 0x1f, 0x0002); in rtl8168e_1_hw_phy_config()
2842 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00); in rtl8168e_1_hw_phy_config()
2843 rtl_writephy(tp, 0x1f, 0x0000); in rtl8168e_1_hw_phy_config()
2846 rtl_writephy(tp, 0x1f, 0x0007); in rtl8168e_1_hw_phy_config()
2847 rtl_writephy(tp, 0x1e, 0x002d); in rtl8168e_1_hw_phy_config()
2848 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000); in rtl8168e_1_hw_phy_config()
2849 rtl_writephy(tp, 0x1f, 0x0000); in rtl8168e_1_hw_phy_config()
2850 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000); in rtl8168e_1_hw_phy_config()
2852 rtl_writephy(tp, 0x1f, 0x0005); in rtl8168e_1_hw_phy_config()
2853 rtl_writephy(tp, 0x05, 0x8b86); in rtl8168e_1_hw_phy_config()
2854 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000); in rtl8168e_1_hw_phy_config()
2855 rtl_writephy(tp, 0x1f, 0x0000); in rtl8168e_1_hw_phy_config()
2857 rtl_writephy(tp, 0x1f, 0x0005); in rtl8168e_1_hw_phy_config()
2858 rtl_writephy(tp, 0x05, 0x8b85); in rtl8168e_1_hw_phy_config()
2859 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000); in rtl8168e_1_hw_phy_config()
2860 rtl_writephy(tp, 0x1f, 0x0007); in rtl8168e_1_hw_phy_config()
2861 rtl_writephy(tp, 0x1e, 0x0020); in rtl8168e_1_hw_phy_config()
2862 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100); in rtl8168e_1_hw_phy_config()
2863 rtl_writephy(tp, 0x1f, 0x0006); in rtl8168e_1_hw_phy_config()
2864 rtl_writephy(tp, 0x00, 0x5a00); in rtl8168e_1_hw_phy_config()
2865 rtl_writephy(tp, 0x1f, 0x0000); in rtl8168e_1_hw_phy_config()
2866 rtl_writephy(tp, 0x0d, 0x0007); in rtl8168e_1_hw_phy_config()
2867 rtl_writephy(tp, 0x0e, 0x003c); in rtl8168e_1_hw_phy_config()
2868 rtl_writephy(tp, 0x0d, 0x4007); in rtl8168e_1_hw_phy_config()
2869 rtl_writephy(tp, 0x0e, 0x0000); in rtl8168e_1_hw_phy_config()
2870 rtl_writephy(tp, 0x0d, 0x0000); in rtl8168e_1_hw_phy_config()
2877 { 0x1f, 0x0004 }, in rtl8168e_2_hw_phy_config()
2878 { 0x1f, 0x0007 }, in rtl8168e_2_hw_phy_config()
2879 { 0x1e, 0x00ac }, in rtl8168e_2_hw_phy_config()
2880 { 0x18, 0x0006 }, in rtl8168e_2_hw_phy_config()
2881 { 0x1f, 0x0002 }, in rtl8168e_2_hw_phy_config()
2882 { 0x1f, 0x0000 }, in rtl8168e_2_hw_phy_config()
2883 { 0x1f, 0x0000 }, in rtl8168e_2_hw_phy_config()
2886 { 0x1f, 0x0003 }, in rtl8168e_2_hw_phy_config()
2887 { 0x09, 0xa20f }, in rtl8168e_2_hw_phy_config()
2888 { 0x1f, 0x0000 }, in rtl8168e_2_hw_phy_config()
2889 { 0x1f, 0x0000 }, in rtl8168e_2_hw_phy_config()
2892 { 0x1f, 0x0005 }, in rtl8168e_2_hw_phy_config()
2893 { 0x05, 0x8b5b }, in rtl8168e_2_hw_phy_config()
2894 { 0x06, 0x9222 }, in rtl8168e_2_hw_phy_config()
2895 { 0x05, 0x8b6d }, in rtl8168e_2_hw_phy_config()
2896 { 0x06, 0x8000 }, in rtl8168e_2_hw_phy_config()
2897 { 0x05, 0x8b76 }, in rtl8168e_2_hw_phy_config()
2898 { 0x06, 0x8000 }, in rtl8168e_2_hw_phy_config()
2899 { 0x1f, 0x0000 } in rtl8168e_2_hw_phy_config()
2907 rtl_writephy(tp, 0x1f, 0x0005); in rtl8168e_2_hw_phy_config()
2908 rtl_writephy(tp, 0x05, 0x8b80); in rtl8168e_2_hw_phy_config()
2909 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000); in rtl8168e_2_hw_phy_config()
2910 rtl_writephy(tp, 0x1f, 0x0000); in rtl8168e_2_hw_phy_config()
2913 rtl_writephy(tp, 0x1f, 0x0004); in rtl8168e_2_hw_phy_config()
2914 rtl_writephy(tp, 0x1f, 0x0007); in rtl8168e_2_hw_phy_config()
2915 rtl_writephy(tp, 0x1e, 0x002d); in rtl8168e_2_hw_phy_config()
2916 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000); in rtl8168e_2_hw_phy_config()
2917 rtl_writephy(tp, 0x1f, 0x0002); in rtl8168e_2_hw_phy_config()
2918 rtl_writephy(tp, 0x1f, 0x0000); in rtl8168e_2_hw_phy_config()
2919 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000); in rtl8168e_2_hw_phy_config()
2922 rtl_writephy(tp, 0x1f, 0x0005); in rtl8168e_2_hw_phy_config()
2923 rtl_writephy(tp, 0x05, 0x8b86); in rtl8168e_2_hw_phy_config()
2924 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000); in rtl8168e_2_hw_phy_config()
2925 rtl_writephy(tp, 0x1f, 0x0000); in rtl8168e_2_hw_phy_config()
2928 rtl_writephy(tp, 0x1f, 0x0005); in rtl8168e_2_hw_phy_config()
2929 rtl_writephy(tp, 0x05, 0x8b85); in rtl8168e_2_hw_phy_config()
2930 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000); in rtl8168e_2_hw_phy_config()
2931 rtl_writephy(tp, 0x1f, 0x0000); in rtl8168e_2_hw_phy_config()
2934 rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, in rtl8168e_2_hw_phy_config()
2936 rtl_writephy(tp, 0x1f, 0x0005); in rtl8168e_2_hw_phy_config()
2937 rtl_writephy(tp, 0x05, 0x8b85); in rtl8168e_2_hw_phy_config()
2938 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000); in rtl8168e_2_hw_phy_config()
2939 rtl_writephy(tp, 0x1f, 0x0004); in rtl8168e_2_hw_phy_config()
2940 rtl_writephy(tp, 0x1f, 0x0007); in rtl8168e_2_hw_phy_config()
2941 rtl_writephy(tp, 0x1e, 0x0020); in rtl8168e_2_hw_phy_config()
2942 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100); in rtl8168e_2_hw_phy_config()
2943 rtl_writephy(tp, 0x1f, 0x0002); in rtl8168e_2_hw_phy_config()
2944 rtl_writephy(tp, 0x1f, 0x0000); in rtl8168e_2_hw_phy_config()
2945 rtl_writephy(tp, 0x0d, 0x0007); in rtl8168e_2_hw_phy_config()
2946 rtl_writephy(tp, 0x0e, 0x003c); in rtl8168e_2_hw_phy_config()
2947 rtl_writephy(tp, 0x0d, 0x4007); in rtl8168e_2_hw_phy_config()
2948 rtl_writephy(tp, 0x0e, 0x0000); in rtl8168e_2_hw_phy_config()
2949 rtl_writephy(tp, 0x0d, 0x0000); in rtl8168e_2_hw_phy_config()
2952 rtl_writephy(tp, 0x1f, 0x0003); in rtl8168e_2_hw_phy_config()
2953 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001); in rtl8168e_2_hw_phy_config()
2954 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400); in rtl8168e_2_hw_phy_config()
2955 rtl_writephy(tp, 0x1f, 0x0000); in rtl8168e_2_hw_phy_config()
2962 { 0x1f, 0x0003 }, in rtl8168f_1_hw_phy_config()
2963 { 0x09, 0xa20f }, in rtl8168f_1_hw_phy_config()
2964 { 0x1f, 0x0000 }, in rtl8168f_1_hw_phy_config()
2967 { 0x1f, 0x0005 }, in rtl8168f_1_hw_phy_config()
2968 { 0x05, 0x8b55 }, in rtl8168f_1_hw_phy_config()
2969 { 0x06, 0x0000 }, in rtl8168f_1_hw_phy_config()
2970 { 0x05, 0x8b5e }, in rtl8168f_1_hw_phy_config()
2971 { 0x06, 0x0000 }, in rtl8168f_1_hw_phy_config()
2972 { 0x05, 0x8b67 }, in rtl8168f_1_hw_phy_config()
2973 { 0x06, 0x0000 }, in rtl8168f_1_hw_phy_config()
2974 { 0x05, 0x8b70 }, in rtl8168f_1_hw_phy_config()
2975 { 0x06, 0x0000 }, in rtl8168f_1_hw_phy_config()
2976 { 0x1f, 0x0000 }, in rtl8168f_1_hw_phy_config()
2977 { 0x1f, 0x0007 }, in rtl8168f_1_hw_phy_config()
2978 { 0x1e, 0x0078 }, in rtl8168f_1_hw_phy_config()
2979 { 0x17, 0x0000 }, in rtl8168f_1_hw_phy_config()
2980 { 0x19, 0x00fb }, in rtl8168f_1_hw_phy_config()
2981 { 0x1f, 0x0000 }, in rtl8168f_1_hw_phy_config()
2984 { 0x1f, 0x0005 }, in rtl8168f_1_hw_phy_config()
2985 { 0x05, 0x8b79 }, in rtl8168f_1_hw_phy_config()
2986 { 0x06, 0xaa00 }, in rtl8168f_1_hw_phy_config()
2987 { 0x1f, 0x0000 }, in rtl8168f_1_hw_phy_config()
2990 { 0x1f, 0x0003 }, in rtl8168f_1_hw_phy_config()
2991 { 0x01, 0x328a }, in rtl8168f_1_hw_phy_config()
2992 { 0x1f, 0x0000 } in rtl8168f_1_hw_phy_config()
3000 rtl_writephy(tp, 0x1f, 0x0005); in rtl8168f_1_hw_phy_config()
3001 rtl_writephy(tp, 0x05, 0x8b80); in rtl8168f_1_hw_phy_config()
3002 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000); in rtl8168f_1_hw_phy_config()
3003 rtl_writephy(tp, 0x1f, 0x0000); in rtl8168f_1_hw_phy_config()
3006 rtl_writephy(tp, 0x1f, 0x0007); in rtl8168f_1_hw_phy_config()
3007 rtl_writephy(tp, 0x1e, 0x002d); in rtl8168f_1_hw_phy_config()
3008 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000); in rtl8168f_1_hw_phy_config()
3009 rtl_writephy(tp, 0x1f, 0x0000); in rtl8168f_1_hw_phy_config()
3010 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000); in rtl8168f_1_hw_phy_config()
3013 rtl_writephy(tp, 0x1f, 0x0005); in rtl8168f_1_hw_phy_config()
3014 rtl_writephy(tp, 0x05, 0x8b86); in rtl8168f_1_hw_phy_config()
3015 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000); in rtl8168f_1_hw_phy_config()
3016 rtl_writephy(tp, 0x1f, 0x0000); in rtl8168f_1_hw_phy_config()
3019 rtl_writephy(tp, 0x1f, 0x0005); in rtl8168f_1_hw_phy_config()
3020 rtl_writephy(tp, 0x05, 0x8b85); in rtl8168f_1_hw_phy_config()
3021 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000); in rtl8168f_1_hw_phy_config()
3022 rtl_writephy(tp, 0x1f, 0x0000); in rtl8168f_1_hw_phy_config()
3030 rtl_writephy(tp, 0x1f, 0x0005); in rtl8168f_2_hw_phy_config()
3031 rtl_writephy(tp, 0x05, 0x8b80); in rtl8168f_2_hw_phy_config()
3032 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000); in rtl8168f_2_hw_phy_config()
3033 rtl_writephy(tp, 0x1f, 0x0000); in rtl8168f_2_hw_phy_config()
3036 rtl_writephy(tp, 0x1f, 0x0007); in rtl8168f_2_hw_phy_config()
3037 rtl_writephy(tp, 0x1e, 0x002d); in rtl8168f_2_hw_phy_config()
3038 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000); in rtl8168f_2_hw_phy_config()
3039 rtl_writephy(tp, 0x1f, 0x0000); in rtl8168f_2_hw_phy_config()
3040 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000); in rtl8168f_2_hw_phy_config()
3043 rtl_writephy(tp, 0x1f, 0x0005); in rtl8168f_2_hw_phy_config()
3044 rtl_writephy(tp, 0x05, 0x8b86); in rtl8168f_2_hw_phy_config()
3045 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000); in rtl8168f_2_hw_phy_config()
3046 rtl_writephy(tp, 0x1f, 0x0000); in rtl8168f_2_hw_phy_config()
3052 { 0x1f, 0x0003 }, in rtl8102e_hw_phy_config()
3053 { 0x08, 0x441d }, in rtl8102e_hw_phy_config()
3054 { 0x01, 0x9100 }, in rtl8102e_hw_phy_config()
3055 { 0x1f, 0x0000 } in rtl8102e_hw_phy_config()
3058 rtl_writephy(tp, 0x1f, 0x0000); in rtl8102e_hw_phy_config()
3059 rtl_patchphy(tp, 0x11, 1 << 12); in rtl8102e_hw_phy_config()
3060 rtl_patchphy(tp, 0x19, 1 << 13); in rtl8102e_hw_phy_config()
3061 rtl_patchphy(tp, 0x10, 1 << 15); in rtl8102e_hw_phy_config()
3069 { 0x1f, 0x0005 }, in rtl8105e_hw_phy_config()
3070 { 0x1a, 0x0000 }, in rtl8105e_hw_phy_config()
3071 { 0x1f, 0x0000 }, in rtl8105e_hw_phy_config()
3073 { 0x1f, 0x0004 }, in rtl8105e_hw_phy_config()
3074 { 0x1c, 0x0000 }, in rtl8105e_hw_phy_config()
3075 { 0x1f, 0x0000 }, in rtl8105e_hw_phy_config()
3077 { 0x1f, 0x0001 }, in rtl8105e_hw_phy_config()
3078 { 0x15, 0x7701 }, in rtl8105e_hw_phy_config()
3079 { 0x1f, 0x0000 } in rtl8105e_hw_phy_config()
3083 rtl_writephy(tp, 0x1f, 0x0000); in rtl8105e_hw_phy_config()
3084 rtl_writephy(tp, 0x18, 0x0310); in rtl8105e_hw_phy_config()
3252 for (i = 0; i < 100; i++) { in rtl8169_phy_reset()
3275 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); in rtl8169_init_phy()
3276 RTL_W8(0x82, 0x01); in rtl8169_init_phy()
3279 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); in rtl8169_init_phy()
3282 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); in rtl8169_init_phy()
3285 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); in rtl8169_init_phy()
3286 RTL_W8(0x82, 0x01); in rtl8169_init_phy()
3287 dprintk("Set PHY Reg 0x0bh = 0x00h\n"); in rtl8169_init_phy()
3288 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0 in rtl8169_init_phy()
3298 ADVERTISED_1000baseT_Full : 0)); in rtl8169_init_phy()
3310 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24); in rtl_rar_set()
3325 { .addr = 0xe0, ERIAR_MASK_1111, .val = low }, in rtl_rar_set()
3326 { .addr = 0xe4, ERIAR_MASK_1111, .val = high }, in rtl_rar_set()
3327 { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 }, in rtl_rar_set()
3328 { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 | in rtl_rar_set()
3352 return 0; in rtl_set_mac_address()
3369 return 0; in rtl_xmii_ioctl()
3372 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f); in rtl_xmii_ioctl()
3373 return 0; in rtl_xmii_ioctl()
3376 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in); in rtl_xmii_ioctl()
3377 return 0; in rtl_xmii_ioctl()
3399 .align = 0,
3433 unsigned msi = 0; in rtl_try_msi()
3521 rtl_writephy(tp, 0x1f, 0x0000); in rtl_wol_pll_power_down()
3522 rtl_writephy(tp, MII_BMCR, 0x0000); in rtl_wol_pll_power_down()
3531 rtl_writephy(tp, 0x1f, 0x0000); in r810x_phy_power_down()
3537 rtl_writephy(tp, 0x1f, 0x0000); in r810x_phy_power_up()
3556 rtl_writephy(tp, 0x1f, 0x0000); in r8168_phy_power_up()
3573 rtl_writephy(tp, 0x0e, 0x0000); in r8168_phy_power_up()
3583 rtl_writephy(tp, 0x1f, 0x0000); in r8168_phy_power_down()
3605 rtl_writephy(tp, 0x0e, 0x0200); in r8168_phy_power_down()
3631 rtl_ephy_write(ioaddr, 0x19, 0xff64); in r8168_pll_power_down()
3646 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80); in r8168_pll_power_down()
3670 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80); in r8168_pll_power_up()
3779 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0; in rtl8169_init_ring_indexes()
3806 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT); in r8168c_hw_jumbo_enable()
3815 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT); in r8168c_hw_jumbo_disable()
3837 RTL_W8(MaxTxPacketSize, 0x3f); in r8168e_hw_jumbo_enable()
3839 RTL_W8(Config4, RTL_R8(Config4) | 0x01); in r8168e_hw_jumbo_enable()
3840 pci_write_config_byte(pdev, 0x79, 0x20); in r8168e_hw_jumbo_enable()
3848 RTL_W8(MaxTxPacketSize, 0x0c); in r8168e_hw_jumbo_disable()
3850 RTL_W8(Config4, RTL_R8(Config4) & ~0x01); in r8168e_hw_jumbo_disable()
3851 pci_write_config_byte(pdev, 0x79, 0x50); in r8168e_hw_jumbo_disable()
3857 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN); in r8168b_0_hw_jumbo_enable()
3863 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN); in r8168b_0_hw_jumbo_disable()
3872 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0)); in r8168b_1_hw_jumbo_enable()
3881 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0)); in r8168b_1_hw_jumbo_disable()
3943 for (i = 0; i < 100; i++) { in rtl_hw_reset()
3944 if ((RTL_R8(ChipCmd) & CmdReset) == 0) in rtl_hw_reset()
3986 mii->phy_id_mask = 0x1f; in rtl8169_init_one()
3987 mii->reg_num_mask = 0x1f; in rtl8169_init_one()
3997 if (rc < 0) { in rtl8169_init_one()
4002 if (pci_set_mwi(pdev) < 0) in rtl8169_init_one()
4023 if (rc < 0) { in rtl8169_init_one()
4036 if (rc < 0) { in rtl8169_init_one()
4059 RTL_W16(IntrMask, 0x0000); in rtl8169_init_one()
4063 RTL_W16(IntrStatus, 0xffff); in rtl8169_init_one()
4086 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0) in rtl8169_init_one()
4088 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0) in rtl8169_init_one()
4112 for (i = 0; i < ETH_ALEN; i++) in rtl8169_init_one()
4137 tp->intr_mask = 0xffff; in rtl8169_init_one()
4143 ~(RxBOVF | RxFOVF) : ~0; in rtl8169_init_one()
4152 if (rc < 0) in rtl8169_init_one()
4157 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n", in rtl8169_init_one()
4159 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq); in rtl8169_init_one()
4239 if (rc < 0) in rtl_request_uncached_firmware()
4243 if (rc < 0) in rtl_request_uncached_firmware()
4292 if (retval < 0) in rtl8169_open()
4302 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED, in rtl8169_open()
4304 if (retval < 0) in rtl8169_open()
4317 tp->saved_wolopts = 0; in rtl8169_open()
4429 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd in rtl8169_set_magic_reg()
4430 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff }, in rtl8169_set_magic_reg()
4431 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe in rtl8169_set_magic_reg()
4432 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff } in rtl8169_set_magic_reg()
4439 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) { in rtl8169_set_magic_reg()
4441 RTL_W32(0x7c, p->val); in rtl8169_set_magic_reg()
4455 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08); in rtl_hw_start_8169()
4481 dprintk("Set MAC Reg C+CR Offset 0xE0. " in rtl_hw_start_8169()
4494 RTL_W16(IntrMitigate, 0x0000); in rtl_hw_start_8169()
4511 RTL_W32(RxMissed, 0); in rtl_hw_start_8169()
4516 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); in rtl_hw_start_8169()
4526 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff; in rtl_csi_access_enable()
4527 rtl_csi_write(ioaddr, 0x070c, csi | bits); in rtl_csi_access_enable()
4532 rtl_csi_access_enable(ioaddr, 0x17000000); in rtl_csi_access_enable_1()
4537 rtl_csi_access_enable(ioaddr, 0x27000000); in rtl_csi_access_enable_2()
4550 while (len-- > 0) { in rtl_ephy_init()
4601 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN); in rtl_hw_start_8168bb()
4610 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0)); in rtl_hw_start_8168bef()
4619 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); in __rtl_hw_start_8168cp()
4629 { 0x01, 0, 0x0001 }, in rtl_hw_start_8168cp_1()
4630 { 0x02, 0x0800, 0x1000 }, in rtl_hw_start_8168cp_1()
4631 { 0x03, 0, 0x0042 }, in rtl_hw_start_8168cp_1()
4632 { 0x06, 0x0080, 0x0000 }, in rtl_hw_start_8168cp_1()
4633 { 0x07, 0, 0x2000 } in rtl_hw_start_8168cp_1()
4649 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); in rtl_hw_start_8168cp_2()
4661 RTL_W8(DBG_REG, 0x20); in rtl_hw_start_8168cp_3()
4665 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); in rtl_hw_start_8168cp_3()
4673 { 0x02, 0x0800, 0x1000 }, in rtl_hw_start_8168c_1()
4674 { 0x03, 0, 0x0002 }, in rtl_hw_start_8168c_1()
4675 { 0x06, 0x0080, 0x0000 } in rtl_hw_start_8168c_1()
4680 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); in rtl_hw_start_8168c_1()
4690 { 0x01, 0, 0x0001 }, in rtl_hw_start_8168c_2()
4691 { 0x03, 0x0400, 0x0220 } in rtl_hw_start_8168c_2()
4721 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); in rtl_hw_start_8168d()
4730 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); in rtl_hw_start_8168dp()
4740 { 0x0b, ~0, 0x48 }, in rtl_hw_start_8168d_4()
4741 { 0x19, 0x20, 0x50 }, in rtl_hw_start_8168d_4()
4742 { 0x0c, ~0, 0x20 } in rtl_hw_start_8168d_4()
4748 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); in rtl_hw_start_8168d_4()
4752 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) { in rtl_hw_start_8168d_4()
4757 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits); in rtl_hw_start_8168d_4()
4766 { 0x00, 0x0200, 0x0100 }, in rtl_hw_start_8168e_1()
4767 { 0x00, 0x0000, 0x0004 }, in rtl_hw_start_8168e_1()
4768 { 0x06, 0x0002, 0x0001 }, in rtl_hw_start_8168e_1()
4769 { 0x06, 0x0000, 0x0030 }, in rtl_hw_start_8168e_1()
4770 { 0x07, 0x0000, 0x2000 }, in rtl_hw_start_8168e_1()
4771 { 0x00, 0x0000, 0x0020 }, in rtl_hw_start_8168e_1()
4772 { 0x03, 0x5800, 0x2000 }, in rtl_hw_start_8168e_1()
4773 { 0x03, 0x0000, 0x0001 }, in rtl_hw_start_8168e_1()
4774 { 0x01, 0x0800, 0x1000 }, in rtl_hw_start_8168e_1()
4775 { 0x07, 0x0000, 0x4000 }, in rtl_hw_start_8168e_1()
4776 { 0x1e, 0x0000, 0x2000 }, in rtl_hw_start_8168e_1()
4777 { 0x19, 0xffff, 0xfe6c }, in rtl_hw_start_8168e_1()
4778 { 0x0a, 0x0000, 0x0040 } in rtl_hw_start_8168e_1()
4785 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); in rtl_hw_start_8168e_1()
4801 { 0x09, 0x0000, 0x0080 }, in rtl_hw_start_8168e_2()
4802 { 0x19, 0x0000, 0x0224 } in rtl_hw_start_8168e_2()
4809 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); in rtl_hw_start_8168e_2()
4811 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); in rtl_hw_start_8168e_2()
4812 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); in rtl_hw_start_8168e_2()
4813 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC); in rtl_hw_start_8168e_2()
4814 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC); in rtl_hw_start_8168e_2()
4815 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC); in rtl_hw_start_8168e_2()
4816 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC); in rtl_hw_start_8168e_2()
4817 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC); in rtl_hw_start_8168e_2()
4818 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, in rtl_hw_start_8168e_2()
4829 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07); in rtl_hw_start_8168e_2()
4839 { 0x06, 0x00c0, 0x0020 }, in rtl_hw_start_8168f_1()
4840 { 0x08, 0x0001, 0x0002 }, in rtl_hw_start_8168f_1()
4841 { 0x09, 0x0000, 0x0080 }, in rtl_hw_start_8168f_1()
4842 { 0x19, 0x0000, 0x0224 } in rtl_hw_start_8168f_1()
4849 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); in rtl_hw_start_8168f_1()
4851 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); in rtl_hw_start_8168f_1()
4852 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); in rtl_hw_start_8168f_1()
4853 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC); in rtl_hw_start_8168f_1()
4854 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC); in rtl_hw_start_8168f_1()
4855 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC); in rtl_hw_start_8168f_1()
4856 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC); in rtl_hw_start_8168f_1()
4857 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC); in rtl_hw_start_8168f_1()
4858 rtl_w1w0_eri(ioaddr, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC); in rtl_hw_start_8168f_1()
4859 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC); in rtl_hw_start_8168f_1()
4860 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC); in rtl_hw_start_8168f_1()
4861 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, in rtl_hw_start_8168f_1()
4872 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07); in rtl_hw_start_8168f_1()
4895 RTL_W16(IntrMitigate, 0x5151); in rtl_hw_start_8168()
4987 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); in rtl_hw_start_8168()
5006 { 0x01, 0, 0x6e65 }, in rtl_hw_start_8102e_1()
5007 { 0x02, 0, 0x091f }, in rtl_hw_start_8102e_1()
5008 { 0x03, 0, 0xc2f9 }, in rtl_hw_start_8102e_1()
5009 { 0x06, 0, 0xafb5 }, in rtl_hw_start_8102e_1()
5010 { 0x07, 0, 0x0e00 }, in rtl_hw_start_8102e_1()
5011 { 0x19, 0, 0xec80 }, in rtl_hw_start_8102e_1()
5012 { 0x01, 0, 0x2e65 }, in rtl_hw_start_8102e_1()
5013 { 0x01, 0, 0x6e65 } in rtl_hw_start_8102e_1()
5021 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); in rtl_hw_start_8102e_1()
5038 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); in rtl_hw_start_8102e_2()
5048 rtl_ephy_write(ioaddr, 0x03, 0xc2f9); in rtl_hw_start_8102e_3()
5054 { 0x07, 0, 0x4000 }, in rtl_hw_start_8105e_1()
5055 { 0x19, 0, 0x0200 }, in rtl_hw_start_8105e_1()
5056 { 0x19, 0, 0x0020 }, in rtl_hw_start_8105e_1()
5057 { 0x1e, 0, 0x2000 }, in rtl_hw_start_8105e_1()
5058 { 0x03, 0, 0x0001 }, in rtl_hw_start_8105e_1()
5059 { 0x19, 0, 0x0100 }, in rtl_hw_start_8105e_1()
5060 { 0x19, 0, 0x0004 }, in rtl_hw_start_8105e_1()
5061 { 0x0a, 0, 0x0020 } in rtl_hw_start_8105e_1()
5065 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800); in rtl_hw_start_8105e_1()
5068 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000); in rtl_hw_start_8105e_1()
5079 rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000); in rtl_hw_start_8105e_2()
5135 RTL_W16(IntrMitigate, 0x0000); in rtl_hw_start_8101()
5146 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000); in rtl_hw_start_8101()
5167 return 0; in rtl8169_change_mtu()
5172 desc->addr = cpu_to_le64(0x0badbadbadbadbadull); in rtl8169_make_unusable_by_asic()
5247 for (i = 0; i < NUM_RX_DESC; i++) { in rtl8169_rx_clear()
5264 for (i = 0; i < NUM_RX_DESC; i++) { in rtl8169_rx_fill()
5279 return 0; in rtl8169_rx_fill()
5292 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info)); in rtl8169_init_ring()
5293 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *)); in rtl8169_init_ring()
5305 desc->opts1 = 0x00; in rtl8169_unmap_tx_skb()
5306 desc->opts2 = 0x00; in rtl8169_unmap_tx_skb()
5307 desc->addr = 0x00; in rtl8169_unmap_tx_skb()
5308 tx_skb->len = 0; in rtl8169_unmap_tx_skb()
5316 for (i = 0; i < n; i++) { in rtl8169_tx_clear_range()
5338 tp->cur_tx = tp->dirty_tx = 0; in rtl8169_tx_clear()
5361 tp->intr_mask = 0xffff; in rtl8169_wait_for_quiescence()
5382 if (unlikely(ret < 0)) { in rtl8169_reinit_task()
5410 for (i = 0; i < NUM_RX_DESC; i++) in rtl8169_reset_task()
5438 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { in rtl8169_xmit_frags()
5458 status = opts[0] | len | in rtl8169_xmit_frags()
5488 opts[0] |= TD_LSO; in rtl8169_tso_csum()
5535 opts[0] = DescOwn; in rtl8169_start_xmit()
5540 if (frags < 0) in rtl8169_start_xmit()
5543 opts[0] |= FirstFrag; in rtl8169_start_xmit()
5545 opts[0] |= FirstFrag | LastFrag; in rtl8169_start_xmit()
5554 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); in rtl8169_start_xmit()
5594 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n", in rtl8169_pcierr_interrupt()
5642 while (tx_left > 0) { in rtl8169_tx_interrupt()
5729 for (; rx_left > 0; rx_left--, cur_rx++) { in rtl8169_rx_interrupt()
5755 int pkt_size = (status & 0x00003fff) - 4; in rtl8169_rx_interrupt()
5790 if ((desc->opts2 & cpu_to_le32(0xfffe000)) && in rtl8169_rx_interrupt()
5792 desc->opts2 = 0; in rtl8169_rx_interrupt()
5810 int handled = 0; in rtl8169_interrupt()
5817 while (status && status != 0xffff) { in rtl8169_interrupt()
5901 tp->intr_mask = 0xffff; in rtl8169_poll()
5916 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff); in rtl8169_rx_missed()
5917 RTL_W32(RxMissed, 0); in rtl8169_rx_missed()
5978 return 0; in rtl8169_close()
5988 u32 tmp = 0; in rtl_set_rx_mode()
5996 mc_filter[1] = mc_filter[0] = 0xffffffff; in rtl_set_rx_mode()
6001 mc_filter[1] = mc_filter[0] = 0xffffffff; in rtl_set_rx_mode()
6006 mc_filter[1] = mc_filter[0] = 0; in rtl_set_rx_mode()
6019 u32 data = mc_filter[0]; in rtl_set_rx_mode()
6021 mc_filter[0] = swab32(mc_filter[1]); in rtl_set_rx_mode()
6026 RTL_W32(MAR0 + 0, mc_filter[0]); in rtl_set_rx_mode()
6076 return 0; in rtl8169_suspend()
6101 return 0; in rtl8169_resume()
6111 return 0; in rtl8169_runtime_suspend()
6120 return 0; in rtl8169_runtime_suspend()
6130 return 0; in rtl8169_runtime_resume()
6134 tp->saved_wolopts = 0; in rtl8169_runtime_resume()
6141 return 0; in rtl8169_runtime_resume()
6150 return tp->TxDescArray ? -EBUSY : 0; in rtl8169_runtime_idle()