51  *	@adapter: the adapter performing the operation
62 static int t1_wait_op_done(adapter_t *adapter, int reg, u32 mask, int polarity,  in t1_wait_op_done()  argument
66 		u32 val = readl(adapter->regs + reg) & mask;  in t1_wait_op_done()
82 int __t1_tpi_write(adapter_t *adapter, u32 addr, u32 value)  in __t1_tpi_write()  argument
86 	writel(addr, adapter->regs + A_TPI_ADDR);  in __t1_tpi_write()
87 	writel(value, adapter->regs + A_TPI_WR_DATA);  in __t1_tpi_write()
88 	writel(F_TPIWR, adapter->regs + A_TPI_CSR);  in __t1_tpi_write()
90 	tpi_busy = t1_wait_op_done(adapter, A_TPI_CSR, F_TPIRDY, 1,  in __t1_tpi_write()
94 			 adapter->name, addr);  in __t1_tpi_write()
98 int t1_tpi_write(adapter_t *adapter, u32 addr, u32 value)  in t1_tpi_write()  argument
102 	spin_lock(&adapter->tpi_lock);  in t1_tpi_write()
103 	ret = __t1_tpi_write(adapter, addr, value);  in t1_tpi_write()
104 	spin_unlock(&adapter->tpi_lock);  in t1_tpi_write()
111 int __t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp)  in __t1_tpi_read()  argument
115 	writel(addr, adapter->regs + A_TPI_ADDR);  in __t1_tpi_read()
116 	writel(0, adapter->regs + A_TPI_CSR);  in __t1_tpi_read()
118 	tpi_busy = t1_wait_op_done(adapter, A_TPI_CSR, F_TPIRDY, 1,  in __t1_tpi_read()
122 			 adapter->name, addr);  in __t1_tpi_read()
124 		*valp = readl(adapter->regs + A_TPI_RD_DATA);  in __t1_tpi_read()
128 int t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp)  in t1_tpi_read()  argument
132 	spin_lock(&adapter->tpi_lock);  in t1_tpi_read()
133 	ret = __t1_tpi_read(adapter, addr, valp);  in t1_tpi_read()
134 	spin_unlock(&adapter->tpi_lock);  in t1_tpi_read()
141 static void t1_tpi_par(adapter_t *adapter, u32 value)  in t1_tpi_par()  argument
143 	writel(V_TPIPAR(value), adapter->regs + A_TPI_PAR);  in t1_tpi_par()
151 void t1_link_changed(adapter_t *adapter, int port_id)  in t1_link_changed()  argument
154 	struct cphy *phy = adapter->port[port_id].phy;  in t1_link_changed()
155 	struct link_config *lc = &adapter->port[port_id].link_config;  in t1_link_changed()
166 		struct cmac *mac = adapter->port[port_id].mac;  in t1_link_changed()
171 	t1_link_negotiated(adapter, port_id, link_ok, speed, duplex, fc);  in t1_link_changed()
174 static int t1_pci_intr_handler(adapter_t *adapter)  in t1_pci_intr_handler()  argument
178 	pci_read_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, &pcix_cause);  in t1_pci_intr_handler()
181 		pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE,  in t1_pci_intr_handler()
183 		t1_fatal_err(adapter);    /* PCI errors are fatal */  in t1_pci_intr_handler()
194 static int fpga_phy_intr_handler(adapter_t *adapter)  in fpga_phy_intr_handler()  argument
197 	u32 cause = readl(adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_CAUSE);  in fpga_phy_intr_handler()
199 	for_each_port(adapter, p)  in fpga_phy_intr_handler()
201 			struct cphy *phy = adapter->port[p].phy;  in fpga_phy_intr_handler()
205 				t1_link_changed(adapter, p);  in fpga_phy_intr_handler()
207 	writel(cause, adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_CAUSE);  in fpga_phy_intr_handler()
214 static int fpga_slow_intr(adapter_t *adapter)  in fpga_slow_intr()  argument
216 	u32 cause = readl(adapter->regs + A_PL_CAUSE);  in fpga_slow_intr()
220 		t1_sge_intr_error_handler(adapter->sge);  in fpga_slow_intr()
223 		fpga_phy_intr_handler(adapter);  in fpga_slow_intr()
230 		u32 tp_cause = readl(adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE);  in fpga_slow_intr()
233 		writel(tp_cause, adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE);  in fpga_slow_intr()
236 		t1_pci_intr_handler(adapter);  in fpga_slow_intr()
240 		writel(cause, adapter->regs + A_PL_CAUSE);  in fpga_slow_intr()
249 static int mi1_wait_until_ready(adapter_t *adapter, int mi1_reg)  in mi1_wait_until_ready()  argument
256 		__t1_tpi_read(adapter, mi1_reg, &val);  in mi1_wait_until_ready()
262 		pr_alert("%s: MDIO operation timed out\n", adapter->name);  in mi1_wait_until_ready()
269 static void mi1_mdio_init(adapter_t *adapter, const struct board_info *bi)  in mi1_mdio_init()  argument
277 	t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_CFG, val);  in mi1_mdio_init()
287 	struct adapter *adapter = dev->ml_priv;  in mi1_mdio_read()  local
291 	spin_lock(&adapter->tpi_lock);  in mi1_mdio_read()
292 	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);  in mi1_mdio_read()
293 	__t1_tpi_write(adapter,  in mi1_mdio_read()
295 	mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);  in mi1_mdio_read()
296 	__t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, &val);  in mi1_mdio_read()
297 	spin_unlock(&adapter->tpi_lock);  in mi1_mdio_read()
304 	struct adapter *adapter = dev->ml_priv;  in mi1_mdio_write()  local
307 	spin_lock(&adapter->tpi_lock);  in mi1_mdio_write()
308 	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);  in mi1_mdio_write()
309 	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, val);  in mi1_mdio_write()
310 	__t1_tpi_write(adapter,  in mi1_mdio_write()
312 	mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);  in mi1_mdio_write()
313 	spin_unlock(&adapter->tpi_lock);  in mi1_mdio_write()
329 	struct adapter *adapter = dev->ml_priv;  in mi1_mdio_ext_read()  local
333 	spin_lock(&adapter->tpi_lock);  in mi1_mdio_ext_read()
336 	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);  in mi1_mdio_ext_read()
337 	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, reg_addr);  in mi1_mdio_ext_read()
338 	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP,  in mi1_mdio_ext_read()
340 	mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);  in mi1_mdio_ext_read()
343 	__t1_tpi_write(adapter,  in mi1_mdio_ext_read()
345 	mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);  in mi1_mdio_ext_read()
348 	__t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, &val);  in mi1_mdio_ext_read()
349 	spin_unlock(&adapter->tpi_lock);  in mi1_mdio_ext_read()
356 	struct adapter *adapter = dev->ml_priv;  in mi1_mdio_ext_write()  local
359 	spin_lock(&adapter->tpi_lock);  in mi1_mdio_ext_write()
362 	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);  in mi1_mdio_ext_write()
363 	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, reg_addr);  in mi1_mdio_ext_write()
364 	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP,  in mi1_mdio_ext_write()
366 	mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);  in mi1_mdio_ext_write()
369 	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, val);  in mi1_mdio_ext_write()
370 	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP, MI1_OP_INDIRECT_WRITE);  in mi1_mdio_ext_write()
371 	mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);  in mi1_mdio_ext_write()
372 	spin_unlock(&adapter->tpi_lock);  in mi1_mdio_ext_write()
563 int t1_seeprom_read(adapter_t *adapter, u32 addr, __le32 *data)  in t1_seeprom_read()  argument
572 	pci_write_config_word(adapter->pdev, A_PCICFG_VPD_ADDR, (u16)addr);  in t1_seeprom_read()
575 		pci_read_config_word(adapter->pdev, A_PCICFG_VPD_ADDR, &val);  in t1_seeprom_read()
580 		       adapter->name, addr);  in t1_seeprom_read()
583 	pci_read_config_dword(adapter->pdev, A_PCICFG_VPD_DATA, &v);  in t1_seeprom_read()
588 static int t1_eeprom_vpd_get(adapter_t *adapter, struct chelsio_vpd_t *vpd)  in t1_eeprom_vpd_get()  argument
593 		ret = t1_seeprom_read(adapter, addr,  in t1_eeprom_vpd_get()
602 static int vpd_macaddress_get(adapter_t *adapter, int index, u8 mac_addr[])  in vpd_macaddress_get()  argument
606 	if (t1_eeprom_vpd_get(adapter, &vpd))  in vpd_macaddress_get()
632 				   (mac->adapter->params.nports < 2)))  in t1_link_start()
668 int t1_elmer0_ext_intr_handler(adapter_t *adapter)  in t1_elmer0_ext_intr_handler()  argument
674 	t1_tpi_read(adapter, A_ELMER0_INT_CAUSE, &cause);  in t1_elmer0_ext_intr_handler()
676 	switch (board_info(adapter)->board) {  in t1_elmer0_ext_intr_handler()
683 		for_each_port(adapter, i) {  in t1_elmer0_ext_intr_handler()
688 			phy = adapter->port[i].phy;  in t1_elmer0_ext_intr_handler()
691 				t1_link_changed(adapter, i);  in t1_elmer0_ext_intr_handler()
697 			phy = adapter->port[0].phy;  in t1_elmer0_ext_intr_handler()
700 				t1_link_changed(adapter, 0);  in t1_elmer0_ext_intr_handler()
711 		for_each_port(adapter, p) {  in t1_elmer0_ext_intr_handler()
712 			phy = adapter->port[p].phy;  in t1_elmer0_ext_intr_handler()
715 			    t1_link_changed(adapter, p);  in t1_elmer0_ext_intr_handler()
724 			phy = adapter->port[0].phy;  in t1_elmer0_ext_intr_handler()
727 				t1_link_changed(adapter, 0);  in t1_elmer0_ext_intr_handler()
732 		if (netif_msg_intr(adapter))  in t1_elmer0_ext_intr_handler()
733 			dev_dbg(&adapter->pdev->dev,  in t1_elmer0_ext_intr_handler()
736 			struct cmac *mac = adapter->port[0].mac;  in t1_elmer0_ext_intr_handler()
743 			t1_tpi_read(adapter,  in t1_elmer0_ext_intr_handler()
745 			if (netif_msg_link(adapter))  in t1_elmer0_ext_intr_handler()
746 				dev_info(&adapter->pdev->dev, "XPAK %s\n",  in t1_elmer0_ext_intr_handler()
751 	t1_tpi_write(adapter, A_ELMER0_INT_CAUSE, cause);  in t1_elmer0_ext_intr_handler()
756 void t1_interrupts_enable(adapter_t *adapter)  in t1_interrupts_enable()  argument
760 	adapter->slow_intr_mask = F_PL_INTR_SGE_ERR | F_PL_INTR_TP;  in t1_interrupts_enable()
762 	t1_sge_intr_enable(adapter->sge);  in t1_interrupts_enable()
763 	t1_tp_intr_enable(adapter->tp);  in t1_interrupts_enable()
764 	if (adapter->espi) {  in t1_interrupts_enable()
765 		adapter->slow_intr_mask |= F_PL_INTR_ESPI;  in t1_interrupts_enable()
766 		t1_espi_intr_enable(adapter->espi);  in t1_interrupts_enable()
770 	for_each_port(adapter, i) {  in t1_interrupts_enable()
771 		adapter->port[i].mac->ops->interrupt_enable(adapter->port[i].mac);  in t1_interrupts_enable()
772 		adapter->port[i].phy->ops->interrupt_enable(adapter->port[i].phy);  in t1_interrupts_enable()
776 	if (t1_is_asic(adapter)) {  in t1_interrupts_enable()
777 		u32 pl_intr = readl(adapter->regs + A_PL_ENABLE);  in t1_interrupts_enable()
780 		pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE,  in t1_interrupts_enable()
783 		adapter->slow_intr_mask |= F_PL_INTR_EXT | F_PL_INTR_PCIX;  in t1_interrupts_enable()
785 		writel(pl_intr, adapter->regs + A_PL_ENABLE);  in t1_interrupts_enable()
790 void t1_interrupts_disable(adapter_t* adapter)  in t1_interrupts_disable()  argument
794 	t1_sge_intr_disable(adapter->sge);  in t1_interrupts_disable()
795 	t1_tp_intr_disable(adapter->tp);  in t1_interrupts_disable()
796 	if (adapter->espi)  in t1_interrupts_disable()
797 		t1_espi_intr_disable(adapter->espi);  in t1_interrupts_disable()
800 	for_each_port(adapter, i) {  in t1_interrupts_disable()
801 		adapter->port[i].mac->ops->interrupt_disable(adapter->port[i].mac);  in t1_interrupts_disable()
802 		adapter->port[i].phy->ops->interrupt_disable(adapter->port[i].phy);  in t1_interrupts_disable()
806 	if (t1_is_asic(adapter))  in t1_interrupts_disable()
807 		writel(0, adapter->regs + A_PL_ENABLE);  in t1_interrupts_disable()
810 	pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE, 0);  in t1_interrupts_disable()
812 	adapter->slow_intr_mask = 0;  in t1_interrupts_disable()
816 void t1_interrupts_clear(adapter_t* adapter)  in t1_interrupts_clear()  argument
820 	t1_sge_intr_clear(adapter->sge);  in t1_interrupts_clear()
821 	t1_tp_intr_clear(adapter->tp);  in t1_interrupts_clear()
822 	if (adapter->espi)  in t1_interrupts_clear()
823 		t1_espi_intr_clear(adapter->espi);  in t1_interrupts_clear()
826 	for_each_port(adapter, i) {  in t1_interrupts_clear()
827 		adapter->port[i].mac->ops->interrupt_clear(adapter->port[i].mac);  in t1_interrupts_clear()
828 		adapter->port[i].phy->ops->interrupt_clear(adapter->port[i].phy);  in t1_interrupts_clear()
832 	if (t1_is_asic(adapter)) {  in t1_interrupts_clear()
833 		u32 pl_intr = readl(adapter->regs + A_PL_CAUSE);  in t1_interrupts_clear()
836 		       adapter->regs + A_PL_CAUSE);  in t1_interrupts_clear()
840 	pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, 0xffffffff);  in t1_interrupts_clear()
846 static int asic_slow_intr(adapter_t *adapter)  in asic_slow_intr()  argument
848 	u32 cause = readl(adapter->regs + A_PL_CAUSE);  in asic_slow_intr()
850 	cause &= adapter->slow_intr_mask;  in asic_slow_intr()
854 		t1_sge_intr_error_handler(adapter->sge);  in asic_slow_intr()
856 		t1_tp_intr_handler(adapter->tp);  in asic_slow_intr()
858 		t1_espi_intr_handler(adapter->espi);  in asic_slow_intr()
860 		t1_pci_intr_handler(adapter);  in asic_slow_intr()
862 		t1_elmer0_ext_intr(adapter);  in asic_slow_intr()
865 	writel(cause, adapter->regs + A_PL_CAUSE);  in asic_slow_intr()
866 	readl(adapter->regs + A_PL_CAUSE); /* flush writes */  in asic_slow_intr()
870 int t1_slow_intr_handler(adapter_t *adapter)  in t1_slow_intr_handler()  argument
873 	if (!t1_is_asic(adapter))  in t1_slow_intr_handler()
874 		return fpga_slow_intr(adapter);  in t1_slow_intr_handler()
876 	return asic_slow_intr(adapter);  in t1_slow_intr_handler()
880 static void power_sequence_xpak(adapter_t* adapter)  in power_sequence_xpak()  argument
886 	t1_tpi_read(adapter, A_ELMER0_GPI_STAT, &mod_detect);  in power_sequence_xpak()
889 		t1_tpi_read(adapter, A_ELMER0_GPO, &gpo);  in power_sequence_xpak()
891 		t1_tpi_write(adapter, A_ELMER0_GPO, gpo);  in power_sequence_xpak()
895 int __devinit t1_get_board_rev(adapter_t *adapter, const struct board_info *bi,  in t1_get_board_rev()  argument
903 		u32 val = readl(adapter->regs + A_TP_PC_CONFIG);  in t1_get_board_rev()
921 static int board_init(adapter_t *adapter, const struct board_info *bi)  in board_init()  argument
928 		t1_tpi_par(adapter, 0xf);  in board_init()
929 		t1_tpi_write(adapter, A_ELMER0_GPO, 0x800);  in board_init()
932 		t1_tpi_par(adapter, 0xf);  in board_init()
933 		t1_tpi_write(adapter, A_ELMER0_GPO, 0x1800);  in board_init()
938 		power_sequence_xpak(adapter);  in board_init()
946 		t1_tpi_par(adapter, 0xf);  in board_init()
947 		t1_tpi_write(adapter, A_ELMER0_GPO, 0x804);  in board_init()
951 		t1_tpi_par(adapter, 0xf);  in board_init()
952 		t1_tpi_write(adapter, A_ELMER0_GPO, 0x1804);  in board_init()
963 int t1_init_hw_modules(adapter_t *adapter)  in t1_init_hw_modules()  argument
966 	const struct board_info *bi = board_info(adapter);  in t1_init_hw_modules()
969 		u32 val = readl(adapter->regs + A_MC4_CFG);  in t1_init_hw_modules()
971 		writel(val | F_READY | F_MC4_SLOW, adapter->regs + A_MC4_CFG);  in t1_init_hw_modules()
973 		       adapter->regs + A_MC5_CONFIG);  in t1_init_hw_modules()
976 	if (adapter->espi && t1_espi_init(adapter->espi, bi->chip_mac,  in t1_init_hw_modules()
980 	if (t1_tp_reset(adapter->tp, &adapter->params.tp, bi->clock_core))  in t1_init_hw_modules()
983 	err = t1_sge_configure(adapter->sge, &adapter->params.sge);  in t1_init_hw_modules()
995 static void __devinit get_pci_mode(adapter_t *adapter, struct chelsio_pci_params *p)  in get_pci_mode()  argument
1000 	pci_read_config_dword(adapter->pdev, A_PCICFG_MODE, &pci_mode);  in get_pci_mode()
1009 void t1_free_sw_modules(adapter_t *adapter)  in t1_free_sw_modules()  argument
1013 	for_each_port(adapter, i) {  in t1_free_sw_modules()
1014 		struct cmac *mac = adapter->port[i].mac;  in t1_free_sw_modules()
1015 		struct cphy *phy = adapter->port[i].phy;  in t1_free_sw_modules()
1023 	if (adapter->sge)  in t1_free_sw_modules()
1024 		t1_sge_destroy(adapter->sge);  in t1_free_sw_modules()
1025 	if (adapter->tp)  in t1_free_sw_modules()
1026 		t1_tp_destroy(adapter->tp);  in t1_free_sw_modules()
1027 	if (adapter->espi)  in t1_free_sw_modules()
1028 		t1_espi_destroy(adapter->espi);  in t1_free_sw_modules()
1052 int __devinit t1_init_sw_modules(adapter_t *adapter,  in t1_init_sw_modules()  argument
1057 	adapter->params.brd_info = bi;  in t1_init_sw_modules()
1058 	adapter->params.nports = bi->port_number;  in t1_init_sw_modules()
1059 	adapter->params.stats_update_period = bi->gmac->stats_update_period;  in t1_init_sw_modules()
1061 	adapter->sge = t1_sge_create(adapter, &adapter->params.sge);  in t1_init_sw_modules()
1062 	if (!adapter->sge) {  in t1_init_sw_modules()
1064 		       adapter->name);  in t1_init_sw_modules()
1068 	if (bi->espi_nports && !(adapter->espi = t1_espi_create(adapter))) {  in t1_init_sw_modules()
1070 		       adapter->name);  in t1_init_sw_modules()
1074 	adapter->tp = t1_tp_create(adapter, &adapter->params.tp);  in t1_init_sw_modules()
1075 	if (!adapter->tp) {  in t1_init_sw_modules()
1077 		       adapter->name);  in t1_init_sw_modules()
1081 	board_init(adapter, bi);  in t1_init_sw_modules()
1082 	bi->mdio_ops->init(adapter, bi);  in t1_init_sw_modules()
1084 		bi->gphy->reset(adapter);  in t1_init_sw_modules()
1086 		bi->gmac->reset(adapter);  in t1_init_sw_modules()
1088 	for_each_port(adapter, i) {  in t1_init_sw_modules()
1093 		adapter->port[i].phy = bi->gphy->create(adapter->port[i].dev,  in t1_init_sw_modules()
1095 		if (!adapter->port[i].phy) {  in t1_init_sw_modules()
1097 			       adapter->name, i);  in t1_init_sw_modules()
1101 		adapter->port[i].mac = mac = bi->gmac->create(adapter, i);  in t1_init_sw_modules()
1104 			       adapter->name, i);  in t1_init_sw_modules()
1112 		if (!t1_is_asic(adapter) || bi->chip_mac == CHBT_MAC_DUMMY)  in t1_init_sw_modules()
1114 		else if (vpd_macaddress_get(adapter, i, hw_addr)) {  in t1_init_sw_modules()
1116 			       adapter->port[i].dev->name);  in t1_init_sw_modules()
1119 		memcpy(adapter->port[i].dev->dev_addr, hw_addr, ETH_ALEN);  in t1_init_sw_modules()
1120 		init_link_config(&adapter->port[i].link_config, bi);  in t1_init_sw_modules()
1123 	get_pci_mode(adapter, &adapter->params.pci);  in t1_init_sw_modules()
1124 	t1_interrupts_clear(adapter);  in t1_init_sw_modules()
1128 	t1_free_sw_modules(adapter);  in t1_init_sw_modules()