Lines Matching defs:tg3
2948 struct tg3 { struct
2971 * updating tg3_flags. argument
2990 u32 (*read32) (struct tg3 *, u32); argument
2991 void (*write32) (struct tg3 *, u32, u32); argument
2992 u32 (*read32_mbox) (struct tg3 *, u32); argument
2993 void (*write32_mbox) (struct tg3 *, u32, argument
3004 void (*write32_tx_mbox) (struct tg3 *, u32, argument
3009 struct tg3_napi napi[TG3_IRQ_MAX_VECS]; argument
3010 void (*write32_rx_mbox) (struct tg3 *, u32, argument
3027 struct tg3_ethtool_stats estats_prev; argument
3049 struct tg3_link_config link_config; argument
3050 struct tg3_bufmgr_config bufmgr_config; argument
3053 u32 rx_mode;
3054 u32 tx_mode;
3055 u32 mac_mode;
3056 u32 mi_mode;
3057 u32 misc_host_ctrl;
3058 u32 grc_mode;
3059 u32 grc_local_ctrl;
3060 u32 dma_rwctrl;
3061 u32 coalesce_mode;
3062 u32 pwrmgmt_thresh;
3065 u32 pci_chip_rev_id;
3066 u16 pci_cmd;
3067 u8 pci_cacheline_sz;
3068 u8 pci_lat_timer;
3070 int pci_fn;
3071 int pm_cap;
3072 int msi_cap;
3073 int pcix_cap;
3074 int pcie_readrq;
3076 struct mii_bus *mdio_bus;
3077 int mdio_irq[PHY_MAX_ADDR];
3079 u8 phy_addr;
3082 u32 phy_id;
3131 u32 phy_flags;
3167 struct tg3_hw_stats *hw_stats; argument
3168 dma_addr_t stats_mapping;
3169 struct work_struct reset_task;
3171 int nvram_lock_cnt;
3172 u32 nvram_size;
3181 u32 nvram_pagesize;
3182 u32 nvram_jedecnum;
3209 unsigned int irq_max;
3210 unsigned int irq_cnt;
3212 struct ethtool_coalesce coal;
3215 const char *fw_needed;
3216 const struct firmware *fw;
3217 u32 fw_len; /* includes BSS */