Lines Matching full:if
187 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
193 #if (NET_IP_ALIGN != 0)
468 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) { in tg3_write_indirect_mbox()
473 if (off == TG3_RX_STD_PROD_IDX_REG) { in tg3_write_indirect_mbox()
487 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) && in tg3_write_indirect_mbox()
508 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
509 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
513 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND)) in _tw32_flush()
519 if (usec_wait) in _tw32_flush()
526 if (usec_wait) in _tw32_flush()
533 if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND)) in tw32_mailbox_flush()
541 if (tg3_flag(tp, TXD_MBOX_HWBUG)) in tg3_write32_tx_mbox()
543 if (tg3_flag(tp, MBOX_WRITE_REORDER)) in tg3_write32_tx_mbox()
572 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 && in tg3_write_mem()
577 if (tg3_flag(tp, SRAM_USE_CONFIG)) { in tg3_write_mem()
597 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 && in tg3_read_mem()
604 if (tg3_flag(tp, SRAM_USE_CONFIG)) { in tg3_read_mem()
625 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) in tg3_ape_lock_init()
640 if (!tp->pci_fn) in tg3_ape_lock_init()
656 if (!tg3_flag(tp, ENABLE_APE)) in tg3_ape_lock()
661 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) in tg3_ape_lock()
665 if (!tp->pci_fn) in tg3_ape_lock()
674 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) { in tg3_ape_lock()
689 if (status == bit) in tg3_ape_lock()
694 if (status != bit) { in tg3_ape_lock()
707 if (!tg3_flag(tp, ENABLE_APE)) in tg3_ape_unlock()
712 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) in tg3_ape_unlock()
716 if (!tp->pci_fn) in tg3_ape_unlock()
725 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) in tg3_ape_unlock()
739 if (tg3_flag(tp, APE_HAS_NCSI)) in tg3_ape_send_event()
743 if (apedata != APE_SEG_SIG_MAGIC) in tg3_ape_send_event()
747 if (!(apedata & APE_FW_STATUS_READY)) in tg3_ape_send_event()
752 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM)) in tg3_ape_send_event()
757 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) in tg3_ape_send_event()
763 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) in tg3_ape_send_event()
769 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) in tg3_ape_send_event()
778 if (!tg3_flag(tp, ENABLE_APE)) in tg3_ape_driver_state_change()
806 if (device_may_wakeup(&tp->pdev->dev) && in tg3_ape_driver_state_change()
855 if (tg3_flag(tp, 1SHOT_MSI)) in tg3_enable_ints()
862 if (!tg3_flag(tp, TAGGED_STATUS) && in tg3_enable_ints()
878 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) { in tg3_has_work()
879 if (sblk->status & SD_STATUS_LINK_CHG) in tg3_has_work()
883 if (sblk->idx[0].tx_consumer != tnapi->tx_cons || in tg3_has_work()
906 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi)) in tg3_int_reenable()
916 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS)) in tg3_switch_clocks()
927 if (tg3_flag(tp, 5705_PLUS)) { in tg3_switch_clocks()
928 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) { in tg3_switch_clocks()
932 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) { in tg3_switch_clocks()
952 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in tg3_readphy()
973 if ((frame_val & MI_COM_BUSY) == 0) { in tg3_readphy()
982 if (loops != 0) { in tg3_readphy()
987 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in tg3_readphy()
1001 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && in tg3_writephy()
1005 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in tg3_writephy()
1024 if ((frame_val & MI_COM_BUSY) == 0) { in tg3_writephy()
1033 if (loops != 0) in tg3_writephy()
1036 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in tg3_writephy()
1049 if (err) in tg3_phy_cl45_write()
1053 if (err) in tg3_phy_cl45_write()
1058 if (err) in tg3_phy_cl45_write()
1072 if (err) in tg3_phy_cl45_read()
1076 if (err) in tg3_phy_cl45_read()
1081 if (err) in tg3_phy_cl45_read()
1095 if (!err) in tg3_phydsp_read()
1106 if (!err) in tg3_phydsp_write()
1119 if (!err) in tg3_phy_auxctl_read()
1127 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC) in tg3_phy_auxctl_write()
1152 if (err != 0) in tg3_bmcr_reset()
1158 if (err != 0) in tg3_bmcr_reset()
1161 if ((phy_control & BMCR_RESET) == 0) { in tg3_bmcr_reset()
1167 if (limit < 0) in tg3_bmcr_reset()
1180 if (tg3_readphy(tp, reg, &val)) in tg3_mdio_read()
1195 if (tg3_writephy(tp, reg, val)) in tg3_mdio_write()
1232 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) { in tg3_mdio_config_5785()
1244 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) in tg3_mdio_config_5785()
1257 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) { in tg3_mdio_config_5785()
1258 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) in tg3_mdio_config_5785()
1260 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) in tg3_mdio_config_5785()
1275 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) { in tg3_mdio_config_5785()
1276 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) in tg3_mdio_config_5785()
1281 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) in tg3_mdio_config_5785()
1295 if (tg3_flag(tp, MDIOBUS_INITED) && in tg3_mdio_start()
1306 if (tg3_flag(tp, 5717_PLUS)) { in tg3_mdio_init()
1311 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) in tg3_mdio_init()
1316 if (is_serdes) in tg3_mdio_init()
1323 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED)) in tg3_mdio_init()
1327 if (tp->mdio_bus == NULL) in tg3_mdio_init()
1349 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN)) in tg3_mdio_init()
1353 if (i) { in tg3_mdio_init()
1361 if (!phydev || !phydev->drv) { in tg3_mdio_init()
1379 if (tg3_flag(tp, RGMII_INBAND_DISABLE)) in tg3_mdio_init()
1381 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) in tg3_mdio_init()
1383 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) in tg3_mdio_init()
1399 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) in tg3_mdio_init()
1407 if (tg3_flag(tp, MDIOBUS_INITED)) { in tg3_mdio_fini()
1435 /* If enough time has passed, no wait is necessary. */ in tg3_wait_for_event_ack()
1439 if (time_remain < 0) in tg3_wait_for_event_ack()
1442 /* Check if we can shorten the wait time. */ in tg3_wait_for_event_ack()
1444 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC) in tg3_wait_for_event_ack()
1449 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT)) in tg3_wait_for_event_ack()
1461 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF)) in tg3_ump_link_report()
1471 if (!tg3_readphy(tp, MII_BMCR, ®)) in tg3_ump_link_report()
1473 if (!tg3_readphy(tp, MII_BMSR, ®)) in tg3_ump_link_report()
1478 if (!tg3_readphy(tp, MII_ADVERTISE, ®)) in tg3_ump_link_report()
1480 if (!tg3_readphy(tp, MII_LPA, ®)) in tg3_ump_link_report()
1485 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) { in tg3_ump_link_report()
1486 if (!tg3_readphy(tp, MII_CTRL1000, ®)) in tg3_ump_link_report()
1488 if (!tg3_readphy(tp, MII_STAT1000, ®)) in tg3_ump_link_report()
1493 if (!tg3_readphy(tp, MII_PHYADDR, ®)) in tg3_ump_link_report()
1505 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) { in tg3_stop_fw()
1524 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) { in tg3_write_sig_pre_reset()
1546 if (kind == RESET_KIND_INIT || in tg3_write_sig_pre_reset()
1554 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) { in tg3_write_sig_post_reset()
1571 if (kind == RESET_KIND_SHUTDOWN) in tg3_write_sig_post_reset()
1578 if (tg3_flag(tp, ENABLE_ASF)) { in tg3_write_sig_legacy()
1606 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { in tg3_poll_fw()
1609 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE) in tg3_poll_fw()
1619 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1) in tg3_poll_fw()
1629 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) { in tg3_poll_fw()
1635 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) { in tg3_poll_fw()
1647 if (!netif_carrier_ok(tp->dev)) { in tg3_link_report()
1650 } else if (netif_msg_link(tp)) { in tg3_link_report()
1665 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) in tg3_link_report()
1677 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX)) in tg3_advert_flowctrl_1000X()
1679 else if (flow_ctrl & FLOW_CTRL_TX) in tg3_advert_flowctrl_1000X()
1681 else if (flow_ctrl & FLOW_CTRL_RX) in tg3_advert_flowctrl_1000X()
1693 if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) { in tg3_resolve_flowctrl_1000X()
1695 } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) { in tg3_resolve_flowctrl_1000X()
1696 if (lcladv & ADVERTISE_1000XPAUSE) in tg3_resolve_flowctrl_1000X()
1698 if (rmtadv & ADVERTISE_1000XPAUSE) in tg3_resolve_flowctrl_1000X()
1712 if (tg3_flag(tp, USE_PHYLIB)) in tg3_setup_flow_control()
1717 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) { in tg3_setup_flow_control()
1718 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_setup_flow_control()
1727 if (flowctrl & FLOW_CTRL_RX) in tg3_setup_flow_control()
1732 if (old_rx_mode != tp->rx_mode) in tg3_setup_flow_control()
1735 if (flowctrl & FLOW_CTRL_TX) in tg3_setup_flow_control()
1740 if (old_tx_mode != tp->tx_mode) in tg3_setup_flow_control()
1758 if (phydev->link) { in tg3_adjust_link()
1762 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10) in tg3_adjust_link()
1764 else if (phydev->speed == SPEED_1000 || in tg3_adjust_link()
1770 if (phydev->duplex == DUPLEX_HALF) in tg3_adjust_link()
1776 if (phydev->pause) in tg3_adjust_link()
1778 if (phydev->asym_pause) in tg3_adjust_link()
1786 if (mac_mode != tp->mac_mode) { in tg3_adjust_link()
1792 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { in tg3_adjust_link()
1793 if (phydev->speed == SPEED_10) in tg3_adjust_link()
1801 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF) in tg3_adjust_link()
1812 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) || in tg3_adjust_link()
1824 if (linkmesg) in tg3_adjust_link()
1832 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) in tg3_phy_init()
1843 if (IS_ERR(phydev)) { in tg3_phy_init()
1852 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_init()
1880 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_phy_start()
1885 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { in tg3_phy_start()
1900 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_phy_stop()
1908 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { in tg3_phy_fini()
1919 if (tp->phy_flags & TG3_PHYFLG_IS_FET) in tg3_phy_set_extloopbk()
1922 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_phy_set_extloopbk()
1933 if (err) in tg3_phy_set_extloopbk()
1948 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { in tg3_phy_fet_toggle_apd()
1953 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) { in tg3_phy_fet_toggle_apd()
1954 if (enable) in tg3_phy_fet_toggle_apd()
1968 if (!tg3_flag(tp, 5705_PLUS) || in tg3_phy_toggle_apd()
1973 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_phy_toggle_apd()
1984 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable) in tg3_phy_toggle_apd()
1993 if (enable) in tg3_phy_toggle_apd()
2003 if (!tg3_flag(tp, 5705_PLUS) || in tg3_phy_toggle_automdix()
2007 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_phy_toggle_automdix()
2010 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) { in tg3_phy_toggle_automdix()
2015 if (!tg3_readphy(tp, reg, &phy)) { in tg3_phy_toggle_automdix()
2016 if (enable) in tg3_phy_toggle_automdix()
2029 if (!ret) { in tg3_phy_toggle_automdix()
2030 if (enable) in tg3_phy_toggle_automdix()
2045 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) in tg3_phy_set_wirespeed()
2049 if (!ret) in tg3_phy_set_wirespeed()
2058 if (!tp->phy_otp) in tg3_phy_apply_otp()
2063 if (TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) in tg3_phy_apply_otp()
2095 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_phy_eee_adjust()
2100 if (tp->link_config.autoneg == AUTONEG_ENABLE && in tg3_phy_eee_adjust()
2107 if (tp->link_config.active_speed == SPEED_1000) in tg3_phy_eee_adjust()
2117 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T || in tg3_phy_eee_adjust()
2122 if (!tp->setlpicnt) { in tg3_phy_eee_adjust()
2123 if (current_link_up == 1 && in tg3_phy_eee_adjust()
2138 if (tp->link_config.active_speed == SPEED_1000 && in tg3_phy_eee_enable()
2160 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) { in tg3_wait_macro_done()
2161 if ((tmp32 & 0x1000) == 0) in tg3_wait_macro_done()
2165 if (limit < 0) in tg3_wait_macro_done()
2193 if (tg3_wait_macro_done(tp)) { in tg3_phy_write_and_check_testpat()
2201 if (tg3_wait_macro_done(tp)) { in tg3_phy_write_and_check_testpat()
2207 if (tg3_wait_macro_done(tp)) { in tg3_phy_write_and_check_testpat()
2215 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) || in tg3_phy_write_and_check_testpat()
2223 if (low != test_pat[chan][i] || in tg3_phy_write_and_check_testpat()
2250 if (tg3_wait_macro_done(tp)) in tg3_phy_reset_chanpat()
2265 if (do_phy_reset) { in tg3_phy_reset_5703_4_5()
2267 if (err) in tg3_phy_reset_5703_4_5()
2273 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) in tg3_phy_reset_5703_4_5()
2284 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig)) in tg3_phy_reset_5703_4_5()
2291 if (err) in tg3_phy_reset_5703_4_5()
2298 if (!err) in tg3_phy_reset_5703_4_5()
2303 if (err) in tg3_phy_reset_5703_4_5()
2315 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) { in tg3_phy_reset_5703_4_5()
2318 } else if (!err) in tg3_phy_reset_5703_4_5()
2324 /* This will reset the tigon3 PHY if there is no valid
2332 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { in tg3_phy_reset()
2339 if (err != 0) in tg3_phy_reset()
2342 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) { in tg3_phy_reset()
2347 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || in tg3_phy_reset()
2351 if (err) in tg3_phy_reset()
2357 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && in tg3_phy_reset()
2360 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) in tg3_phy_reset()
2366 if (err) in tg3_phy_reset()
2369 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) { in tg3_phy_reset()
2376 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX || in tg3_phy_reset()
2379 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) == in tg3_phy_reset()
2387 if (tg3_flag(tp, 5717_PLUS) && in tg3_phy_reset()
2393 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) in tg3_phy_reset()
2399 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) && in tg3_phy_reset()
2406 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) { in tg3_phy_reset()
2411 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) { in tg3_phy_reset()
2412 if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { in tg3_phy_reset()
2418 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) { in tg3_phy_reset()
2419 if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { in tg3_phy_reset()
2421 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) { in tg3_phy_reset()
2434 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_phy_reset()
2437 } else if (tg3_flag(tp, JUMBO_CAPABLE)) { in tg3_phy_reset()
2441 if (!err) in tg3_phy_reset()
2449 if (tg3_flag(tp, JUMBO_CAPABLE)) { in tg3_phy_reset()
2450 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val)) in tg3_phy_reset()
2455 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { in tg3_phy_reset()
2485 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || in tg3_set_function_status()
2495 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || in tg3_set_function_status()
2506 if (!tg3_flag(tp, IS_NIC)) in tg3_pwrsrc_switch_to_vmain()
2509 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || in tg3_pwrsrc_switch_to_vmain()
2512 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO)) in tg3_pwrsrc_switch_to_vmain()
2533 if (!tg3_flag(tp, IS_NIC) || in tg3_pwrsrc_die_with_vmain()
2555 if (!tg3_flag(tp, IS_NIC)) in tg3_pwrsrc_switch_to_vaux()
2558 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || in tg3_pwrsrc_switch_to_vaux()
2567 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || in tg3_pwrsrc_switch_to_vaux()
2591 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { in tg3_pwrsrc_switch_to_vaux()
2607 if (no_gpio2) { in tg3_pwrsrc_switch_to_vaux()
2621 if (!no_gpio2) { in tg3_pwrsrc_switch_to_vaux()
2635 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO)) in tg3_frob_aux_power_5717()
2638 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable) in tg3_frob_aux_power_5717()
2643 if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK) in tg3_frob_aux_power_5717()
2646 if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK) in tg3_frob_aux_power_5717()
2660 if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS)) in tg3_frob_aux_power()
2663 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || in tg3_frob_aux_power()
2671 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) { in tg3_frob_aux_power()
2677 if (dev_peer) { in tg3_frob_aux_power()
2680 if (tg3_flag(tp_peer, INIT_COMPLETE)) in tg3_frob_aux_power()
2683 if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) || in tg3_frob_aux_power()
2689 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) || in tg3_frob_aux_power()
2693 if (need_vaux) in tg3_frob_aux_power()
2701 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2) in tg3_5700_link_polarity()
2703 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) { in tg3_5700_link_polarity()
2704 if (speed != SPEED_10) in tg3_5700_link_polarity()
2706 } else if (speed == SPEED_10) in tg3_5700_link_polarity()
2719 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_power_down_phy()
2720 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { in tg3_power_down_phy()
2732 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { in tg3_power_down_phy()
2738 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_power_down_phy()
2740 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { in tg3_power_down_phy()
2749 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) { in tg3_power_down_phy()
2758 } else if (do_low_power) { in tg3_power_down_phy()
2771 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || in tg3_power_down_phy()
2777 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX || in tg3_power_down_phy()
2791 if (tg3_flag(tp, NVRAM)) { in tg3_nvram_lock()
2794 if (tp->nvram_lock_cnt == 0) { in tg3_nvram_lock()
2797 if (tr32(NVRAM_SWARB) & SWARB_GNT1) in tg3_nvram_lock()
2801 if (i == 8000) { in tg3_nvram_lock()
2814 if (tg3_flag(tp, NVRAM)) { in tg3_nvram_unlock()
2815 if (tp->nvram_lock_cnt > 0) in tg3_nvram_unlock()
2817 if (tp->nvram_lock_cnt == 0) in tg3_nvram_unlock()
2825 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) { in tg3_enable_nvram_access()
2835 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) { in tg3_disable_nvram_access()
2848 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0) in tg3_nvram_read_using_eeprom()
2864 if (tmp & EEPROM_ADDR_COMPLETE) in tg3_nvram_read_using_eeprom()
2868 if (!(tmp & EEPROM_ADDR_COMPLETE)) in tg3_nvram_read_using_eeprom()
2891 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) { in tg3_nvram_exec_cmd()
2897 if (i == NVRAM_CMD_TIMEOUT) in tg3_nvram_exec_cmd()
2905 if (tg3_flag(tp, NVRAM) && in tg3_nvram_phys_addr()
2920 if (tg3_flag(tp, NVRAM) && in tg3_nvram_logical_addr()
2943 if (!tg3_flag(tp, NVRAM)) in tg3_nvram_read()
2948 if (offset > NVRAM_ADDR_MSK) in tg3_nvram_read()
2952 if (ret) in tg3_nvram_read()
2961 if (ret == 0) in tg3_nvram_read()
2976 if (!res) in tg3_nvram_read_be32()
2993 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { in tg3_halt_cpu()
2999 if (offset == RX_CPU_BASE) { in tg3_halt_cpu()
3003 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT) in tg3_halt_cpu()
3014 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT) in tg3_halt_cpu()
3019 if (i >= 10000) { in tg3_halt_cpu()
3026 if (tg3_flag(tp, NVRAM)) in tg3_halt_cpu()
3045 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) { in tg3_load_firmware_cpu()
3052 if (tg3_flag(tp, 5705_PLUS)) in tg3_load_firmware_cpu()
3062 if (!lock_err) in tg3_load_firmware_cpu()
3064 if (err) in tg3_load_firmware_cpu()
3105 if (err) in tg3_load_5701_a0_firmware_fix()
3111 if (err) in tg3_load_5701_a0_firmware_fix()
3119 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base) in tg3_load_5701_a0_firmware_fix()
3126 if (i >= 5) { in tg3_load_5701_a0_firmware_fix()
3146 if (tg3_flag(tp, HW_TSO_1) || in tg3_load_tso_firmware()
3164 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { in tg3_load_tso_firmware()
3176 if (err) in tg3_load_tso_firmware()
3184 if (tr32(cpu_base + CPU_PC) == info.fw_base) in tg3_load_tso_firmware()
3191 if (i >= 5) { in tg3_load_tso_firmware()
3216 if (i == 1 && skip_mac_1) in __tg3_set_mac_addr()
3222 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || in __tg3_set_mac_addr()
3257 if (!err) { in tg3_power_up()
3258 /* Switch out of Vaux if it is a NIC */ in tg3_power_up()
3275 if (tg3_flag(tp, CLKREQ_BUG)) { in tg3_power_down_prepare()
3294 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_power_down_prepare()
3296 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) && in tg3_power_down_prepare()
3315 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) { in tg3_power_down_prepare()
3316 if (tg3_flag(tp, WOL_SPEED_100MB)) in tg3_power_down_prepare()
3330 if (phyid != PHY_ID_BCMAC131) { in tg3_power_down_prepare()
3332 if (phyid == PHY_BCM_OUI_1 || in tg3_power_down_prepare()
3341 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { in tg3_power_down_prepare()
3348 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_power_down_prepare()
3356 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { in tg3_power_down_prepare()
3361 } else if (!tg3_flag(tp, ENABLE_ASF)) { in tg3_power_down_prepare()
3367 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1) in tg3_power_down_prepare()
3372 if (tg3_flag(tp, WOL_CAP)) in tg3_power_down_prepare()
3378 if (device_should_wake) { in tg3_power_down_prepare()
3381 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { in tg3_power_down_prepare()
3382 if (do_low_power && in tg3_power_down_prepare()
3392 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_power_down_prepare()
3398 if (GET_ASIC_REV(tp->pci_chip_rev_id) == in tg3_power_down_prepare()
3402 if (tg3_5700_link_polarity(tp, speed)) in tg3_power_down_prepare()
3411 if (!tg3_flag(tp, 5750_PLUS)) in tg3_power_down_prepare()
3415 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) && in tg3_power_down_prepare()
3419 if (tg3_flag(tp, ENABLE_APE)) in tg3_power_down_prepare()
3431 if (!tg3_flag(tp, WOL_SPEED_100MB) && in tg3_power_down_prepare()
3442 } else if (tg3_flag(tp, 5780_CLASS) || in tg3_power_down_prepare()
3446 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) { in tg3_power_down_prepare()
3449 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || in tg3_power_down_prepare()
3455 } else if (tg3_flag(tp, 5705_PLUS)) { in tg3_power_down_prepare()
3469 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_power_down_prepare()
3472 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || in tg3_power_down_prepare()
3486 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF)) in tg3_power_down_prepare()
3492 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) || in tg3_power_down_prepare()
3498 if (!tg3_flag(tp, ENABLE_ASF)) { in tg3_power_down_prepare()
3503 if (!err) in tg3_power_down_prepare()
3555 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_aux_stat_to_speed_duplex()
3578 if (err) in tg3_phy_autoneg_cfg()
3581 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_autoneg_cfg()
3584 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || in tg3_phy_autoneg_cfg()
3589 if (err) in tg3_phy_autoneg_cfg()
3593 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_phy_autoneg_cfg()
3600 if (!err) { in tg3_phy_autoneg_cfg()
3605 if (advertise & ADVERTISED_100baseT_Full) in tg3_phy_autoneg_cfg()
3608 if (advertise & ADVERTISED_1000baseT_Full) in tg3_phy_autoneg_cfg()
3611 if (err) in tg3_phy_autoneg_cfg()
3619 /* If we advertised any eee advertisements above... */ in tg3_phy_autoneg_cfg()
3620 if (val) in tg3_phy_autoneg_cfg()
3627 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val)) in tg3_phy_autoneg_cfg()
3633 if (!err) in tg3_phy_autoneg_cfg()
3646 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { in tg3_phy_copper_begin()
3649 if (tg3_flag(tp, WOL_SPEED_100MB)) in tg3_phy_copper_begin()
3655 } else if (tp->link_config.speed == SPEED_INVALID) { in tg3_phy_copper_begin()
3656 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) in tg3_phy_copper_begin()
3665 if (tp->link_config.speed == SPEED_1000) { in tg3_phy_copper_begin()
3666 if (tp->link_config.duplex == DUPLEX_FULL) in tg3_phy_copper_begin()
3670 } else if (tp->link_config.speed == SPEED_100) { in tg3_phy_copper_begin()
3671 if (tp->link_config.duplex == DUPLEX_FULL) in tg3_phy_copper_begin()
3676 if (tp->link_config.duplex == DUPLEX_FULL) in tg3_phy_copper_begin()
3686 if (tp->link_config.autoneg == AUTONEG_DISABLE && in tg3_phy_copper_begin()
3708 if (tp->link_config.duplex == DUPLEX_FULL) in tg3_phy_copper_begin()
3711 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) && in tg3_phy_copper_begin()
3718 if (tg3_readphy(tp, MII_BMSR, &tmp) || in tg3_phy_copper_begin()
3721 if (!(tmp & BMSR_LSTATUS)) { in tg3_phy_copper_begin()
3762 if (tp->link_config.active_duplex == DUPLEX_FULL) { in tg3_phy_copper_an_config_ok()
3767 if (tg3_readphy(tp, MII_ADVERTISE, lcladv)) in tg3_phy_copper_an_config_ok()
3770 if ((*lcladv & advmsk) != tgtadv) in tg3_phy_copper_an_config_ok()
3773 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_copper_an_config_ok()
3778 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl)) in tg3_phy_copper_an_config_ok()
3782 if (tg3_ctrl != tgtadv) in tg3_phy_copper_an_config_ok()
3793 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_copper_fetch_rmtadv()
3796 if (tg3_readphy(tp, MII_STAT1000, &val)) in tg3_phy_copper_fetch_rmtadv()
3802 if (tg3_readphy(tp, MII_LPA, rmtadv)) in tg3_phy_copper_fetch_rmtadv()
3829 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in tg3_setup_copper_phy()
3840 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || in tg3_setup_copper_phy()
3845 if (!tg3_readphy(tp, MII_BMSR, &bmsr) && in tg3_setup_copper_phy()
3849 if (force_reset) in tg3_setup_copper_phy()
3852 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_setup_copper_phy()
3854 if (tg3_readphy(tp, MII_BMSR, &bmsr) || in tg3_setup_copper_phy()
3858 if (!(bmsr & BMSR_LSTATUS)) { in tg3_setup_copper_phy()
3860 if (err) in tg3_setup_copper_phy()
3866 if (!tg3_readphy(tp, MII_BMSR, &bmsr) && in tg3_setup_copper_phy()
3873 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) == in tg3_setup_copper_phy()
3878 if (!err) in tg3_setup_copper_phy()
3880 if (err) in tg3_setup_copper_phy()
3884 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || in tg3_setup_copper_phy()
3897 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) in tg3_setup_copper_phy()
3899 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) in tg3_setup_copper_phy()
3902 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || in tg3_setup_copper_phy()
3904 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1) in tg3_setup_copper_phy()
3917 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) { in tg3_setup_copper_phy()
3921 if (!err && !(val & (1 << 10))) { in tg3_setup_copper_phy()
3932 if (!tg3_readphy(tp, MII_BMSR, &bmsr) && in tg3_setup_copper_phy()
3938 if (bmsr & BMSR_LSTATUS) { in tg3_setup_copper_phy()
3944 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) && in tg3_setup_copper_phy()
3956 if (tg3_readphy(tp, MII_BMCR, &bmcr)) in tg3_setup_copper_phy()
3958 if (bmcr && bmcr != 0x7fff) in tg3_setup_copper_phy()
3969 if (tp->link_config.autoneg == AUTONEG_ENABLE) { in tg3_setup_copper_phy()
3970 if ((bmcr & BMCR_ANENABLE) && in tg3_setup_copper_phy()
3975 if (!(bmcr & BMCR_ANENABLE) && in tg3_setup_copper_phy()
3984 if (current_link_up == 1 && in tg3_setup_copper_phy()
3988 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_setup_copper_phy()
3996 if (!tg3_readphy(tp, reg, &val) && (val & bit)) in tg3_setup_copper_phy()
4004 if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { in tg3_setup_copper_phy()
4008 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) || in tg3_setup_copper_phy()
4014 if (current_link_up == 1) { in tg3_setup_copper_phy()
4015 if (tp->link_config.active_speed == SPEED_100 || in tg3_setup_copper_phy()
4020 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) in tg3_setup_copper_phy()
4026 if (tp->link_config.active_duplex == DUPLEX_HALF) in tg3_setup_copper_phy()
4029 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) { in tg3_setup_copper_phy()
4030 if (current_link_up == 1 && in tg3_setup_copper_phy()
4040 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 && in tg3_setup_copper_phy()
4052 if (tg3_flag(tp, USE_LINKCHG_REG)) { in tg3_setup_copper_phy()
4060 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 && in tg3_setup_copper_phy()
4075 if (tg3_flag(tp, CLKREQ_BUG)) { in tg3_setup_copper_phy()
4081 if (tp->link_config.active_speed == SPEED_100 || in tg3_setup_copper_phy()
4086 if (newlnkctl != oldlnkctl) in tg3_setup_copper_phy()
4092 if (current_link_up != netif_carrier_ok(tp->dev)) { in tg3_setup_copper_phy()
4093 if (current_link_up) in tg3_setup_copper_phy()
4175 if (ap->state == ANEG_STATE_UNKNOWN) { in tg3_fiber_aneg_smachine()
4187 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) { in tg3_fiber_aneg_smachine()
4190 if (rx_cfg_reg != ap->ability_match_cfg) { in tg3_fiber_aneg_smachine()
4195 if (++ap->ability_match_count > 1) { in tg3_fiber_aneg_smachine()
4200 if (rx_cfg_reg & ANEG_CFG_ACK) in tg3_fiber_aneg_smachine()
4221 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN)) in tg3_fiber_aneg_smachine()
4227 if (ap->flags & MR_AN_ENABLE) { in tg3_fiber_aneg_smachine()
4257 if (delta > ANEG_STATE_SETTLE_TIME) in tg3_fiber_aneg_smachine()
4271 if (flowctrl & ADVERTISE_1000XPAUSE) in tg3_fiber_aneg_smachine()
4273 if (flowctrl & ADVERTISE_1000XPSE_ASYM) in tg3_fiber_aneg_smachine()
4284 if (ap->ability_match != 0 && ap->rxconfig != 0) in tg3_fiber_aneg_smachine()
4299 if (ap->ack_match != 0) { in tg3_fiber_aneg_smachine()
4300 if ((ap->rxconfig & ~ANEG_CFG_ACK) == in tg3_fiber_aneg_smachine()
4306 } else if (ap->ability_match != 0 && in tg3_fiber_aneg_smachine()
4313 if (ap->rxconfig & ANEG_CFG_INVAL) { in tg3_fiber_aneg_smachine()
4326 if (ap->rxconfig & ANEG_CFG_FD) in tg3_fiber_aneg_smachine()
4328 if (ap->rxconfig & ANEG_CFG_HD) in tg3_fiber_aneg_smachine()
4330 if (ap->rxconfig & ANEG_CFG_PS1) in tg3_fiber_aneg_smachine()
4332 if (ap->rxconfig & ANEG_CFG_PS2) in tg3_fiber_aneg_smachine()
4334 if (ap->rxconfig & ANEG_CFG_RF1) in tg3_fiber_aneg_smachine()
4336 if (ap->rxconfig & ANEG_CFG_RF2) in tg3_fiber_aneg_smachine()
4338 if (ap->rxconfig & ANEG_CFG_NP) in tg3_fiber_aneg_smachine()
4344 if (ap->rxconfig & 0x0008) in tg3_fiber_aneg_smachine()
4346 if (ap->rxconfig & ANEG_CFG_NP) in tg3_fiber_aneg_smachine()
4355 if (ap->ability_match != 0 && in tg3_fiber_aneg_smachine()
4361 if (delta > ANEG_STATE_SETTLE_TIME) { in tg3_fiber_aneg_smachine()
4362 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) { in tg3_fiber_aneg_smachine()
4365 if ((ap->txconfig & ANEG_CFG_NP) == 0 && in tg3_fiber_aneg_smachine()
4386 if (ap->ability_match != 0 && in tg3_fiber_aneg_smachine()
4392 if (delta > ANEG_STATE_SETTLE_TIME) { in tg3_fiber_aneg_smachine()
4443 if (status == ANEG_DONE || status == ANEG_FAILED) in fiber_autoneg()
4456 if (status == ANEG_DONE && in fiber_autoneg()
4470 if (tg3_flag(tp, INIT_COMPLETE) && in tg3_init_bcm8002()
4528 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 && in tg3_setup_fiber_hw_autoneg()
4531 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) in tg3_setup_fiber_hw_autoneg()
4541 if (tp->link_config.autoneg != AUTONEG_ENABLE) { in tg3_setup_fiber_hw_autoneg()
4542 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) { in tg3_setup_fiber_hw_autoneg()
4543 if (workaround) { in tg3_setup_fiber_hw_autoneg()
4546 if (port_a) in tg3_setup_fiber_hw_autoneg()
4555 if (mac_status & MAC_STATUS_PCS_SYNCED) { in tg3_setup_fiber_hw_autoneg()
4566 if (flowctrl & ADVERTISE_1000XPAUSE) in tg3_setup_fiber_hw_autoneg()
4568 if (flowctrl & ADVERTISE_1000XPSE_ASYM) in tg3_setup_fiber_hw_autoneg()
4571 if (sg_dig_ctrl != expected_sg_dig_ctrl) { in tg3_setup_fiber_hw_autoneg()
4572 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) && in tg3_setup_fiber_hw_autoneg()
4582 if (workaround) in tg3_setup_fiber_hw_autoneg()
4590 } else if (mac_status & (MAC_STATUS_PCS_SYNCED | in tg3_setup_fiber_hw_autoneg()
4595 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) && in tg3_setup_fiber_hw_autoneg()
4599 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP) in tg3_setup_fiber_hw_autoneg()
4601 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE) in tg3_setup_fiber_hw_autoneg()
4604 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE) in tg3_setup_fiber_hw_autoneg()
4606 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE) in tg3_setup_fiber_hw_autoneg()
4616 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) { in tg3_setup_fiber_hw_autoneg()
4617 if (tp->serdes_counter) in tg3_setup_fiber_hw_autoneg()
4620 if (workaround) { in tg3_setup_fiber_hw_autoneg()
4623 if (port_a) in tg3_setup_fiber_hw_autoneg()
4635 /* only if we have PCS_SYNC and not */ in tg3_setup_fiber_hw_autoneg()
4638 if ((mac_status & MAC_STATUS_PCS_SYNCED) && in tg3_setup_fiber_hw_autoneg()
4663 if (!(mac_status & MAC_STATUS_PCS_SYNCED)) in tg3_setup_fiber_by_hand()
4666 if (tp->link_config.autoneg == AUTONEG_ENABLE) { in tg3_setup_fiber_by_hand()
4670 if (fiber_autoneg(tp, &txflags, &rxflags)) { in tg3_setup_fiber_by_hand()
4673 if (txflags & ANEG_CFG_PS1) in tg3_setup_fiber_by_hand()
4675 if (txflags & ANEG_CFG_PS2) in tg3_setup_fiber_by_hand()
4678 if (rxflags & MR_LP_ADV_SYM_PAUSE) in tg3_setup_fiber_by_hand()
4680 if (rxflags & MR_LP_ADV_ASYM_PAUSE) in tg3_setup_fiber_by_hand()
4696 if ((tr32(MAC_STATUS) & in tg3_setup_fiber_by_hand()
4703 if (current_link_up == 0 && in tg3_setup_fiber_by_hand()
4737 if (!tg3_flag(tp, HW_AUTONEG) && in tg3_setup_fiber_phy()
4745 if (mac_status == (MAC_STATUS_PCS_SYNCED | in tg3_setup_fiber_phy()
4760 if (tp->phy_id == TG3_PHY_ID_BCM8002) in tg3_setup_fiber_phy()
4771 if (tg3_flag(tp, HW_AUTONEG)) in tg3_setup_fiber_phy()
4784 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED | in tg3_setup_fiber_phy()
4791 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) { in tg3_setup_fiber_phy()
4793 if (tp->link_config.autoneg == AUTONEG_ENABLE && in tg3_setup_fiber_phy()
4802 if (current_link_up == 1) { in tg3_setup_fiber_phy()
4816 if (current_link_up != netif_carrier_ok(tp->dev)) { in tg3_setup_fiber_phy()
4817 if (current_link_up) in tg3_setup_fiber_phy()
4824 if (orig_pause_cfg != now_pause_cfg || in tg3_setup_fiber_phy()
4854 if (force_reset) in tg3_setup_fiber_mii_phy()
4864 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { in tg3_setup_fiber_mii_phy()
4865 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) in tg3_setup_fiber_mii_phy()
4873 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset && in tg3_setup_fiber_mii_phy()
4876 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) { in tg3_setup_fiber_mii_phy()
4888 if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) { in tg3_setup_fiber_mii_phy()
4905 if (tp->link_config.duplex == DUPLEX_FULL) in tg3_setup_fiber_mii_phy()
4908 if (new_bmcr != bmcr) { in tg3_setup_fiber_mii_phy()
4915 if (netif_carrier_ok(tp->dev)) { in tg3_setup_fiber_mii_phy()
4933 if (GET_ASIC_REV(tp->pci_chip_rev_id) == in tg3_setup_fiber_mii_phy()
4935 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) in tg3_setup_fiber_mii_phy()
4944 if (bmsr & BMSR_LSTATUS) { in tg3_setup_fiber_mii_phy()
4947 if (bmcr & BMCR_FULLDPLX) in tg3_setup_fiber_mii_phy()
4955 if (bmcr & BMCR_ANENABLE) { in tg3_setup_fiber_mii_phy()
4961 if (common & (ADVERTISE_1000XHALF | in tg3_setup_fiber_mii_phy()
4963 if (common & ADVERTISE_1000XFULL) in tg3_setup_fiber_mii_phy()
4970 } else if (!tg3_flag(tp, 5780_CLASS)) { in tg3_setup_fiber_mii_phy()
4978 if (current_link_up == 1 && current_duplex == DUPLEX_FULL) in tg3_setup_fiber_mii_phy()
4982 if (tp->link_config.active_duplex == DUPLEX_HALF) in tg3_setup_fiber_mii_phy()
4993 if (current_link_up != netif_carrier_ok(tp->dev)) { in tg3_setup_fiber_mii_phy()
4994 if (current_link_up) in tg3_setup_fiber_mii_phy()
5007 if (tp->serdes_counter) { in tg3_serdes_parallel_detect()
5013 if (!netif_carrier_ok(tp->dev) && in tg3_serdes_parallel_detect()
5018 if (bmcr & BMCR_ANENABLE) { in tg3_serdes_parallel_detect()
5031 if ((phy1 & 0x10) && !(phy2 & 0x20)) { in tg3_serdes_parallel_detect()
5043 } else if (netif_carrier_ok(tp->dev) && in tg3_serdes_parallel_detect()
5052 if (phy2 & 0x20) { in tg3_serdes_parallel_detect()
5070 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_setup_phy()
5072 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_setup_phy()
5077 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) { in tg3_setup_phy()
5081 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5) in tg3_setup_phy()
5083 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25) in tg3_setup_phy()
5095 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) in tg3_setup_phy()
5100 if (tp->link_config.active_speed == SPEED_1000 && in tg3_setup_phy()
5108 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_setup_phy()
5109 if (netif_carrier_ok(tp->dev)) { in tg3_setup_phy()
5117 if (tg3_flag(tp, ASPM_WORKAROUND)) { in tg3_setup_phy()
5119 if (!netif_carrier_ok(tp->dev)) in tg3_setup_phy()
5166 if (tg3_flag(tp, SUPPORT_MSIX)) in tg3_dump_legacy_regs()
5178 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_dump_legacy_regs()
5190 if (tg3_flag(tp, NVRAM)) in tg3_dump_legacy_regs()
5200 if (!regs) { in tg3_dump_state()
5205 if (tg3_flag(tp, PCI_EXPRESS)) { in tg3_dump_state()
5213 if (!regs[i + 0] && !regs[i + 1] && in tg3_dump_state()
5295 if (tg3_flag(tp, ENABLE_TSS)) in tg3_tx()
5305 if (unlikely(skb == NULL)) { in tg3_tx()
5327 if (unlikely(ri->skb != NULL || sw_idx == hw_idx)) in tg3_tx()
5349 if (unlikely(tx_bug)) { in tg3_tx()
5366 if (unlikely(netif_tx_queue_stopped(txq) && in tg3_tx()
5369 if (netif_tx_queue_stopped(txq) && in tg3_tx()
5378 if (!ri->data) in tg3_rx_data_free()
5430 * we leave everything unchanged if we fail. in tg3_alloc_rx_data()
5435 if (!data) in tg3_alloc_rx_data()
5442 if (pci_dma_mapping_error(tp->pdev, mapping)) { in tg3_alloc_rx_data()
5524 * sense from a cache coherency perspective. If only the host writes
5527 * If both the host and chip were to write into the same ring, cache line
5561 if (opaque_key == RXD_OPAQUE_RING_STD) { in tg3_rx()
5567 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) { in tg3_rx()
5577 if ((desc->err_vlan & RXD_ERR_MASK) != 0 && in tg3_rx()
5592 if (len > TG3_RX_COPY_THRESH(tp)) { in tg3_rx()
5597 if (skb_size < 0) in tg3_rx()
5604 if (!skb) { in tg3_rx()
5622 if (skb == NULL) in tg3_rx()
5634 if ((tp->dev->features & NETIF_F_RXCSUM) && in tg3_rx()
5644 if (len > (tp->dev->mtu + ETH_HLEN) && in tg3_rx()
5650 if (desc->type_flags & RXD_FLAG_VLAN && in tg3_rx()
5663 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) { in tg3_rx()
5675 /* Refresh hw_idx to see if there is new work */ in tg3_rx()
5676 if (sw_idx == hw_idx) { in tg3_rx()
5687 if (!tg3_flag(tp, ENABLE_RSS)) { in tg3_rx()
5688 if (work_mask & RXD_OPAQUE_RING_STD) { in tg3_rx()
5694 if (work_mask & RXD_OPAQUE_RING_JUMBO) { in tg3_rx()
5701 } else if (work_mask) { in tg3_rx()
5710 if (tnapi != &tp->napi[1]) in tg3_rx()
5720 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) { in tg3_poll_link()
5723 if (sblk->status & SD_STATUS_LINK_CHG) { in tg3_poll_link()
5727 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_poll_link()
5756 if (spr->rx_std_cons_idx == src_prod_idx) in tg3_rx_prodring_xfer()
5759 if (spr->rx_std_cons_idx < src_prod_idx) in tg3_rx_prodring_xfer()
5772 if (dpr->rx_std_buffers[i].data) { in tg3_rx_prodring_xfer()
5779 if (!cpycnt) in tg3_rx_prodring_xfer()
5814 if (spr->rx_jmb_cons_idx == src_prod_idx) in tg3_rx_prodring_xfer()
5817 if (spr->rx_jmb_cons_idx < src_prod_idx) in tg3_rx_prodring_xfer()
5830 if (dpr->rx_jmb_buffers[i].data) { in tg3_rx_prodring_xfer()
5837 if (!cpycnt) in tg3_rx_prodring_xfer()
5872 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) { in tg3_poll_work()
5874 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) in tg3_poll_work()
5882 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) in tg3_poll_work()
5885 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) { in tg3_poll_work()
5897 if (std_prod_idx != dpr->rx_std_prod_idx) in tg3_poll_work()
5901 if (jmb_prod_idx != dpr->rx_jmb_prod_idx) in tg3_poll_work()
5907 if (err) in tg3_poll_work()
5916 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags)) in tg3_reset_task_schedule()
5936 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) in tg3_poll_msix()
5939 if (unlikely(work_done >= budget)) in tg3_poll_msix()
5951 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons && in tg3_poll_msix()
5975 if (tg3_flag(tp, ERROR_PROCESSED)) in tg3_process_error()
5980 if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) { in tg3_process_error()
5985 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) { in tg3_process_error()
5990 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) { in tg3_process_error()
5995 if (!real_error) in tg3_process_error()
6012 if (sblk->status & SD_STATUS_ERROR) in tg3_poll()
6019 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) in tg3_poll()
6022 if (unlikely(work_done >= budget)) in tg3_poll()
6025 if (tg3_flag(tp, TAGGED_STATUS)) { in tg3_poll()
6036 if (likely(!tg3_has_work(tnapi))) { in tg3_poll()
6119 * If irq_sync is non-zero, then the IRQ handler must be synchronized
6126 if (irq_sync) in tg3_full_lock()
6144 if (tnapi->rx_rcb) in tg3_msi_1shot()
6147 if (likely(!tg3_irq_sync(tp))) in tg3_msi_1shot()
6163 if (tnapi->rx_rcb) in tg3_msi()
6173 if (likely(!tg3_irq_sync(tp))) in tg3_msi()
6191 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) { in tg3_interrupt()
6192 if (tg3_flag(tp, CHIP_RESETTING) || in tg3_interrupt()
6211 if (tg3_irq_sync(tp)) in tg3_interrupt()
6214 if (likely(tg3_has_work(tnapi))) { in tg3_interrupt()
6240 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) { in tg3_interrupt_tagged()
6241 if (tg3_flag(tp, CHIP_RESETTING) || in tg3_interrupt_tagged()
6269 if (tg3_irq_sync(tp)) in tg3_interrupt_tagged()
6287 if ((sblk->status & SD_STATUS_UPDATED) || in tg3_test_isr()
6308 if (err) { in tg3_restart_hw()
6340 if (!netif_running(tp->dev)) { in tg3_reset_task()
6354 if (tg3_flag(tp, TX_RECOVERY_PENDING)) { in tg3_reset_task()
6363 if (err) in tg3_reset_task()
6371 if (!err) in tg3_reset_task()
6381 if (netif_msg_tx_err(tp)) { in tg3_tx_timeout()
6401 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64) in tg3_40bit_overflow_test()
6402 if (tg3_flag(tp, 40BIT_DMA_BUG)) in tg3_40bit_overflow_test()
6427 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8) in tg3_tx_frag_set()
6430 if (tg3_4g_overflow_test(map, len)) in tg3_tx_frag_set()
6433 if (tg3_40bit_overflow_test(tp, map, len)) in tg3_tx_frag_set()
6436 if (tp->dma_limit) { in tg3_tx_frag_set()
6444 if (len <= 8) { in tg3_tx_frag_set()
6460 if (len) { in tg3_tx_frag_set()
6461 if (*budget) { in tg3_tx_frag_set()
6529 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) in tigon3_dma_hwbug_workaround()
6539 if (!new_skb) { in tigon3_dma_hwbug_workaround()
6546 if (pci_dma_mapping_error(tp->pdev, new_addr)) { in tigon3_dma_hwbug_workaround()
6558 if (tg3_tx_frag_set(tnapi, entry, budget, new_addr, in tigon3_dma_hwbug_workaround()
6584 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) { in tg3_tso_bug()
6593 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est) in tg3_tso_bug()
6600 if (IS_ERR(segs)) in tg3_tso_bug()
6632 if (tg3_flag(tp, ENABLE_TSS)) in tg3_start_xmit()
6642 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) { in tg3_start_xmit()
6643 if (!netif_tx_queue_stopped(txq)) { in tg3_start_xmit()
6655 if (skb->ip_summed == CHECKSUM_PARTIAL) in tg3_start_xmit()
6659 if (mss) { in tg3_start_xmit()
6663 if (skb_header_cloned(skb) && in tg3_start_xmit()
6672 if (!skb_is_gso_v6(skb)) { in tg3_start_xmit()
6677 if (unlikely((ETH_HLEN + hdr_len) > 80) && in tg3_start_xmit()
6684 if (tg3_flag(tp, HW_TSO_1) || in tg3_start_xmit()
6695 if (tg3_flag(tp, HW_TSO_3)) { in tg3_start_xmit()
6697 if (hdr_len & 0x10) in tg3_start_xmit()
6700 } else if (tg3_flag(tp, HW_TSO_2)) in tg3_start_xmit()
6702 else if (tg3_flag(tp, HW_TSO_1) || in tg3_start_xmit()
6704 if (tcp_opt_len || iph->ihl > 5) { in tg3_start_xmit()
6711 if (tcp_opt_len || iph->ihl > 5) { in tg3_start_xmit()
6720 if (tg3_flag(tp, USE_JUMBO_BDFLAG) && in tg3_start_xmit()
6724 if (vlan_tx_tag_present(skb)) { in tg3_start_xmit()
6732 if (pci_dma_mapping_error(tp->pdev, mapping)) in tg3_start_xmit()
6741 if (tg3_flag(tp, 5701_DMA_BUG)) in tg3_start_xmit()
6744 if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags | in tg3_start_xmit()
6749 } else if (skb_shinfo(skb)->nr_frags > 0) { in tg3_start_xmit()
6752 if (!tg3_flag(tp, HW_TSO_1) && in tg3_start_xmit()
6768 if (dma_mapping_error(&tp->pdev->dev, mapping)) in tg3_start_xmit()
6771 if (!budget || in tg3_start_xmit()
6782 if (would_hit_hwbug) { in tg3_start_xmit()
6785 /* If the workaround fails due to memory/mapping in tg3_start_xmit()
6790 if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget, in tg3_start_xmit()
6802 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) { in tg3_start_xmit()
6811 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)) in tg3_start_xmit()
6830 if (enable) { in tg3_mac_loopback()
6836 if (!tg3_flag(tp, 5705_PLUS)) in tg3_mac_loopback()
6839 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) in tg3_mac_loopback()
6846 if (tg3_flag(tp, 5705_PLUS) || in tg3_mac_loopback()
6863 if (extlpbk && tg3_phy_set_extloopbk(tp)) in tg3_phy_lpbk_set()
6875 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_phy_lpbk_set()
6884 if (extlpbk) { in tg3_phy_lpbk_set()
6885 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) { in tg3_phy_lpbk_set()
6901 if (tp->phy_flags & TG3_PHYFLG_IS_FET) in tg3_phy_lpbk_set()
6906 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && in tg3_phy_lpbk_set()
6917 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_phy_lpbk_set()
6926 if (speed == SPEED_1000) in tg3_phy_lpbk_set()
6931 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) { in tg3_phy_lpbk_set()
6934 if (masked_phy_id == TG3_PHY_ID_BCM5401) in tg3_phy_lpbk_set()
6936 else if (masked_phy_id == TG3_PHY_ID_BCM5411) in tg3_phy_lpbk_set()
6953 if (features & NETIF_F_LOOPBACK) { in tg3_set_loopback()
6954 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK) in tg3_set_loopback()
6963 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) in tg3_set_loopback()
6980 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS)) in tg3_fix_features()
6990 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev)) in tg3_set_features()
7001 if (new_mtu > ETH_DATA_LEN) { in tg3_set_mtu()
7002 if (tg3_flag(tp, 5780_CLASS)) { in tg3_set_mtu()
7009 if (tg3_flag(tp, 5780_CLASS)) { in tg3_set_mtu()
7022 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp)) in tg3_change_mtu()
7025 if (!netif_running(dev)) { in tg3_change_mtu()
7045 if (!err) in tg3_change_mtu()
7050 if (!err) in tg3_change_mtu()
7061 if (tpr != &tp->napi[0].prodring) { in tg3_rx_prodring_free()
7067 if (tg3_flag(tp, JUMBO_CAPABLE)) { in tg3_rx_prodring_free()
7083 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) { in tg3_rx_prodring_free()
7107 if (tpr != &tp->napi[0].prodring) { in tg3_rx_prodring_alloc()
7110 if (tpr->rx_jmb_buffers) in tg3_rx_prodring_alloc()
7120 if (tg3_flag(tp, 5780_CLASS) && in tg3_rx_prodring_alloc()
7141 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) { in tg3_rx_prodring_alloc()
7146 if (i == 0) in tg3_rx_prodring_alloc()
7153 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS)) in tg3_rx_prodring_alloc()
7158 if (!tg3_flag(tp, JUMBO_RING_ENABLE)) in tg3_rx_prodring_alloc()
7173 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) { in tg3_rx_prodring_alloc()
7178 if (i == 0) in tg3_rx_prodring_alloc()
7200 if (tpr->rx_std) { in tg3_rx_prodring_fini()
7205 if (tpr->rx_jmb) { in tg3_rx_prodring_fini()
7217 if (!tpr->rx_std_buffers) in tg3_rx_prodring_init()
7224 if (!tpr->rx_std) in tg3_rx_prodring_init()
7227 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) { in tg3_rx_prodring_init()
7230 if (!tpr->rx_jmb_buffers) in tg3_rx_prodring_init()
7237 if (!tpr->rx_jmb) in tg3_rx_prodring_init()
7264 if (!tnapi->tx_buffers) in tg3_free_rings()
7270 if (!skb) in tg3_free_rings()
7307 if (tnapi->tx_ring) in tg3_init_rings()
7311 if (tnapi->rx_rcb) in tg3_init_rings()
7314 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) { in tg3_init_rings()
7334 if (tnapi->tx_ring) { in tg3_free_consistent()
7343 if (tnapi->rx_rcb) { in tg3_free_consistent()
7353 if (tnapi->hw_status) { in tg3_free_consistent()
7361 if (tp->hw_stats) { in tg3_free_consistent()
7380 if (!tp->hw_stats) in tg3_alloc_consistent()
7393 if (!tnapi->hw_status) in tg3_alloc_consistent()
7399 if (tg3_rx_prodring_init(tp, &tnapi->prodring)) in tg3_alloc_consistent()
7402 /* If multivector TSS is enabled, vector 0 does not handle in tg3_alloc_consistent()
7405 if ((!i && !tg3_flag(tp, ENABLE_TSS)) || in tg3_alloc_consistent()
7410 if (!tnapi->tx_buffers) in tg3_alloc_consistent()
7417 if (!tnapi->tx_ring) in tg3_alloc_consistent()
7443 * If multivector RSS is enabled, vector 0 does not handle in tg3_alloc_consistent()
7446 if (!i && tg3_flag(tp, ENABLE_RSS)) in tg3_alloc_consistent()
7453 if (!tnapi->rx_rcb) in tg3_alloc_consistent()
7476 if (tg3_flag(tp, 5705_PLUS)) { in tg3_stop_block()
7500 if ((val & enable_bit) == 0) in tg3_stop_block()
7504 if (i == MAX_WAIT_CNT && !silent) { in tg3_stop_block()
7549 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE)) in tg3_abort_hw()
7552 if (i >= MAX_WAIT_CNT) { in tg3_abort_hw()
7571 if (tnapi->hw_status) in tg3_abort_hw()
7595 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && in tg3_restore_pci_state()
7599 if (tg3_flag(tp, ENABLE_APE)) in tg3_restore_pci_state()
7607 if (!tg3_flag(tp, PCI_EXPRESS)) { in tg3_restore_pci_state()
7615 if (tg3_flag(tp, PCIX_MODE)) { in tg3_restore_pci_state()
7625 if (tg3_flag(tp, 5780_CLASS)) { in tg3_restore_pci_state()
7630 if (tg3_flag(tp, USING_MSI)) { in tg3_restore_pci_state()
7667 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || in tg3_chip_reset()
7678 if (write_op == tg3_write_flush_reg32) in tg3_chip_reset()
7690 if (tnapi->hw_status) { in tg3_chip_reset()
7702 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { in tg3_chip_reset()
7710 if (tg3_flag(tp, PCI_EXPRESS)) { in tg3_chip_reset()
7712 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && in tg3_chip_reset()
7718 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) { in tg3_chip_reset()
7724 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { in tg3_chip_reset()
7731 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT)) in tg3_chip_reset()
7744 * properly if the PCI write is posted for a long period in tg3_chip_reset()
7764 if (tg3_flag(tp, PCI_EXPRESS) && pci_pcie_cap(tp->pdev)) { in tg3_chip_reset()
7767 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) { in tg3_chip_reset()
7790 if (!tg3_flag(tp, CPMU_PRESENT)) in tg3_chip_reset()
7811 if (tg3_flag(tp, 5780_CLASS)) in tg3_chip_reset()
7815 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) { in tg3_chip_reset()
7822 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) { in tg3_chip_reset()
7828 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 && in tg3_chip_reset()
7831 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) in tg3_chip_reset()
7836 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_chip_reset()
7839 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { in tg3_chip_reset()
7851 if (err) in tg3_chip_reset()
7856 if (tg3_flag(tp, PCI_EXPRESS) && in tg3_chip_reset()
7865 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { in tg3_chip_reset()
7874 if (val == NIC_SRAM_DATA_SIG_MAGIC) { in tg3_chip_reset()
7878 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { in tg3_chip_reset()
7881 if (tg3_flag(tp, 5750_PLUS)) in tg3_chip_reset()
7909 if (tp->hw_stats) { in tg3_halt()
7918 if (err) in tg3_halt()
7930 if (!is_valid_ether_addr(addr->sa_data)) in tg3_set_mac_addr()
7935 if (!netif_running(dev)) in tg3_set_mac_addr()
7938 if (tg3_flag(tp, ENABLE_ASF)) { in tg3_set_mac_addr()
7946 /* Skip MAC addr 1 if ASF is using it. */ in tg3_set_mac_addr()
7947 if ((addr0_high != addr1_high || addr0_low != addr1_low) && in tg3_set_mac_addr()
7973 if (!tg3_flag(tp, 5705_PLUS)) in tg3_set_bdinfo()
7984 if (!tg3_flag(tp, ENABLE_TSS)) { in __tg3_set_coalesce()
7994 if (!tg3_flag(tp, ENABLE_RSS)) { in __tg3_set_coalesce()
8004 if (!tg3_flag(tp, 5705_PLUS)) { in __tg3_set_coalesce()
8010 if (!netif_carrier_ok(tp->dev)) in __tg3_set_coalesce()
8026 if (tg3_flag(tp, ENABLE_TSS)) { in __tg3_set_coalesce()
8041 if (tg3_flag(tp, ENABLE_TSS)) { in __tg3_set_coalesce()
8057 if (!tg3_flag(tp, 5705_PLUS)) in tg3_rings_reset()
8059 else if (tg3_flag(tp, 5717_PLUS)) in tg3_rings_reset()
8061 else if (tg3_flag(tp, 57765_CLASS)) in tg3_rings_reset()
8073 if (tg3_flag(tp, 5717_PLUS)) in tg3_rings_reset()
8075 else if (!tg3_flag(tp, 5705_PLUS)) in tg3_rings_reset()
8077 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || in tg3_rings_reset()
8095 if (tg3_flag(tp, SUPPORT_MSIX)) { in tg3_rings_reset()
8099 if (tg3_flag(tp, ENABLE_TSS)) in tg3_rings_reset()
8107 if (!tg3_flag(tp, ENABLE_TSS)) in tg3_rings_reset()
8117 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_rings_reset()
8135 if (tnapi->tx_ring) { in tg3_rings_reset()
8143 if (tnapi->rx_rcb) { in tg3_rings_reset()
8160 if (tnapi->tx_ring) { in tg3_rings_reset()
8181 if (!tg3_flag(tp, 5750_PLUS) || in tg3_setup_rxbd_thresholds()
8187 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || in tg3_setup_rxbd_thresholds()
8199 if (tg3_flag(tp, 57765_PLUS)) in tg3_setup_rxbd_thresholds()
8202 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS)) in tg3_setup_rxbd_thresholds()
8212 if (tg3_flag(tp, 57765_PLUS)) in tg3_setup_rxbd_thresholds()
8229 if (!tg3_flag(tp, SUPPORT_MSIX)) in tg3_rss_check_indir_tbl()
8232 if (tp->irq_cnt <= 2) { in tg3_rss_check_indir_tbl()
8239 if (tp->rss_ind_tbl[i] >= tp->irq_cnt - 1) in tg3_rss_check_indir_tbl()
8243 if (i != TG3_RSS_INDIR_TBL_SIZE) in tg3_rss_check_indir_tbl()
8277 if (tg3_flag(tp, INIT_COMPLETE)) in tg3_reset_hw()
8281 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) { in tg3_reset_hw()
8294 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) in tg3_reset_hw()
8297 if (tg3_flag(tp, ENABLE_APE)) in tg3_reset_hw()
8311 if (reset_phy) in tg3_reset_hw()
8315 if (err) in tg3_reset_hw()
8320 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) { in tg3_reset_hw()
8341 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { in tg3_reset_hw()
8356 if (tg3_flag(tp, L1PLLPD_EN)) { in tg3_reset_hw()
8370 if (tg3_flag(tp, 57765_CLASS)) { in tg3_reset_hw()
8371 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) { in tg3_reset_hw()
8386 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_57765_AX) { in tg3_reset_hw()
8411 * chips and don't even touch the clocks if the CPMU is present. in tg3_reset_hw()
8413 if (!tg3_flag(tp, CPMU_PRESENT)) { in tg3_reset_hw()
8414 if (!tg3_flag(tp, PCI_EXPRESS)) in tg3_reset_hw()
8419 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && in tg3_reset_hw()
8426 if (tg3_flag(tp, ENABLE_APE)) { in tg3_reset_hw()
8437 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) { in tg3_reset_hw()
8450 if (err) in tg3_reset_hw()
8453 if (tg3_flag(tp, 57765_PLUS)) { in tg3_reset_hw()
8456 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) in tg3_reset_hw()
8458 if (!tg3_flag(tp, 57765_CLASS) && in tg3_reset_hw()
8462 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 && in tg3_reset_hw()
8495 if (tg3_flag(tp, 5750_PLUS)) { in tg3_reset_hw()
8497 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) { in tg3_reset_hw()
8499 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) in tg3_reset_hw()
8505 } else if (tg3_flag(tp, TSO_CAPABLE)) { in tg3_reset_hw()
8516 if (tp->dev->mtu <= ETH_DATA_LEN) { in tg3_reset_hw()
8537 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) in tg3_reset_hw()
8539 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || in tg3_reset_hw()
8545 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE) in tg3_reset_hw()
8549 if (i >= 2000) { in tg3_reset_hw()
8554 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1) in tg3_reset_hw()
8580 if (!tg3_flag(tp, 5717_PLUS)) in tg3_reset_hw()
8585 if (!tg3_flag(tp, 5705_PLUS)) in tg3_reset_hw()
8592 if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 || in tg3_reset_hw()
8595 if (tg3_flag(tp, JUMBO_RING_ENABLE)) { in tg3_reset_hw()
8604 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) || in tg3_reset_hw()
8613 if (tg3_flag(tp, 57765_PLUS)) { in tg3_reset_hw()
8640 /* The slot time is changed by tg3_setup_phy if we in tg3_reset_hw()
8647 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) in tg3_reset_hw()
8667 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) in tg3_reset_hw()
8670 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || in tg3_reset_hw()
8677 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && in tg3_reset_hw()
8679 if (tg3_flag(tp, TSO_CAPABLE) && in tg3_reset_hw()
8682 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && in tg3_reset_hw()
8688 if (tg3_flag(tp, PCI_EXPRESS)) in tg3_reset_hw()
8691 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766) in tg3_reset_hw()
8694 if (tg3_flag(tp, HW_TSO_1) || in tg3_reset_hw()
8699 if (tg3_flag(tp, 57765_PLUS) || in tg3_reset_hw()
8704 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) in tg3_reset_hw()
8707 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || in tg3_reset_hw()
8713 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || in tg3_reset_hw()
8726 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || in tg3_reset_hw()
8735 if (tg3_flag(tp, 5750_PLUS)) { in tg3_reset_hw()
8739 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) && in tg3_reset_hw()
8756 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE)) in tg3_reset_hw()
8763 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_reset_hw()
8789 if (!tg3_flag(tp, 5705_PLUS)) in tg3_reset_hw()
8792 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { in tg3_reset_hw()
8802 if (tg3_flag(tp, ENABLE_APE)) in tg3_reset_hw()
8804 if (!tg3_flag(tp, 5705_PLUS) && in tg3_reset_hw()
8812 * If TG3_FLAG_IS_NIC is zero, we should read the in tg3_reset_hw()
8817 if (!tg3_flag(tp, IS_NIC)) { in tg3_reset_hw()
8824 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) in tg3_reset_hw()
8828 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) in tg3_reset_hw()
8835 if (tg3_flag(tp, EEPROM_WRITE_PROT)) in tg3_reset_hw()
8842 if (tg3_flag(tp, USING_MSIX)) { in tg3_reset_hw()
8845 if (tp->irq_cnt > 1) in tg3_reset_hw()
8847 if (!tg3_flag(tp, 1SHOT_MSI)) in tg3_reset_hw()
8852 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_reset_hw()
8863 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && in tg3_reset_hw()
8865 if (tg3_flag(tp, TSO_CAPABLE) && in tg3_reset_hw()
8869 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && in tg3_reset_hw()
8876 if (tg3_flag(tp, 5755_PLUS)) in tg3_reset_hw()
8879 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) in tg3_reset_hw()
8885 if (tg3_flag(tp, PCIX_MODE)) { in tg3_reset_hw()
8890 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) { in tg3_reset_hw()
8893 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { in tg3_reset_hw()
8905 if (!tg3_flag(tp, 5705_PLUS)) in tg3_reset_hw()
8908 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) in tg3_reset_hw()
8917 if (tg3_flag(tp, LRG_PROD_RING_CAP)) in tg3_reset_hw()
8921 if (tg3_flag(tp, HW_TSO_1) || in tg3_reset_hw()
8926 if (tg3_flag(tp, ENABLE_TSS)) in tg3_reset_hw()
8931 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) { in tg3_reset_hw()
8933 if (err) in tg3_reset_hw()
8937 if (tg3_flag(tp, TSO_CAPABLE)) { in tg3_reset_hw()
8939 if (err) in tg3_reset_hw()
8945 if (tg3_flag(tp, 5755_PLUS) || in tg3_reset_hw()
8949 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { in tg3_reset_hw()
8958 if (tg3_flag(tp, ENABLE_RSS)) { in tg3_reset_hw()
8975 if (tg3_flag(tp, 5755_PLUS)) in tg3_reset_hw()
8978 if (tg3_flag(tp, ENABLE_RSS)) in tg3_reset_hw()
8992 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_reset_hw()
8999 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_reset_hw()
9000 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) && in tg3_reset_hw()
9003 /* only if the signal pre-emphasis bit is not set */ in tg3_reset_hw()
9009 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) in tg3_reset_hw()
9016 if (tg3_flag(tp, 57765_CLASS)) in tg3_reset_hw()
9022 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 && in tg3_reset_hw()
9028 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_reset_hw()
9039 if (!tg3_flag(tp, USE_PHYLIB)) { in tg3_reset_hw()
9040 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { in tg3_reset_hw()
9048 if (err) in tg3_reset_hw()
9051 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_reset_hw()
9056 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) { in tg3_reset_hw()
9072 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) in tg3_reset_hw()
9076 if (tg3_flag(tp, ENABLE_ASF)) in tg3_reset_hw()
9114 if (tg3_flag(tp, ENABLE_APE)) in tg3_reset_hw()
9139 if ((PSTAT)->low < __val) \
9147 if (!netif_carrier_ok(tp->dev)) in tg3_periodic_fetch_stats()
9180 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 && in tg3_periodic_fetch_stats()
9187 if (val) { in tg3_periodic_fetch_stats()
9190 if (sp->rx_discards.low < val) in tg3_periodic_fetch_stats()
9205 if (tg3_has_work(tnapi)) { in tg3_chk_missed_msi()
9206 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr && in tg3_chk_missed_msi()
9208 if (tnapi->chk_msi_cnt < 1) { in tg3_chk_missed_msi()
9225 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING)) in tg3_timer()
9230 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || in tg3_timer()
9234 if (!tg3_flag(tp, TAGGED_STATUS)) { in tg3_timer()
9239 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) { in tg3_timer()
9247 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { in tg3_timer()
9255 if (!--tp->timer_counter) { in tg3_timer()
9256 if (tg3_flag(tp, 5705_PLUS)) in tg3_timer()
9259 if (tp->setlpicnt && !--tp->setlpicnt) in tg3_timer()
9262 if (tg3_flag(tp, USE_LINKCHG_REG)) { in tg3_timer()
9269 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) { in tg3_timer()
9270 if (mac_stat & MAC_STATUS_MI_INTERRUPT) in tg3_timer()
9272 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED) in tg3_timer()
9275 if (phy_event) in tg3_timer()
9277 } else if (tg3_flag(tp, POLL_SERDES)) { in tg3_timer()
9281 if (netif_carrier_ok(tp->dev) && in tg3_timer()
9285 if (!netif_carrier_ok(tp->dev) && in tg3_timer()
9290 if (need_setup) { in tg3_timer()
9291 if (!tp->serdes_counter) { in tg3_timer()
9301 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_timer()
9315 * If the FIFO is full, ASF will no longer function properly. in tg3_timer()
9326 if (!--tp->asf_counter) { in tg3_timer()
9327 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) { in tg3_timer()
9355 if (tp->irq_cnt == 1) in tg3_request_irq()
9363 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) { in tg3_request_irq()
9365 if (tg3_flag(tp, 1SHOT_MSI)) in tg3_request_irq()
9370 if (tg3_flag(tp, TAGGED_STATUS)) in tg3_request_irq()
9385 if (!netif_running(dev)) in tg3_test_interrupt()
9396 if (tg3_flag(tp, 57765_PLUS)) { in tg3_test_interrupt()
9403 if (err) in tg3_test_interrupt()
9418 if ((int_mbox != 0) || in tg3_test_interrupt()
9424 if (tg3_flag(tp, 57765_PLUS) && in tg3_test_interrupt()
9437 if (err) in tg3_test_interrupt()
9440 if (intr_ok) { in tg3_test_interrupt()
9442 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) { in tg3_test_interrupt()
9452 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
9460 if (!tg3_flag(tp, USING_MSI)) in tg3_test_msi()
9474 if (!err) in tg3_test_msi()
9478 if (err != -EIO) in tg3_test_msi()
9494 if (err) in tg3_test_msi()
9507 if (err) in tg3_test_msi()
9517 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) { in tg3_request_firmware()
9531 if (tp->fw_len < (tp->fw->size - 12)) { in tg3_request_firmware()
9550 if (tp->irq_cnt > 1) { in tg3_enable_msix()
9565 if (rc < 0) { in tg3_enable_msix()
9567 } else if (rc != 0) { in tg3_enable_msix()
9568 if (pci_enable_msix(tp->pdev, msix_ent, rc)) in tg3_enable_msix()
9580 if (netif_set_real_num_rx_queues(tp->dev, rc)) { in tg3_enable_msix()
9585 if (tp->irq_cnt > 1) { in tg3_enable_msix()
9588 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || in tg3_enable_msix()
9600 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) && in tg3_ints_init()
9610 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp)) in tg3_ints_init()
9612 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0) in tg3_ints_init()
9615 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) { in tg3_ints_init()
9617 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1) in tg3_ints_init()
9619 if (!tg3_flag(tp, 1SHOT_MSI)) in tg3_ints_init()
9624 if (!tg3_flag(tp, USING_MSIX)) { in tg3_ints_init()
9634 if (tg3_flag(tp, USING_MSIX)) in tg3_ints_fini()
9636 else if (tg3_flag(tp, USING_MSI)) in tg3_ints_fini()
9649 if (tp->fw_needed) { in tg3_open()
9651 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) { in tg3_open()
9652 if (err) in tg3_open()
9654 } else if (err) { in tg3_open()
9657 } else if (!tg3_flag(tp, TSO_CAPABLE)) { in tg3_open()
9666 if (err) in tg3_open()
9688 if (err) in tg3_open()
9698 if (err) { in tg3_open()
9710 if (err) { in tg3_open()
9714 if (tg3_flag(tp, TAGGED_STATUS) && in tg3_open()
9735 if (err) in tg3_open()
9738 if (tg3_flag(tp, USING_MSI)) { in tg3_open()
9741 if (err) { in tg3_open()
9750 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) { in tg3_open()
9771 * Reset loopback feature if it was turned on while the device was down in tg3_open()
9774 if (dev->features & NETIF_F_LOOPBACK) in tg3_open()
9852 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_calc_crc_errors()
9857 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) { in tg3_calc_crc_errors()
9881 if (!hw_stats) in tg3_get_estats()
10035 if (tmp) in calc_crc()
10060 #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE) in __tg3_set_rx_mode()
10064 if (!tg3_flag(tp, ENABLE_ASF)) in __tg3_set_rx_mode()
10068 if (dev->flags & IFF_PROMISC) { in __tg3_set_rx_mode()
10071 } else if (dev->flags & IFF_ALLMULTI) { in __tg3_set_rx_mode()
10074 } else if (netdev_mc_empty(dev)) { in __tg3_set_rx_mode()
10099 if (rx_mode != tp->rx_mode) { in __tg3_set_rx_mode()
10110 if (!netif_running(dev)) in tg3_set_rx_mode()
10132 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) in tg3_get_regs()
10157 if (tg3_flag(tp, NO_NVRAM)) in tg3_get_eeprom()
10160 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) in tg3_get_eeprom()
10169 if (offset & 3) { in tg3_get_eeprom()
10173 if (b_count > len) { in tg3_get_eeprom()
10178 if (ret) in tg3_get_eeprom()
10190 if (ret) { in tg3_get_eeprom()
10198 if (len & 3) { in tg3_get_eeprom()
10204 if (ret) in tg3_get_eeprom()
10222 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) in tg3_set_eeprom()
10225 if (tg3_flag(tp, NO_NVRAM) || in tg3_set_eeprom()
10232 if ((b_offset = (offset & 3))) { in tg3_set_eeprom()
10235 if (ret) in tg3_set_eeprom()
10239 if (len < 4) in tg3_set_eeprom()
10244 if (len & 3) { in tg3_set_eeprom()
10249 if (ret) in tg3_set_eeprom()
10254 if (b_offset || odd_len) { in tg3_set_eeprom()
10256 if (!buf) in tg3_set_eeprom()
10258 if (b_offset) in tg3_set_eeprom()
10260 if (odd_len) in tg3_set_eeprom()
10267 if (buf != data) in tg3_set_eeprom()
10277 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_get_settings()
10279 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_get_settings()
10287 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) in tg3_get_settings()
10291 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_get_settings()
10304 if (tg3_flag(tp, PAUSE_AUTONEG)) { in tg3_get_settings()
10305 if (tp->link_config.flowctrl & FLOW_CTRL_RX) { in tg3_get_settings()
10306 if (tp->link_config.flowctrl & FLOW_CTRL_TX) { in tg3_get_settings()
10312 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) { in tg3_get_settings()
10316 if (netif_running(dev) && netif_carrier_ok(dev)) { in tg3_get_settings()
10320 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_get_settings()
10321 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE) in tg3_get_settings()
10344 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_set_settings()
10346 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_set_settings()
10352 if (cmd->autoneg != AUTONEG_ENABLE && in tg3_set_settings()
10356 if (cmd->autoneg == AUTONEG_DISABLE && in tg3_set_settings()
10361 if (cmd->autoneg == AUTONEG_ENABLE) { in tg3_set_settings()
10366 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) in tg3_set_settings()
10370 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_set_settings()
10379 if (cmd->advertising & ~mask) in tg3_set_settings()
10391 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) { in tg3_set_settings()
10392 if (speed != SPEED_1000) in tg3_set_settings()
10395 if (cmd->duplex != DUPLEX_FULL) in tg3_set_settings()
10398 if (speed != SPEED_100 && in tg3_set_settings()
10407 if (cmd->autoneg == AUTONEG_ENABLE) { in tg3_set_settings()
10422 if (netif_running(dev)) in tg3_set_settings()
10444 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev)) in tg3_get_wol()
10449 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev)) in tg3_get_wol()
10459 if (wol->wolopts & ~WAKE_MAGIC) in tg3_set_wol()
10461 if ((wol->wolopts & WAKE_MAGIC) && in tg3_set_wol()
10468 if (device_may_wakeup(dp)) in tg3_set_wol()
10494 if (!netif_running(dev)) in tg3_nway_reset()
10497 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_nway_reset()
10500 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_nway_reset()
10501 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_nway_reset()
10510 if (!tg3_readphy(tp, MII_BMCR, &bmcr) && in tg3_nway_reset()
10528 if (tg3_flag(tp, JUMBO_RING_ENABLE)) in tg3_get_ringparam()
10536 if (tg3_flag(tp, JUMBO_RING_ENABLE)) in tg3_get_ringparam()
10549 if ((ering->rx_pending > tp->rx_std_ring_mask) || in tg3_set_ringparam()
10557 if (netif_running(dev)) { in tg3_set_ringparam()
10567 if (tg3_flag(tp, MAX_RXPEND_64) && in tg3_set_ringparam()
10575 if (netif_running(dev)) { in tg3_set_ringparam()
10578 if (!err) in tg3_set_ringparam()
10584 if (irq_sync && !err) in tg3_set_ringparam()
10596 if (tp->link_config.flowctrl & FLOW_CTRL_RX) in tg3_get_pauseparam()
10601 if (tp->link_config.flowctrl & FLOW_CTRL_TX) in tg3_get_pauseparam()
10612 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_set_pauseparam()
10618 if (!(phydev->supported & SUPPORTED_Pause) || in tg3_set_pauseparam()
10624 if (epause->rx_pause) { in tg3_set_pauseparam()
10627 if (epause->tx_pause) { in tg3_set_pauseparam()
10633 } else if (epause->tx_pause) { in tg3_set_pauseparam()
10639 if (epause->autoneg) in tg3_set_pauseparam()
10644 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { in tg3_set_pauseparam()
10647 if (oldadv != newadv) { in tg3_set_pauseparam()
10652 if (phydev->autoneg) { in tg3_set_pauseparam()
10656 * flow control settings, even if the in tg3_set_pauseparam()
10665 if (!epause->autoneg) in tg3_set_pauseparam()
10676 if (netif_running(dev)) { in tg3_set_pauseparam()
10683 if (epause->autoneg) in tg3_set_pauseparam()
10687 if (epause->rx_pause) in tg3_set_pauseparam()
10691 if (epause->tx_pause) in tg3_set_pauseparam()
10696 if (netif_running(dev)) { in tg3_set_pauseparam()
10699 if (!err) in tg3_set_pauseparam()
10726 if (!tg3_flag(tp, SUPPORT_MSIX)) in tg3_get_rxnfc()
10731 if (netif_running(tp->dev)) in tg3_get_rxnfc()
10735 if (info->data > TG3_IRQ_MAX_VECS_RSS) in tg3_get_rxnfc()
10755 if (tg3_flag(tp, SUPPORT_MSIX)) in tg3_get_rxfh_indir_size()
10780 if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS)) in tg3_set_rxfh_indir()
10813 if (!netif_running(tp->dev)) in tg3_set_phys_id()
10858 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic)) in tg3_vpd_readblock()
10861 if (magic == TG3_EEPROM_MAGIC) { in tg3_vpd_readblock()
10865 if (tg3_nvram_read(tp, offset, &val)) in tg3_vpd_readblock()
10868 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == in tg3_vpd_readblock()
10873 if (offset != TG3_NVM_DIR_END) { in tg3_vpd_readblock()
10875 if (tg3_nvram_read(tp, offset + 4, &offset)) in tg3_vpd_readblock()
10882 if (!offset || !len) { in tg3_vpd_readblock()
10888 if (buf == NULL) in tg3_vpd_readblock()
10891 if (magic == TG3_EEPROM_MAGIC) { in tg3_vpd_readblock()
10897 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4])) in tg3_vpd_readblock()
10909 if (cnt == -ETIMEDOUT || cnt == -EINTR) in tg3_vpd_readblock()
10911 else if (cnt < 0) in tg3_vpd_readblock()
10914 if (pos != len) in tg3_vpd_readblock()
10943 if (tg3_flag(tp, NO_NVRAM)) in tg3_test_nvram()
10946 if (tg3_nvram_read(tp, 0, &magic) != 0) in tg3_test_nvram()
10949 if (magic == TG3_EEPROM_MAGIC) in tg3_test_nvram()
10951 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) { in tg3_test_nvram()
10952 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) == in tg3_test_nvram()
10978 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW) in tg3_test_nvram()
10984 if (buf == NULL) in tg3_test_nvram()
10990 if (err) in tg3_test_nvram()
10993 if (i < size) in tg3_test_nvram()
10998 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == in tg3_test_nvram()
11002 if ((magic & TG3_EEPROM_SB_REVISION_MASK) == in tg3_test_nvram()
11014 if (csum8 == 0) { in tg3_test_nvram()
11023 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == in tg3_test_nvram()
11031 if ((i == 0) || (i == 8)) { in tg3_test_nvram()
11038 } else if (i == 16) { in tg3_test_nvram()
11057 if ((hw8 & 0x1) && parity[i]) in tg3_test_nvram()
11059 else if (!(hw8 & 0x1) && !parity[i]) in tg3_test_nvram()
11070 if (csum != le32_to_cpu(buf[0x10/4])) in tg3_test_nvram()
11075 if (csum != le32_to_cpu(buf[0xfc/4])) in tg3_test_nvram()
11081 if (!buf) in tg3_test_nvram()
11085 if (i > 0) { in tg3_test_nvram()
11087 if (j < 0) in tg3_test_nvram()
11090 if (i + PCI_VPD_LRDT_TAG_SIZE + j > len) in tg3_test_nvram()
11096 if (j > 0) { in tg3_test_nvram()
11104 if (csum8) in tg3_test_nvram()
11123 if (!netif_running(tp->dev)) in tg3_test_link()
11126 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_test_link()
11132 if (netif_carrier_ok(tp->dev)) in tg3_test_link()
11135 if (msleep_interruptible(1000)) in tg3_test_link()
11293 if (tg3_flag(tp, 5705_PLUS)) { in tg3_test_registers()
11295 if (tg3_flag(tp, 5750_PLUS)) in tg3_test_registers()
11300 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705)) in tg3_test_registers()
11303 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705)) in tg3_test_registers()
11306 if (tg3_flag(tp, IS_5788) && in tg3_test_registers()
11310 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750)) in tg3_test_registers()
11331 if (((val & read_mask) != read_val) || (val & write_mask)) in tg3_test_registers()
11343 if ((val & read_mask) != read_val) in tg3_test_registers()
11347 if ((val & write_mask) != write_mask) in tg3_test_registers()
11356 if (netif_msg_hw(tp)) in tg3_test_registers()
11375 if (val != test_pattern[i]) in tg3_do_mem_test()
11429 if (tg3_flag(tp, 5717_PLUS)) in tg3_test_memory()
11431 else if (tg3_flag(tp, 57765_CLASS)) in tg3_test_memory()
11433 else if (tg3_flag(tp, 5755_PLUS)) in tg3_test_memory()
11435 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) in tg3_test_memory()
11437 else if (tg3_flag(tp, 5705_PLUS)) in tg3_test_memory()
11444 if (err) in tg3_test_memory()
11489 if (tp->irq_cnt > 1) { in tg3_run_loopback()
11490 if (tg3_flag(tp, ENABLE_RSS)) in tg3_run_loopback()
11492 if (tg3_flag(tp, ENABLE_TSS)) in tg3_run_loopback()
11501 if (!skb) in tg3_run_loopback()
11510 if (tso_loopback) { in tg3_run_loopback()
11529 if (tg3_flag(tp, HW_TSO_1) || in tg3_run_loopback()
11539 if (tg3_flag(tp, HW_TSO_3)) { in tg3_run_loopback()
11541 if (hdr_len & 0x10) in tg3_run_loopback()
11544 } else if (tg3_flag(tp, HW_TSO_2)) in tg3_run_loopback()
11546 else if (tg3_flag(tp, HW_TSO_1) || in tg3_run_loopback()
11563 if (pci_dma_mapping_error(tp->pdev, map)) { in tg3_run_loopback()
11580 if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len, in tg3_run_loopback()
11603 if ((tx_idx == tnapi->tx_prod) && in tg3_run_loopback()
11611 if (tx_idx != tnapi->tx_prod) in tg3_run_loopback()
11614 if (rx_idx != rx_start_idx + num_pkts) in tg3_run_loopback()
11623 if ((desc->err_vlan & RXD_ERR_MASK) != 0 && in tg3_run_loopback()
11630 if (!tso_loopback) { in tg3_run_loopback()
11631 if (rx_len != tx_len) in tg3_run_loopback()
11634 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) { in tg3_run_loopback()
11635 if (opaque_key != RXD_OPAQUE_RING_STD) in tg3_run_loopback()
11638 if (opaque_key != RXD_OPAQUE_RING_JUMBO) in tg3_run_loopback()
11641 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) && in tg3_run_loopback()
11647 if (opaque_key == RXD_OPAQUE_RING_STD) { in tg3_run_loopback()
11651 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) { in tg3_run_loopback()
11663 if (*(rx_data + i) != (u8) (val & 0xff)) in tg3_run_loopback()
11691 if (!netif_running(tp->dev)) { in tg3_test_loopback()
11694 if (do_extlpbk) in tg3_test_loopback()
11700 if (err) { in tg3_test_loopback()
11703 if (do_extlpbk) in tg3_test_loopback()
11708 if (tg3_flag(tp, ENABLE_RSS)) { in tg3_test_loopback()
11722 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 && in tg3_test_loopback()
11726 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false)) in tg3_test_loopback()
11729 if (tg3_flag(tp, JUMBO_RING_ENABLE) && in tg3_test_loopback()
11736 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_test_loopback()
11744 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) in tg3_test_loopback()
11749 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false)) in tg3_test_loopback()
11751 if (tg3_flag(tp, TSO_CAPABLE) && in tg3_test_loopback()
11754 if (tg3_flag(tp, JUMBO_RING_ENABLE) && in tg3_test_loopback()
11758 if (do_extlpbk) { in tg3_test_loopback()
11767 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false)) in tg3_test_loopback()
11769 if (tg3_flag(tp, TSO_CAPABLE) && in tg3_test_loopback()
11772 if (tg3_flag(tp, JUMBO_RING_ENABLE) && in tg3_test_loopback()
11778 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) in tg3_test_loopback()
11796 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) && in tg3_self_test()
11805 if (tg3_test_nvram(tp) != 0) { in tg3_self_test()
11809 if (!doextlpbk && tg3_test_link(tp)) { in tg3_self_test()
11813 if (etest->flags & ETH_TEST_FL_OFFLINE) { in tg3_self_test()
11816 if (netif_running(dev)) { in tg3_self_test()
11827 if (!tg3_flag(tp, 5705_PLUS)) in tg3_self_test()
11829 if (!err) in tg3_self_test()
11832 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_self_test()
11835 if (tg3_test_registers(tp) != 0) { in tg3_self_test()
11840 if (tg3_test_memory(tp) != 0) { in tg3_self_test()
11845 if (doextlpbk) in tg3_self_test()
11848 if (tg3_test_loopback(tp, &data[4], doextlpbk)) in tg3_self_test()
11853 if (tg3_test_interrupt(tp) != 0) { in tg3_self_test()
11861 if (netif_running(dev)) { in tg3_self_test()
11864 if (!err2) in tg3_self_test()
11870 if (irq_sync && !err2) in tg3_self_test()
11873 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) in tg3_self_test()
11884 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_ioctl()
11886 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_ioctl()
11900 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_ioctl()
11903 if (!netif_running(dev)) in tg3_ioctl()
11916 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_ioctl()
11919 if (!netif_running(dev)) in tg3_ioctl()
11949 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_set_coalesce()
11956 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) || in tg3_set_coalesce()
11968 /* No rx interrupts will be generated if both are zero */ in tg3_set_coalesce()
11969 if ((ec->rx_coalesce_usecs == 0) && in tg3_set_coalesce()
11973 /* No tx interrupts will be generated if both are zero */ in tg3_set_coalesce()
11974 if ((ec->tx_coalesce_usecs == 0) && in tg3_set_coalesce()
11989 if (netif_running(dev)) { in tg3_set_coalesce()
12035 if (tg3_nvram_read(tp, 0, &magic) != 0) in tg3_get_eeprom_size()
12038 if ((magic != TG3_EEPROM_MAGIC) && in tg3_get_eeprom_size()
12051 if (tg3_nvram_read(tp, cursize, &val) != 0) in tg3_get_eeprom_size()
12054 if (val == magic) in tg3_get_eeprom_size()
12067 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0) in tg3_get_nvram_size()
12071 if (val != TG3_EEPROM_MAGIC) { in tg3_get_nvram_size()
12076 if (tg3_nvram_read(tp, 0xf0, &val) == 0) { in tg3_get_nvram_size()
12077 if (val != 0) { in tg3_get_nvram_size()
12101 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) { in tg3_get_nvram_info()
12108 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || in tg3_get_nvram_info()
12181 if (nvcfg1 & (1 << 27)) in tg3_get_5752_nvram_info()
12204 if (tg3_flag(tp, FLASH)) { in tg3_get_5752_nvram_info()
12222 if (nvcfg1 & (1 << 27)) { in tg3_get_5755_nvram_info()
12237 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 || in tg3_get_5755_nvram_info()
12241 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2) in tg3_get_5755_nvram_info()
12255 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10) in tg3_get_5755_nvram_info()
12259 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20) in tg3_get_5755_nvram_info()
12316 if (nvcfg1 & (1 << 27)) { in tg3_get_5761_nvram_info()
12352 if (protect) { in tg3_get_5761_nvram_info()
12459 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) in tg3_get_57780_nvram_info()
12538 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) in tg3_get_5717_nvram_info()
12557 if (nvmpinstrp == FLASH_5720_EEPROM_HD) in tg3_get_5720_nvram_info()
12650 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) in tg3_get_5720_nvram_info()
12669 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && in tg3_nvram_init()
12673 if (tg3_nvram_lock(tp)) { in tg3_nvram_init()
12683 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) in tg3_nvram_init()
12685 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) in tg3_nvram_init()
12687 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || in tg3_nvram_init()
12691 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) in tg3_nvram_init()
12693 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) in tg3_nvram_init()
12695 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || in tg3_nvram_init()
12698 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || in tg3_nvram_init()
12701 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) in tg3_nvram_init()
12706 if (tp->nvram_size == 0) in tg3_nvram_init()
12756 if (val & EEPROM_ADDR_COMPLETE) in tg3_nvram_write_block_using_eeprom()
12760 if (!(val & EEPROM_ADDR_COMPLETE)) { in tg3_nvram_write_block_using_eeprom()
12780 if (tmp == NULL) in tg3_nvram_write_block_unbuffered()
12792 if (ret) in tg3_nvram_write_block_unbuffered()
12795 if (ret) in tg3_nvram_write_block_unbuffered()
12800 if (len < size) in tg3_nvram_write_block_unbuffered()
12817 if (tg3_nvram_exec_cmd(tp, nvram_cmd)) in tg3_nvram_write_block_unbuffered()
12826 if (tg3_nvram_exec_cmd(tp, nvram_cmd)) in tg3_nvram_write_block_unbuffered()
12832 if (tg3_nvram_exec_cmd(tp, nvram_cmd)) in tg3_nvram_write_block_unbuffered()
12847 if (j == 0) in tg3_nvram_write_block_unbuffered()
12849 else if (j == (pagesize - 4)) in tg3_nvram_write_block_unbuffered()
12852 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd))) in tg3_nvram_write_block_unbuffered()
12855 if (ret) in tg3_nvram_write_block_unbuffered()
12888 if (page_off == 0 || i == 0) in tg3_nvram_write_block_buffered()
12890 if (page_off == (tp->nvram_pagesize - 4)) in tg3_nvram_write_block_buffered()
12893 if (i == (len - 4)) in tg3_nvram_write_block_buffered()
12896 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 && in tg3_nvram_write_block_buffered()
12901 if ((ret = tg3_nvram_exec_cmd(tp, in tg3_nvram_write_block_buffered()
12907 if (!tg3_flag(tp, FLASH)) { in tg3_nvram_write_block_buffered()
12912 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd))) in tg3_nvram_write_block_buffered()
12923 if (tg3_flag(tp, EEPROM_WRITE_PROT)) { in tg3_nvram_write_block()
12929 if (!tg3_flag(tp, NVRAM)) { in tg3_nvram_write_block()
12935 if (ret) in tg3_nvram_write_block()
12939 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) in tg3_nvram_write_block()
12945 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) { in tg3_nvram_write_block()
12960 if (tg3_flag(tp, EEPROM_WRITE_PROT)) { in tg3_nvram_write_block()
13042 if ((subsys_id_to_phy_id[i].subsys_vendor == in tg3_lookup_by_subsys()
13062 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { in tg3_get_eeprom_hw_cfg()
13063 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) { in tg3_get_eeprom_hw_cfg()
13068 if (val & VCPU_CFGSHDW_ASPM_DBNC) in tg3_get_eeprom_hw_cfg()
13070 if ((val & VCPU_CFGSHDW_WOL_ENABLE) && in tg3_get_eeprom_hw_cfg()
13079 if (val == NIC_SRAM_DATA_SIG_MAGIC) { in tg3_get_eeprom_hw_cfg()
13089 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && in tg3_get_eeprom_hw_cfg()
13095 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) in tg3_get_eeprom_hw_cfg()
13098 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) == in tg3_get_eeprom_hw_cfg()
13103 if (nic_phy_id != 0) { in tg3_get_eeprom_hw_cfg()
13114 if (eeprom_phy_serdes) { in tg3_get_eeprom_hw_cfg()
13115 if (!tg3_flag(tp, 5705_PLUS)) in tg3_get_eeprom_hw_cfg()
13121 if (tg3_flag(tp, 5750_PLUS)) in tg3_get_eeprom_hw_cfg()
13140 /* Default to PHY_1_MODE if 0 (MAC_MODE) is in tg3_get_eeprom_hw_cfg()
13143 if (GET_ASIC_REV(tp->pci_chip_rev_id) == in tg3_get_eeprom_hw_cfg()
13153 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 && in tg3_get_eeprom_hw_cfg()
13165 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) in tg3_get_eeprom_hw_cfg()
13172 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || in tg3_get_eeprom_hw_cfg()
13177 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) in tg3_get_eeprom_hw_cfg()
13180 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) { in tg3_get_eeprom_hw_cfg()
13182 if ((tp->pdev->subsystem_vendor == in tg3_get_eeprom_hw_cfg()
13192 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { in tg3_get_eeprom_hw_cfg()
13194 if (tg3_flag(tp, 5750_PLUS)) in tg3_get_eeprom_hw_cfg()
13198 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) && in tg3_get_eeprom_hw_cfg()
13202 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES && in tg3_get_eeprom_hw_cfg()
13206 if (tg3_flag(tp, WOL_CAP) && in tg3_get_eeprom_hw_cfg()
13212 if (cfg2 & (1 << 17)) in tg3_get_eeprom_hw_cfg()
13216 /* bootcode if bit 18 is set */ in tg3_get_eeprom_hw_cfg()
13217 if (cfg2 & (1 << 18)) in tg3_get_eeprom_hw_cfg()
13220 if ((tg3_flag(tp, 57765_PLUS) || in tg3_get_eeprom_hw_cfg()
13226 if (tg3_flag(tp, PCI_EXPRESS) && in tg3_get_eeprom_hw_cfg()
13232 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE) in tg3_get_eeprom_hw_cfg()
13236 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE) in tg3_get_eeprom_hw_cfg()
13238 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN) in tg3_get_eeprom_hw_cfg()
13240 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN) in tg3_get_eeprom_hw_cfg()
13244 if (tg3_flag(tp, WOL_CAP)) in tg3_get_eeprom_hw_cfg()
13262 if (val & OTP_STATUS_CMD_DONE) in tg3_issue_otp_command()
13280 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT)) in tg3_read_otp_phycfg()
13285 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) in tg3_read_otp_phycfg()
13292 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) in tg3_read_otp_phycfg()
13304 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) in tg3_phy_init_link_config()
13308 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_phy_init_link_config()
13338 if (tg3_flag(tp, USE_PHYLIB)) in tg3_phy_probe()
13345 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) { in tg3_phy_probe()
13349 * that it is sane. If it doesn't look good, we fall back in tg3_phy_probe()
13363 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) { in tg3_phy_probe()
13365 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002) in tg3_phy_probe()
13370 if (tp->phy_id != TG3_PHY_ID_INVALID) { in tg3_phy_probe()
13381 if (!p) in tg3_phy_probe()
13385 if (!tp->phy_id || in tg3_phy_probe()
13391 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && in tg3_phy_probe()
13402 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && in tg3_phy_probe()
13408 if (!tg3_readphy(tp, MII_BMSR, &bmsr) && in tg3_phy_probe()
13413 if (err) in tg3_phy_probe()
13418 if (!tg3_phy_copper_an_config_ok(tp, &dummy)) { in tg3_phy_probe()
13428 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_phy_probe()
13430 if (err) in tg3_phy_probe()
13447 if (!vpd_data) in tg3_read_vpd()
13451 if (i < 0) in tg3_read_vpd()
13458 if (block_end > vpdlen) in tg3_read_vpd()
13463 if (j > 0) { in tg3_read_vpd()
13467 if (j + len > block_end || len != 4 || in tg3_read_vpd()
13473 if (j < 0) in tg3_read_vpd()
13479 if (j + len > block_end) in tg3_read_vpd()
13489 if (i < 0) in tg3_read_vpd()
13495 if (len > TG3_BPN_SIZE || in tg3_read_vpd()
13503 if (tp->board_part_number[0]) in tg3_read_vpd()
13507 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) { in tg3_read_vpd()
13508 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717) in tg3_read_vpd()
13510 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718) in tg3_read_vpd()
13514 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { in tg3_read_vpd()
13515 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780) in tg3_read_vpd()
13517 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760) in tg3_read_vpd()
13519 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790) in tg3_read_vpd()
13521 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788) in tg3_read_vpd()
13525 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) { in tg3_read_vpd()
13526 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761) in tg3_read_vpd()
13528 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765) in tg3_read_vpd()
13530 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781) in tg3_read_vpd()
13532 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785) in tg3_read_vpd()
13534 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791) in tg3_read_vpd()
13536 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795) in tg3_read_vpd()
13540 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766) { in tg3_read_vpd()
13541 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762) in tg3_read_vpd()
13543 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766) in tg3_read_vpd()
13545 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782) in tg3_read_vpd()
13547 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786) in tg3_read_vpd()
13551 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { in tg3_read_vpd()
13563 if (tg3_nvram_read(tp, offset, &val) || in tg3_fw_img_is_valid()
13578 if (tg3_nvram_read(tp, 0xc, &offset) || in tg3_read_bc_ver()
13584 if (tg3_nvram_read(tp, offset, &val)) in tg3_read_bc_ver()
13587 if ((val & 0xfc000000) == 0x0c000000) { in tg3_read_bc_ver()
13588 if (tg3_nvram_read(tp, offset + 4, &val)) in tg3_read_bc_ver()
13591 if (val == 0) in tg3_read_bc_ver()
13597 if (newver) { in tg3_read_bc_ver()
13598 if (TG3_VER_SIZE - dst_off < 16 || in tg3_read_bc_ver()
13605 if (tg3_nvram_read_be32(tp, offset + i, &v)) in tg3_read_bc_ver()
13613 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset)) in tg3_read_bc_ver()
13629 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val)) in tg3_read_hwsb_ver()
13646 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1) in tg3_read_sb_ver()
13672 if (tg3_nvram_read(tp, offset, &val)) in tg3_read_sb_ver()
13681 if (minor > 99 || build > 26) in tg3_read_sb_ver()
13688 if (build > 0) { in tg3_read_sb_ver()
13690 if (offset < TG3_VER_SIZE - 1) in tg3_read_sb_ver()
13703 if (tg3_nvram_read(tp, offset, &val)) in tg3_read_mgmtfw_ver()
13706 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI) in tg3_read_mgmtfw_ver()
13710 if (offset == TG3_NVM_DIR_END) in tg3_read_mgmtfw_ver()
13713 if (!tg3_flag(tp, 5705_PLUS)) in tg3_read_mgmtfw_ver()
13715 else if (tg3_nvram_read(tp, offset - 4, &start)) in tg3_read_mgmtfw_ver()
13718 if (tg3_nvram_read(tp, offset + 4, &offset) || in tg3_read_mgmtfw_ver()
13732 if (tg3_nvram_read_be32(tp, offset, &v)) in tg3_read_mgmtfw_ver()
13737 if (vlen > TG3_VER_SIZE - sizeof(v)) { in tg3_read_mgmtfw_ver()
13753 if (!tg3_flag(tp, ENABLE_APE) || !tg3_flag(tp, ENABLE_ASF)) in tg3_read_dash_ver()
13757 if (apedata != APE_SEG_SIG_MAGIC) in tg3_read_dash_ver()
13761 if (!(apedata & APE_FW_STATUS_READY)) in tg3_read_dash_ver()
13766 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) { in tg3_read_dash_ver()
13788 if (tp->fw_ver[0] != 0) in tg3_read_fw_ver()
13791 if (tg3_flag(tp, NO_NVRAM)) { in tg3_read_fw_ver()
13796 if (tg3_nvram_read(tp, 0, &val)) in tg3_read_fw_ver()
13799 if (val == TG3_EEPROM_MAGIC) in tg3_read_fw_ver()
13801 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) in tg3_read_fw_ver()
13803 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW) in tg3_read_fw_ver()
13808 if (vpd_vers) in tg3_read_fw_ver()
13811 if (tg3_flag(tp, ENABLE_APE)) { in tg3_read_fw_ver()
13812 if (tg3_flag(tp, ENABLE_ASF)) in tg3_read_fw_ver()
13814 } else if (tg3_flag(tp, ENABLE_ASF)) { in tg3_read_fw_ver()
13826 if (tg3_flag(tp, LRG_PROD_RING_CAP)) in tg3_rx_ret_ring_size()
13828 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) in tg3_rx_ret_ring_size()
13849 /* Force memory write invalidate off. If we leave it on, in tg3_get_invariants()
13874 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) { in tg3_get_invariants()
13877 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || in tg3_get_invariants()
13884 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 || in tg3_get_invariants()
13907 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW) in tg3_get_invariants()
13910 /* If we have 5702/03 A1 or A2 on certain ICH chipsets, in tg3_get_invariants()
13924 * enable this workaround if the 5703 is on the secondary in tg3_get_invariants()
13927 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) || in tg3_get_invariants()
13950 if (!bridge) { in tg3_get_invariants()
13954 if (pci_id->rev != PCI_ANY_ID) { in tg3_get_invariants()
13955 if (bridge->revision > pci_id->rev) in tg3_get_invariants()
13958 if (bridge->subordinate && in tg3_get_invariants()
13968 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { in tg3_get_invariants()
13984 if (!bridge) { in tg3_get_invariants()
13988 if (bridge->subordinate && in tg3_get_invariants()
14006 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 || in tg3_get_invariants()
14018 if (bridge && bridge->subordinate && in tg3_get_invariants()
14030 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || in tg3_get_invariants()
14034 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || in tg3_get_invariants()
14039 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 || in tg3_get_invariants()
14043 if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS)) in tg3_get_invariants()
14047 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || in tg3_get_invariants()
14056 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || in tg3_get_invariants()
14063 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 || in tg3_get_invariants()
14068 if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0) in tg3_get_invariants()
14070 else if (tg3_flag(tp, 57765_PLUS)) in tg3_get_invariants()
14072 else if (tg3_flag(tp, 5755_PLUS) || in tg3_get_invariants()
14075 else if (tg3_flag(tp, 5750_PLUS)) { in tg3_get_invariants()
14078 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 && in tg3_get_invariants()
14081 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && in tg3_get_invariants()
14085 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) in tg3_get_invariants()
14092 if (tg3_flag(tp, HW_TSO_1) || in tg3_get_invariants()
14097 * We'll disable TSO later if we discover ASF in tg3_get_invariants()
14107 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) in tg3_get_invariants()
14112 if (tg3_flag(tp, 5750_PLUS)) { in tg3_get_invariants()
14114 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX || in tg3_get_invariants()
14121 if (tg3_flag(tp, 5755_PLUS) || in tg3_get_invariants()
14126 if (tg3_flag(tp, 57765_PLUS)) { in tg3_get_invariants()
14133 if (tg3_flag(tp, 5755_PLUS)) in tg3_get_invariants()
14136 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) in tg3_get_invariants()
14138 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766) in tg3_get_invariants()
14141 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || in tg3_get_invariants()
14146 if (tg3_flag(tp, 57765_PLUS) && in tg3_get_invariants()
14150 if (!tg3_flag(tp, 5705_PLUS) || in tg3_get_invariants()
14158 if (pci_is_pcie(tp->pdev)) { in tg3_get_invariants()
14163 if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0) { in tg3_get_invariants()
14165 if (readrq > 2048) in tg3_get_invariants()
14172 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) { in tg3_get_invariants()
14173 if (GET_ASIC_REV(tp->pci_chip_rev_id) == in tg3_get_invariants()
14178 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || in tg3_get_invariants()
14183 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) { in tg3_get_invariants()
14186 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { in tg3_get_invariants()
14192 } else if (!tg3_flag(tp, 5705_PLUS) || in tg3_get_invariants()
14195 if (!tp->pcix_cap) { in tg3_get_invariants()
14201 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE)) in tg3_get_invariants()
14205 /* If we have an AMD 762 or VIA K8T800 chipset, write in tg3_get_invariants()
14211 if (pci_dev_present(tg3_write_reorder_chipsets) && in tg3_get_invariants()
14219 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && in tg3_get_invariants()
14229 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) { in tg3_get_invariants()
14235 /* If we are in PCI-X mode, enable register write workaround. in tg3_get_invariants()
14240 if (tg3_flag(tp, PCIX_MODE)) { in tg3_get_invariants()
14265 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0) in tg3_get_invariants()
14267 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0) in tg3_get_invariants()
14271 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) && in tg3_get_invariants()
14286 if (tg3_flag(tp, PCIX_TARGET_HWBUG)) in tg3_get_invariants()
14288 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 || in tg3_get_invariants()
14301 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) { in tg3_get_invariants()
14303 if (tg3_flag(tp, MBOX_WRITE_REORDER)) in tg3_get_invariants()
14307 if (tg3_flag(tp, ICH_WORKAROUND)) { in tg3_get_invariants()
14322 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { in tg3_get_invariants()
14329 if (tp->write32 == tg3_write_indirect_reg32 || in tg3_get_invariants()
14344 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || in tg3_get_invariants()
14346 if (tg3_flag(tp, PCIX_MODE)) { in tg3_get_invariants()
14352 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) { in tg3_get_invariants()
14354 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) == in tg3_get_invariants()
14359 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || in tg3_get_invariants()
14362 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) == in tg3_get_invariants()
14379 if (tp->fw_needed && tg3_flag(tp, ENABLE_ASF)) { in tg3_get_invariants()
14385 if (tg3_flag(tp, ENABLE_APE)) { in tg3_get_invariants()
14398 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || in tg3_get_invariants()
14411 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || in tg3_get_invariants()
14418 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) in tg3_get_invariants()
14421 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || in tg3_get_invariants()
14426 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || in tg3_get_invariants()
14430 if (tg3_flag(tp, IS_NIC)) in tg3_get_invariants()
14436 /* Switch out of Vaux if it is a NIC */ in tg3_get_invariants()
14442 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS)) in tg3_get_invariants()
14446 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || in tg3_get_invariants()
14455 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) in tg3_get_invariants()
14459 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || in tg3_get_invariants()
14467 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX || in tg3_get_invariants()
14470 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) in tg3_get_invariants()
14473 if (tg3_flag(tp, 5705_PLUS) && in tg3_get_invariants()
14478 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || in tg3_get_invariants()
14482 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 && in tg3_get_invariants()
14485 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M) in tg3_get_invariants()
14491 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && in tg3_get_invariants()
14494 if (tp->phy_otp == 0) in tg3_get_invariants()
14498 if (tg3_flag(tp, CPMU_PRESENT)) in tg3_get_invariants()
14504 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX && in tg3_get_invariants()
14509 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || in tg3_get_invariants()
14516 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || in tg3_get_invariants()
14521 if (err) in tg3_get_invariants()
14526 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) in tg3_get_invariants()
14544 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 && in tg3_get_invariants()
14548 if (chiprevid == CHIPREV_ID_5701_A0 || in tg3_get_invariants()
14555 * area, see if it reads back correctly. If the return in tg3_get_invariants()
14563 if (readl(sram_base) != 0x00000000) in tg3_get_invariants()
14574 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && in tg3_get_invariants()
14579 if (!tg3_flag(tp, IS_5788) && in tg3_get_invariants()
14582 if (tg3_flag(tp, TAGGED_STATUS)) { in tg3_get_invariants()
14592 if (tg3_flag(tp, ENABLE_APE)) in tg3_get_invariants()
14598 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && in tg3_get_invariants()
14616 if (err) { in tg3_get_invariants()
14625 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_get_invariants()
14628 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) in tg3_get_invariants()
14638 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) in tg3_get_invariants()
14647 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL && in tg3_get_invariants()
14655 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_get_invariants()
14662 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 && in tg3_get_invariants()
14679 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || in tg3_get_invariants()
14684 if (tg3_flag(tp, ASPM_WORKAROUND)) in tg3_get_invariants()
14701 if (addr && len == 6) { in tg3_get_macaddr_sparc()
14726 if (!tg3_get_macaddr_sparc(tp)) in tg3_get_device_address()
14731 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || in tg3_get_device_address()
14733 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) in tg3_get_device_address()
14735 if (tg3_nvram_lock(tp)) in tg3_get_device_address()
14739 } else if (tg3_flag(tp, 5717_PLUS)) { in tg3_get_device_address()
14740 if (tp->pci_fn & 1) in tg3_get_device_address()
14742 if (tp->pci_fn > 1) in tg3_get_device_address()
14744 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) in tg3_get_device_address()
14749 if ((hi >> 16) == 0x484b) { in tg3_get_device_address()
14762 if (!addr_ok) { in tg3_get_device_address()
14764 if (!tg3_flag(tp, NO_NVRAM) && in tg3_get_device_address()
14784 if (!is_valid_ether_addr(&dev->dev_addr[0])) { in tg3_get_device_address()
14786 if (!tg3_get_default_macaddr_sparc(tp)) in tg3_get_device_address()
14805 if (byte == 0) in tg3_calc_dma_bndry()
14813 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && in tg3_calc_dma_bndry()
14818 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC) in tg3_calc_dma_bndry()
14821 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA) in tg3_calc_dma_bndry()
14828 if (tg3_flag(tp, 57765_PLUS)) { in tg3_calc_dma_bndry()
14833 if (!goal) in tg3_calc_dma_bndry()
14847 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) { in tg3_calc_dma_bndry()
14853 if (goal == BOUNDARY_SINGLE_CACHELINE) { in tg3_calc_dma_bndry()
14872 } else if (tg3_flag(tp, PCI_EXPRESS)) { in tg3_calc_dma_bndry()
14877 if (goal == BOUNDARY_SINGLE_CACHELINE) { in tg3_calc_dma_bndry()
14892 if (goal == BOUNDARY_SINGLE_CACHELINE) { in tg3_calc_dma_bndry()
14899 if (goal == BOUNDARY_SINGLE_CACHELINE) { in tg3_calc_dma_bndry()
14906 if (goal == BOUNDARY_SINGLE_CACHELINE) { in tg3_calc_dma_bndry()
14913 if (goal == BOUNDARY_SINGLE_CACHELINE) { in tg3_calc_dma_bndry()
14972 if (to_device) { in tg3_do_test_dma()
14995 if (to_device) in tg3_do_test_dma()
15004 if (to_device) in tg3_do_test_dma()
15008 if ((val & 0xffff) == sram_dma_descs) { in tg3_do_test_dma()
15034 if (!buf) { in tg3_test_dma()
15044 if (tg3_flag(tp, 57765_PLUS)) in tg3_test_dma()
15047 if (tg3_flag(tp, PCI_EXPRESS)) { in tg3_test_dma()
15050 } else if (!tg3_flag(tp, PCIX_MODE)) { in tg3_test_dma()
15051 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 || in tg3_test_dma()
15057 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || in tg3_test_dma()
15062 /* If the 5704 is behind the EPB bridge, we can in tg3_test_dma()
15066 if (tg3_flag(tp, 40BIT_DMA_BUG) && in tg3_test_dma()
15069 else if (ccval == 0x6 || ccval == 0x7) in tg3_test_dma()
15072 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) in tg3_test_dma()
15079 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) { in tg3_test_dma()
15082 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { in tg3_test_dma()
15090 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || in tg3_test_dma()
15094 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || in tg3_test_dma()
15096 /* Remove this if it causes problems for some boards. */ in tg3_test_dma()
15114 #if 0 in tg3_test_dma()
15119 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && in tg3_test_dma()
15138 if (ret) { in tg3_test_dma()
15145 #if 0 in tg3_test_dma()
15150 if (le32_to_cpu(val) != p[i]) { in tg3_test_dma()
15161 if (ret) { in tg3_test_dma()
15169 if (p[i] == i) in tg3_test_dma()
15172 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != in tg3_test_dma()
15187 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) { in tg3_test_dma()
15193 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != in tg3_test_dma()
15199 if (pci_dev_present(tg3_dma_wait_state_chipsets)) { in tg3_test_dma()
15218 if (tg3_flag(tp, 57765_PLUS)) { in tg3_init_bufmgr_config()
15232 } else if (tg3_flag(tp, 5705_PLUS)) { in tg3_init_bufmgr_config()
15239 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { in tg3_init_bufmgr_config()
15305 if (tg3_flag(tp, PCI_EXPRESS)) { in tg3_bus_string()
15308 } else if (tg3_flag(tp, PCIX_MODE)) { in tg3_bus_string()
15313 if ((clock_ctrl == 7) || in tg3_bus_string()
15317 else if (clock_ctrl == 0) in tg3_bus_string()
15319 else if (clock_ctrl == 2) in tg3_bus_string()
15321 else if (clock_ctrl == 4) in tg3_bus_string()
15323 else if (clock_ctrl == 6) in tg3_bus_string()
15327 if (tg3_flag(tp, PCI_HIGH_SPEED)) in tg3_bus_string()
15332 if (tg3_flag(tp, PCI_32BIT)) in tg3_bus_string()
15346 if (peer && peer != tp->pdev) in tg3_find_peer()
15353 if (!peer) { in tg3_find_peer()
15383 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD | in tg3_init_coal()
15391 if (tg3_flag(tp, 5705_PLUS)) { in tg3_init_coal()
15403 if (!tp->hw_stats) in tg3_get_stats64()
15445 if (err) { in tg3_init_one()
15451 if (err) { in tg3_init_one()
15460 if (pm_cap == 0) { in tg3_init_one()
15468 if (err) { in tg3_init_one()
15474 if (!dev) { in tg3_init_one()
15489 if (tg3_debug > 0) in tg3_init_one()
15520 if (!tp->regs) { in tg3_init_one()
15526 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || in tg3_init_one()
15536 if (!tp->aperegs) { in tg3_init_one()
15553 if (err) { in tg3_init_one()
15565 if (tg3_flag(tp, IS_5788)) in tg3_init_one()
15567 else if (tg3_flag(tp, 40BIT_DMA_BUG)) { in tg3_init_one()
15576 if (dma_mask > DMA_BIT_MASK(32)) { in tg3_init_one()
15578 if (!err) { in tg3_init_one()
15582 if (err < 0) { in tg3_init_one()
15589 if (err || dma_mask == DMA_BIT_MASK(32)) { in tg3_init_one()
15591 if (err) { in tg3_init_one()
15605 if (tp->pci_chip_rev_id != CHIPREV_ID_5700_B0) { in tg3_init_one()
15608 if (tg3_flag(tp, 5755_PLUS)) in tg3_init_one()
15616 if ((tg3_flag(tp, HW_TSO_1) || in tg3_init_one()
15621 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) { in tg3_init_one()
15622 if (features & NETIF_F_IPV6_CSUM) in tg3_init_one()
15624 if (tg3_flag(tp, HW_TSO_3) || in tg3_init_one()
15641 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 && in tg3_init_one()
15648 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 && in tg3_init_one()
15656 if (err) { in tg3_init_one()
15667 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) || in tg3_init_one()
15674 if (err) { in tg3_init_one()
15689 if (i <= 4) in tg3_init_one()
15697 if (i) in tg3_init_one()
15702 if (!tg3_flag(tp, SUPPORT_MSIX)) in tg3_init_one()
15706 * If we support MSIX, we'll be using RSS. If we're using in tg3_init_one()
15712 if (!i) in tg3_init_one()
15717 if (sndmbx & 0x4) in tg3_init_one()
15727 if (tg3_flag(tp, 5717_PLUS)) { in tg3_init_one()
15733 if (err) { in tg3_init_one()
15744 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { in tg3_init_one()
15753 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) in tg3_init_one()
15755 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_init_one()
15783 if (tp->aperegs) { in tg3_init_one()
15789 if (tp->regs) { in tg3_init_one()
15813 if (dev) { in tg3_remove_one()
15816 if (tp->fw) in tg3_remove_one()
15821 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_remove_one()
15827 if (tp->aperegs) { in tg3_remove_one()
15831 if (tp->regs) { in tg3_remove_one()
15850 if (!netif_running(dev)) in tg3_suspend()
15871 if (err) { in tg3_suspend()
15878 if (err2) in tg3_suspend()
15890 if (!err2) in tg3_suspend()
15904 if (!netif_running(dev)) in tg3_resume()
15913 if (err) in tg3_resume()
15924 if (!err) in tg3_resume()
15958 if (!netif_running(netdev)) in tg3_io_error_detected()
15973 /* Clean up software state, even if MMIO is blocked */ in tg3_io_error_detected()
15979 if (state == pci_channel_io_perm_failure) in tg3_io_error_detected()
15993 * Restart the card from scratch, as if from a cold-boot.
16007 if (pci_enable_device(pdev)) { in tg3_io_slot_reset()
16016 if (!netif_running(netdev)) { in tg3_io_slot_reset()
16022 if (err) in tg3_io_slot_reset()
16048 if (!netif_running(netdev)) in tg3_io_resume()
16055 if (err) { in tg3_io_resume()