ethernet/8390/8390.h

3    under the same license. Auto-loading of 8390.o only in v2.2 - Paul G.
4    Some of these names and comments originated from the Crynwr
17 /* The 8390 specific per-packet-header format. */
36 /* Without I/O delay - non ISA or later chips */
72 /* You have one of these per-board */
84 	unsigned word16:1;  		/* We have the 16-bit (vs 8-bit) version of the card. */
85 	unsigned bigendian:1;		/* 16-bit big endian mode. Do NOT */
94 	short tx1, tx2;			/* Packet lengths for ping-pong tx. */
98 	unsigned char saved_irq;	/* Original dev->irq value. */
139 #define E8390_PAGE1	0x40	/* using the two high-order bits */
144  *      - removed AMIGA_PCMCIA from this list, handled as ISA io now
145  *	- the _p for generates no delay by default 8390p.c overrides this.
166 #define EN0_TSR		EI_SHIFT(0x04)	/* Transmit status reg RD */
168 #define EN0_NCR		EI_SHIFT(0x05)	/* Number of collision reg RD */
172 #define EN0_ISR		EI_SHIFT(0x07)	/* Interrupt status reg RD WR */
174 #define EN0_RSARLO	EI_SHIFT(0x08)	/* Remote start address reg 0 */
176 #define EN0_RSARHI	EI_SHIFT(0x09)	/* Remote start address reg 1 */
177 #define EN0_RCNTLO	EI_SHIFT(0x0a)	/* Remote byte count reg WR */
178 #define EN0_RCNTHI	EI_SHIFT(0x0b)	/* Remote byte count reg WR */
179 #define EN0_RSR		EI_SHIFT(0x0c)	/* rx status reg RD */
180 #define EN0_RXCR	EI_SHIFT(0x0c)	/* RX configuration reg WR */
181 #define EN0_TXCR	EI_SHIFT(0x0d)	/* TX configuration reg WR */
183 #define EN0_DCFG	EI_SHIFT(0x0e)	/* Data configuration reg WR */
185 #define EN0_IMR		EI_SHIFT(0x0f)	/* Interrupt mask reg WR */
188 /* Bits in EN0_ISR - Interrupt status register */
199 /* Bits in EN0_DCFG - Data config register */
228 #define ENTSR_OWC 0x80  /* There was an out-of-window collision. */