mtd/maps/sc520cdp.c

21  * from AMD. It has two banks of 32-bit Flash ROM, each 8 Megabytes in size,
22  * and up to 512 KiB of 8-bit DIL Flash ROM.
36 ** The Embedded Systems BIOS decodes the first FLASH starting at
38 ** the flash at this location causes the A22 address line to be high
40 ** order address line on the raw flash devices themselves!!
41 ** This causes the top HALF of the flash to be accessed first. Beyond
42 ** the physical limits of the flash, the flash chip aliases over (to
44 ** flash into two and inverts it! If you then try to access this from another
46 ** first half of the flash, but not find what you expect there. That
48 ** BIOS for the second FLASH bank is also quite a bad choice.
50 ** choose more useful addresses for the FLASH banks by reprogramming the
88 		.name = "SC520CDP Flash Bank #0",
94 		.name = "SC520CDP Flash Bank #1",
100 		.name = "SC520CDP DIL Flash",
166 	{	/* Flash Bank #0: selected by ROMCS0 */
171 	{	/* Flash Bank #1: selected by ROMCS1 */
176 	{	/* DIL (BIOS) Flash: selected by BOOTCS */
233 	/* reprogram PAR registers so flash appears at the desired addresses */  in init_sc520cdp()
238 		printk(KERN_NOTICE "SC520 CDP flash device: 0x%Lx at 0x%Lx\n",  in init_sc520cdp()
266 		/* Combine the two flash banks into a single MTD device & register it: */  in init_sc520cdp()
267 		merged_mtd = mtd_concat_create(mymtd, 2, "SC520CDP Flash Banks #0 and #1");  in init_sc520cdp()
271 	if(devices_found == 3) /* register the third (DIL-Flash) device */  in init_sc520cdp()