20  *  02111-1307  USA
23 #include "cx18-driver.h"
24 #include "cx18-io.h"
25 #include "cx18-scb.h"
26 #include "cx18-irq.h"
27 #include "cx18-firmware.h"
28 #include "cx18-cards.h"
109 	if (request_firmware(&fw, fn, &cx->pci_dev->dev)) {  in load_cpu_fw_direct()
112 		return -ENOMEM;  in load_cpu_fw_direct()
115 	src = (const u32 *)fw->data;  in load_cpu_fw_direct()
117 	for (i = 0; i < fw->size; i += 4096) {  in load_cpu_fw_direct()
119 		for (j = i; j < fw->size && j < i + 4096; j += 4) {  in load_cpu_fw_direct()
126 				return -EIO;  in load_cpu_fw_direct()
132 	if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags))  in load_cpu_fw_direct()
133 		CX18_INFO("loaded %s firmware (%zd bytes)\n", fn, fw->size);  in load_cpu_fw_direct()
134 	size = fw->size;  in load_cpu_fw_direct()
153 	if (request_firmware(&fw, fn, &cx->pci_dev->dev)) {  in load_apu_fw_direct()
157 		return -ENOMEM;  in load_apu_fw_direct()
161 	src = (const u32 *)fw->data;  in load_apu_fw_direct()
162 	vers = fw->data + sizeof(seghdr);  in load_apu_fw_direct()
163 	sz = fw->size;  in load_apu_fw_direct()
166 	while (offset + sizeof(seghdr) < fw->size) {  in load_apu_fw_direct()
175 		CX18_DEBUG_INFO("load segment %x-%x\n", seghdr.addr,  in load_apu_fw_direct()
176 				seghdr.addr + seghdr.size - 1);  in load_apu_fw_direct()
193 					return -EIO;  in load_apu_fw_direct()
199 	if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags))  in load_apu_fw_direct()
201 				fn, apu_version, fw->size);  in load_apu_fw_direct()
202 	size = fw->size;  in load_apu_fw_direct()
219 	/* power-down Spare and AOM PLLs */  in cx18_init_power()
220 	/* power-up fast, slow and mpeg PLLs */  in cx18_init_power()
238 	 * the NTSC Standards", Proceedings of the I-R-E, January 1954, pp 79-80  in cx18_init_power()
241 	 * NTSC Standards", Proceedings of the I-R-E, January 1954, pp 81-83  in cx18_init_power()
254 	 * the shelf crystal will have for accuracy anyway.  in cx18_init_power()
263 	/* the fast clock is at 200/245 MHz */  in cx18_init_power()
264 	/* 1 * xtal_freq * 0x0d.f7df9b8 / 2 = 200 MHz: 400 MHz pre post-divide*/  in cx18_init_power()
265 	/* 1 * xtal_freq * 0x11.1c71eb8 / 2 = 245 MHz: 490 MHz pre post-divide*/  in cx18_init_power()
274 	/* set slow clock to 125/120 MHz */  in cx18_init_power()
275 	/* xtal_freq * 0x0d.1861a20 / 3 = 125 MHz: 375 MHz before post-divide */  in cx18_init_power()
276 	/* xtal_freq * 0x0c.92493f8 / 3 = 120 MHz: 360 MHz before post-divide */  in cx18_init_power()
282 	/* mpeg clock pll 54MHz */  in cx18_init_power()
283 	/* xtal_freq * 0xf.15f17f0 / 8 = 54 MHz: 432 MHz before post-divide */  in cx18_init_power()
309 		/* This doesn't explicitly set every clock select */  in cx18_init_power()
333 	cx18_write_reg(cx, cx->card->ddr.chip_config, CX18_DDR_CHIP_CONFIG);  in cx18_init_memory()
337 	cx18_write_reg(cx, cx->card->ddr.refresh, CX18_DDR_REFRESH);  in cx18_init_memory()
338 	cx18_write_reg(cx, cx->card->ddr.timing1, CX18_DDR_TIMING1);  in cx18_init_memory()
339 	cx18_write_reg(cx, cx->card->ddr.timing2, CX18_DDR_TIMING2);  in cx18_init_memory()
344 	cx18_write_reg(cx, cx->card->ddr.tune_lane, CX18_DDR_TUNE_LANE);  in cx18_init_memory()
345 	cx18_write_reg(cx, cx->card->ddr.initial_emrs, CX18_DDR_INITIAL_EMRS);  in cx18_init_memory()
353 	/* use power-down mode when idle */  in cx18_init_memory()
392 		return -EIO;  in cx18_firmware_init()
398 	sz = load_cpu_fw_direct("v4l-cx23418-cpu.fw", cx->enc_mem, cx);  in cx18_firmware_init()
406 	sz = load_apu_fw_direct("v4l-cx23418-apu.fw", cx->enc_mem, cx,  in cx18_firmware_init()
426 		return -EIO;  in cx18_firmware_init()