Lines Matching defs:drxk_state
197 struct drxk_state { struct
198 struct dvb_frontend frontend;
199 struct dtv_frontend_properties props;
200 struct device *dev;
202 struct i2c_adapter *i2c;
203 u8 demod_address;
204 void *priv;
206 struct mutex mutex;
208 u32 m_Instance; /**< Channel 1,2,3 or 4 */
210 int m_ChunkSize;
211 u8 Chunk[256];
213 bool m_hasLNA;
214 bool m_hasDVBT;
215 bool m_hasDVBC;
216 bool m_hasAudio;
217 bool m_hasATV;
218 bool m_hasOOB;
219 bool m_hasSAWSW; /**< TRUE if mat_tx is available */
220 bool m_hasGPIO1; /**< TRUE if mat_rx is available */
221 bool m_hasGPIO2; /**< TRUE if GPIO is available */
222 bool m_hasIRQN; /**< TRUE if IRQN is available */
223 u16 m_oscClockFreq;
224 u16 m_HICfgTimingDiv;
225 u16 m_HICfgBridgeDelay;
226 u16 m_HICfgWakeUpKey;
227 u16 m_HICfgTimeout;
228 u16 m_HICfgCtrl;
229 s32 m_sysClockFreq; /**< system clock frequency in kHz */
231 enum EDrxkState m_DrxkState; /**< State of Drxk (init,stopped,started) */
232 enum OperationMode m_OperationMode; /**< digital standards */
233 struct SCfgAgc m_vsbRfAgcCfg; /**< settings for VSB RF-AGC */
234 struct SCfgAgc m_vsbIfAgcCfg; /**< settings for VSB IF-AGC */
235 u16 m_vsbPgaCfg; /**< settings for VSB PGA */
236 struct SCfgPreSaw m_vsbPreSawCfg; /**< settings for pre SAW sense */
237 s32 m_Quality83percent; /**< MER level (*0.1 dB) for 83% quality indication */
238 s32 m_Quality93percent; /**< MER level (*0.1 dB) for 93% quality indication */
239 bool m_smartAntInverted;
240 bool m_bDebugEnableBridge;
241 …ol m_bPDownOpenBridge; /**< only open DRXK bridge before power-down once it has been accessed */
242 bool m_bPowerDown; /**< Power down when not used */
244 u32 m_IqmFsRateOfs; /**< frequency shift as written to DRXK register (28bit fixpoint) */
246 bool m_enableMPEGOutput; /**< If TRUE, enable MPEG output */
247 bool m_insertRSByte; /**< If TRUE, insert RS byte */
248 bool m_enableParallel; /**< If TRUE, parallel out otherwise serial */
249 bool m_invertDATA; /**< If TRUE, invert DATA signals */
250 bool m_invertERR; /**< If TRUE, invert ERR signal */
251 bool m_invertSTR; /**< If TRUE, invert STR signals */
252 bool m_invertVAL; /**< If TRUE, invert VAL signals */
253 bool m_invertCLK; /**< If TRUE, invert CLK signals */
254 bool m_DVBCStaticCLK;
255 bool m_DVBTStaticCLK; /**< If TRUE, static MPEG clockrate will
258 u32 m_DVBTBitrate;
259 u32 m_DVBCBitrate;
261 u8 m_TSDataStrength;
262 u8 m_TSClockkStrength;
264 bool m_itut_annex_c; /* If true, uses ITU-T DVB-C Annex C, instead of Annex A */
266 enum DRXMPEGStrWidth_t m_widthSTR; /**< MPEG start width */
267 u32 m_mpegTsStaticBitrate; /**< Maximum bitrate in b/s in case
271 s32 m_MpegLockTimeOut; /**< WaitForLockStatus Timeout (counts from start time) */
272 s32 m_DemodLockTimeOut; /**< WaitForLockStatus Timeout (counts from start time) */
274 bool m_disableTEIhandling;
276 bool m_RfAgcPol;
277 bool m_IfAgcPol;
279 struct SCfgAgc m_atvRfAgcCfg; /**< settings for ATV RF-AGC */
280 struct SCfgAgc m_atvIfAgcCfg; /**< settings for ATV IF-AGC */
281 struct SCfgPreSaw m_atvPreSawCfg; /**< settings for ATV pre SAW sense */
282 bool m_phaseCorrectionBypass;
283 s16 m_atvTopVidPeak;
284 u16 m_atvTopNoiseTh;
285 enum EDrxkSifAttenuation m_sifAttenuation;
286 bool m_enableCVBSOutput;
287 bool m_enableSIFOutput;
288 bool m_bMirrorFreqSpect;
289 enum EDrxkConstellation m_Constellation; /**< Constellation type of the channel */
290 u32 m_CurrSymbolRate; /**< Current QAM symbol rate */
291 struct SCfgAgc m_qamRfAgcCfg; /**< settings for QAM RF-AGC */
292 struct SCfgAgc m_qamIfAgcCfg; /**< settings for QAM IF-AGC */
293 u16 m_qamPgaCfg; /**< settings for QAM PGA */
294 struct SCfgPreSaw m_qamPreSawCfg; /**< settings for QAM pre SAW sense */
295 enum EDrxkInterleaveMode m_qamInterleaveMode; /**< QAM Interleave mode */
296 u16 m_fecRsPlen;
297 u16 m_fecRsPrescale;
299 enum DRXKCfgDvbtSqiSpeed m_sqiSpeed;
301 u16 m_GPIO;
302 u16 m_GPIOCfg;
304 struct SCfgAgc m_dvbtRfAgcCfg; /**< settings for QAM RF-AGC */
305 struct SCfgAgc m_dvbtIfAgcCfg; /**< settings for QAM IF-AGC */
306 struct SCfgPreSaw m_dvbtPreSawCfg; /**< settings for QAM pre SAW sense */
308 u16 m_agcFastClipCtrlDelay;
309 bool m_adcCompPassed;
310 u16 m_adcCompCoef[64];
311 u16 m_adcState;
313 u8 *m_microcode;
314 int m_microcode_length;
315 bool m_DRXK_A1_PATCH_CODE;
316 bool m_DRXK_A1_ROM_CODE;
317 bool m_DRXK_A2_ROM_CODE;
318 bool m_DRXK_A3_ROM_CODE;
319 bool m_DRXK_A2_PATCH_CODE;
320 bool m_DRXK_A3_PATCH_CODE;
322 bool m_rfmirror;
323 u8 m_deviceSpin;
324 u32 m_iqmRcRate;
326 enum DRXPowerMode m_currentPowerMode;
333 u16 UIO_mask; /* Bits used by UIO */
335 bool single_master;
336 bool no_i2c_bridge;
337 bool antenna_dvbt;
338 u16 antenna_gpio;
340 const char *microcode_name;