Lines Matching full:state
38 static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode);
39 static int PowerDownQAM(struct drxk_state *state);
40 static int SetDVBTStandard(struct drxk_state *state,
42 static int SetQAMStandard(struct drxk_state *state,
44 static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
46 static int SetDVBTStandard(struct drxk_state *state,
48 static int DVBTStart(struct drxk_state *state);
49 static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
51 static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus);
52 static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus);
53 static int SwitchAntennaToQAM(struct drxk_state *state);
54 static int SwitchAntennaToDVBT(struct drxk_state *state);
56 static bool IsDVBT(struct drxk_state *state) in IsDVBT() argument
58 return state->m_OperationMode == OM_DVBT; in IsDVBT()
61 static bool IsQAM(struct drxk_state *state) in IsQAM() argument
63 return state->m_OperationMode == OM_QAM_ITU_A || in IsQAM()
64 state->m_OperationMode == OM_QAM_ITU_B || in IsQAM()
65 state->m_OperationMode == OM_QAM_ITU_C; in IsQAM()
68 bool IsA1WithPatchCode(struct drxk_state *state) in IsA1WithPatchCode() argument
70 return state->m_DRXK_A1_PATCH_CODE; in IsA1WithPatchCode()
73 bool IsA1WithRomCode(struct drxk_state *state) in IsA1WithRomCode() argument
75 return state->m_DRXK_A1_ROM_CODE; in IsA1WithRomCode()
121 #define DRXK_KI_RAGC_DVBT (IsA1WithPatchCode(state) ? 3 : 2)
124 #define DRXK_KI_IAGC_DVBT (IsA1WithPatchCode(state) ? 4 : 2)
127 #define DRXK_KI_DAGC_DVBT (IsA1WithPatchCode(state) ? 10 : 7)
382 static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags) in read16_flags() argument
385 u8 adr = state->demod_address, mm1[4], mm2[2], len; in read16_flags()
387 if (state->single_master) in read16_flags()
402 status = i2c_read(state->i2c, adr, mm1, len, mm2, 2); in read16_flags()
411 static int read16(struct drxk_state *state, u32 reg, u16 *data) in read16() argument
413 return read16_flags(state, reg, data, 0); in read16()
416 static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags) in read32_flags() argument
419 u8 adr = state->demod_address, mm1[4], mm2[4], len; in read32_flags()
421 if (state->single_master) in read32_flags()
436 status = i2c_read(state->i2c, adr, mm1, len, mm2, 4); in read32_flags()
446 static int read32(struct drxk_state *state, u32 reg, u32 *data) in read32() argument
448 return read32_flags(state, reg, data, 0); in read32()
451 static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags) in write16_flags() argument
453 u8 adr = state->demod_address, mm[6], len; in write16_flags()
455 if (state->single_master) in write16_flags()
472 return i2c_write(state->i2c, adr, mm, len + 2); in write16_flags()
475 static int write16(struct drxk_state *state, u32 reg, u16 data) in write16() argument
477 return write16_flags(state, reg, data, 0); in write16()
480 static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags) in write32_flags() argument
482 u8 adr = state->demod_address, mm[8], len; in write32_flags()
484 if (state->single_master) in write32_flags()
503 return i2c_write(state->i2c, adr, mm, len + 4); in write32_flags()
506 static int write32(struct drxk_state *state, u32 reg, u32 data) in write32() argument
508 return write32_flags(state, reg, data, 0); in write32()
511 static int write_block(struct drxk_state *state, u32 Address, in write_block() argument
517 if (state->single_master) in write_block()
521 int Chunk = BlkSize > state->m_ChunkSize ? in write_block()
522 state->m_ChunkSize : BlkSize; in write_block()
523 u8 *AdrBuf = &state->Chunk[0]; in write_block()
533 if (Chunk == state->m_ChunkSize) in write_block()
541 memcpy(&state->Chunk[AdrLength], pBlock, Chunk); in write_block()
550 status = i2c_write(state->i2c, state->demod_address, in write_block()
551 &state->Chunk[0], Chunk + AdrLength); in write_block()
568 int PowerUpDevice(struct drxk_state *state) in PowerUpDevice() argument
576 status = i2c_read1(state->i2c, state->demod_address, &data); in PowerUpDevice()
580 status = i2c_write(state->i2c, state->demod_address, in PowerUpDevice()
586 status = i2c_read1(state->i2c, state->demod_address, in PowerUpDevice()
595 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE); in PowerUpDevice()
598 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); in PowerUpDevice()
602 status = write16(state, SIO_CC_PLL_LOCK__A, 1); in PowerUpDevice()
606 state->m_currentPowerMode = DRX_POWER_UP; in PowerUpDevice()
616 static int init_state(struct drxk_state *state) in init_state() argument
676 state->m_hasLNA = false; in init_state()
677 state->m_hasDVBT = false; in init_state()
678 state->m_hasDVBC = false; in init_state()
679 state->m_hasATV = false; in init_state()
680 state->m_hasOOB = false; in init_state()
681 state->m_hasAudio = false; in init_state()
683 if (!state->m_ChunkSize) in init_state()
684 state->m_ChunkSize = 124; in init_state()
686 state->m_oscClockFreq = 0; in init_state()
687 state->m_smartAntInverted = false; in init_state()
688 state->m_bPDownOpenBridge = false; in init_state()
691 state->m_sysClockFreq = 151875; in init_state()
694 state->m_HICfgTimingDiv = ((state->m_sysClockFreq / 1000) * in init_state()
697 if (state->m_HICfgTimingDiv > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M) in init_state()
698 state->m_HICfgTimingDiv = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M; in init_state()
699 state->m_HICfgWakeUpKey = (state->demod_address << 1); in init_state()
701 state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE; in init_state()
703 state->m_bPowerDown = (ulPowerDown != 0); in init_state()
705 state->m_DRXK_A1_PATCH_CODE = false; in init_state()
706 state->m_DRXK_A1_ROM_CODE = false; in init_state()
707 state->m_DRXK_A2_ROM_CODE = false; in init_state()
708 state->m_DRXK_A3_ROM_CODE = false; in init_state()
709 state->m_DRXK_A2_PATCH_CODE = false; in init_state()
710 state->m_DRXK_A3_PATCH_CODE = false; in init_state()
714 state->m_vsbIfAgcCfg.ctrlMode = (ulVSBIfAgcMode); in init_state()
715 state->m_vsbIfAgcCfg.outputLevel = (ulVSBIfAgcOutputLevel); in init_state()
716 state->m_vsbIfAgcCfg.minOutputLevel = (ulVSBIfAgcMinLevel); in init_state()
717 state->m_vsbIfAgcCfg.maxOutputLevel = (ulVSBIfAgcMaxLevel); in init_state()
718 state->m_vsbIfAgcCfg.speed = (ulVSBIfAgcSpeed); in init_state()
719 state->m_vsbPgaCfg = 140; in init_state()
722 state->m_vsbRfAgcCfg.ctrlMode = (ulVSBRfAgcMode); in init_state()
723 state->m_vsbRfAgcCfg.outputLevel = (ulVSBRfAgcOutputLevel); in init_state()
724 state->m_vsbRfAgcCfg.minOutputLevel = (ulVSBRfAgcMinLevel); in init_state()
725 state->m_vsbRfAgcCfg.maxOutputLevel = (ulVSBRfAgcMaxLevel); in init_state()
726 state->m_vsbRfAgcCfg.speed = (ulVSBRfAgcSpeed); in init_state()
727 state->m_vsbRfAgcCfg.top = (ulVSBRfAgcTop); in init_state()
728 state->m_vsbRfAgcCfg.cutOffCurrent = (ulVSBRfAgcCutOffCurrent); in init_state()
729 state->m_vsbPreSawCfg.reference = 0x07; in init_state()
730 state->m_vsbPreSawCfg.usePreSaw = true; in init_state()
732 state->m_Quality83percent = DEFAULT_MER_83; in init_state()
733 state->m_Quality93percent = DEFAULT_MER_93; in init_state()
735 state->m_Quality83percent = ulQual83; in init_state()
736 state->m_Quality93percent = ulQual93; in init_state()
740 state->m_atvIfAgcCfg.ctrlMode = (ulATVIfAgcMode); in init_state()
741 state->m_atvIfAgcCfg.outputLevel = (ulATVIfAgcOutputLevel); in init_state()
742 state->m_atvIfAgcCfg.minOutputLevel = (ulATVIfAgcMinLevel); in init_state()
743 state->m_atvIfAgcCfg.maxOutputLevel = (ulATVIfAgcMaxLevel); in init_state()
744 state->m_atvIfAgcCfg.speed = (ulATVIfAgcSpeed); in init_state()
747 state->m_atvRfAgcCfg.ctrlMode = (ulATVRfAgcMode); in init_state()
748 state->m_atvRfAgcCfg.outputLevel = (ulATVRfAgcOutputLevel); in init_state()
749 state->m_atvRfAgcCfg.minOutputLevel = (ulATVRfAgcMinLevel); in init_state()
750 state->m_atvRfAgcCfg.maxOutputLevel = (ulATVRfAgcMaxLevel); in init_state()
751 state->m_atvRfAgcCfg.speed = (ulATVRfAgcSpeed); in init_state()
752 state->m_atvRfAgcCfg.top = (ulATVRfAgcTop); in init_state()
753 state->m_atvRfAgcCfg.cutOffCurrent = (ulATVRfAgcCutOffCurrent); in init_state()
754 state->m_atvPreSawCfg.reference = 0x04; in init_state()
755 state->m_atvPreSawCfg.usePreSaw = true; in init_state()
759 state->m_dvbtRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF; in init_state()
760 state->m_dvbtRfAgcCfg.outputLevel = 0; in init_state()
761 state->m_dvbtRfAgcCfg.minOutputLevel = 0; in init_state()
762 state->m_dvbtRfAgcCfg.maxOutputLevel = 0xFFFF; in init_state()
763 state->m_dvbtRfAgcCfg.top = 0x2100; in init_state()
764 state->m_dvbtRfAgcCfg.cutOffCurrent = 4000; in init_state()
765 state->m_dvbtRfAgcCfg.speed = 1; in init_state()
769 state->m_dvbtIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO; in init_state()
770 state->m_dvbtIfAgcCfg.outputLevel = 0; in init_state()
771 state->m_dvbtIfAgcCfg.minOutputLevel = 0; in init_state()
772 state->m_dvbtIfAgcCfg.maxOutputLevel = 9000; in init_state()
773 state->m_dvbtIfAgcCfg.top = 13424; in init_state()
774 state->m_dvbtIfAgcCfg.cutOffCurrent = 0; in init_state()
775 state->m_dvbtIfAgcCfg.speed = 3; in init_state()
776 state->m_dvbtIfAgcCfg.FastClipCtrlDelay = 30; in init_state()
777 state->m_dvbtIfAgcCfg.IngainTgtMax = 30000; in init_state()
778 /* state->m_dvbtPgaCfg = 140; */ in init_state()
780 state->m_dvbtPreSawCfg.reference = 4; in init_state()
781 state->m_dvbtPreSawCfg.usePreSaw = false; in init_state()
784 state->m_qamRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF; in init_state()
785 state->m_qamRfAgcCfg.outputLevel = 0; in init_state()
786 state->m_qamRfAgcCfg.minOutputLevel = 6023; in init_state()
787 state->m_qamRfAgcCfg.maxOutputLevel = 27000; in init_state()
788 state->m_qamRfAgcCfg.top = 0x2380; in init_state()
789 state->m_qamRfAgcCfg.cutOffCurrent = 4000; in init_state()
790 state->m_qamRfAgcCfg.speed = 3; in init_state()
793 state->m_qamIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO; in init_state()
794 state->m_qamIfAgcCfg.outputLevel = 0; in init_state()
795 state->m_qamIfAgcCfg.minOutputLevel = 0; in init_state()
796 state->m_qamIfAgcCfg.maxOutputLevel = 9000; in init_state()
797 state->m_qamIfAgcCfg.top = 0x0511; in init_state()
798 state->m_qamIfAgcCfg.cutOffCurrent = 0; in init_state()
799 state->m_qamIfAgcCfg.speed = 3; in init_state()
800 state->m_qamIfAgcCfg.IngainTgtMax = 5119; in init_state()
801 state->m_qamIfAgcCfg.FastClipCtrlDelay = 50; in init_state()
803 state->m_qamPgaCfg = 140; in init_state()
804 state->m_qamPreSawCfg.reference = 4; in init_state()
805 state->m_qamPreSawCfg.usePreSaw = false; in init_state()
807 state->m_OperationMode = OM_NONE; in init_state()
808 state->m_DrxkState = DRXK_UNINITIALIZED; in init_state()
811 state->m_enableMPEGOutput = true; /* If TRUE; enable MPEG ouput */ in init_state()
812 state->m_insertRSByte = false; /* If TRUE; insert RS byte */ in init_state()
813 state->m_invertDATA = false; /* If TRUE; invert DATA signals */ in init_state()
814 state->m_invertERR = false; /* If TRUE; invert ERR signal */ in init_state()
815 state->m_invertSTR = false; /* If TRUE; invert STR signals */ in init_state()
816 state->m_invertVAL = false; /* If TRUE; invert VAL signals */ in init_state()
817 state->m_invertCLK = (ulInvertTSClock != 0); /* If TRUE; invert CLK signals */ in init_state()
818 state->m_DVBTStaticCLK = (ulDVBTStaticTSClock != 0); in init_state()
819 state->m_DVBCStaticCLK = (ulDVBCStaticTSClock != 0); in init_state()
823 state->m_DVBTBitrate = ulDVBTBitrate; in init_state()
824 state->m_DVBCBitrate = ulDVBCBitrate; in init_state()
826 state->m_TSDataStrength = (ulTSDataStrength & 0x07); in init_state()
827 state->m_TSClockkStrength = (ulTSClockkStrength & 0x07); in init_state()
830 state->m_mpegTsStaticBitrate = 19392658; in init_state()
831 state->m_disableTEIhandling = false; in init_state()
834 state->m_insertRSByte = true; in init_state()
836 state->m_MpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT; in init_state()
838 state->m_MpegLockTimeOut = ulMpegLockTimeOut; in init_state()
839 state->m_DemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT; in init_state()
841 state->m_DemodLockTimeOut = ulDemodLockTimeOut; in init_state()
844 state->m_Constellation = DRX_CONSTELLATION_AUTO; in init_state()
845 state->m_qamInterleaveMode = DRXK_QAM_I12_J17; in init_state()
846 state->m_fecRsPlen = 204 * 8; /* fecRsPlen annex A */ in init_state()
847 state->m_fecRsPrescale = 1; in init_state()
849 state->m_sqiSpeed = DRXK_DVBT_SQI_SPEED_MEDIUM; in init_state()
850 state->m_agcFastClipCtrlDelay = 0; in init_state()
852 state->m_GPIOCfg = (ulGPIOCfg); in init_state()
854 state->m_bPowerDown = false; in init_state()
855 state->m_currentPowerMode = DRX_POWER_DOWN; in init_state()
857 state->m_rfmirror = (ulRfMirror == 0); in init_state()
858 state->m_IfAgcPol = false; in init_state()
862 static int DRXX_Open(struct drxk_state *state) in DRXX_Open() argument
871 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); in DRXX_Open()
875 status = read16(state, SIO_TOP_COMM_KEY__A, &key); in DRXX_Open()
878 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); in DRXX_Open()
881 status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag); in DRXX_Open()
884 status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid); in DRXX_Open()
887 status = write16(state, SIO_TOP_COMM_KEY__A, key); in DRXX_Open()
894 static int GetDeviceCapabilities(struct drxk_state *state) in GetDeviceCapabilities() argument
905 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); in GetDeviceCapabilities()
908 status = write16(state, SIO_TOP_COMM_KEY__A, 0xFABA); in GetDeviceCapabilities()
911 status = read16(state, SIO_PDR_OHW_CFG__A, &sioPdrOhwCfg); in GetDeviceCapabilities()
914 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000); in GetDeviceCapabilities()
924 state->m_oscClockFreq = 27000; in GetDeviceCapabilities()
928 state->m_oscClockFreq = 20250; in GetDeviceCapabilities()
932 state->m_oscClockFreq = 20250; in GetDeviceCapabilities()
942 status = read32(state, SIO_TOP_JTAGID_LO__A, &sioTopJtagidLo); in GetDeviceCapabilities()
951 state->m_deviceSpin = DRXK_SPIN_A1; in GetDeviceCapabilities()
955 state->m_deviceSpin = DRXK_SPIN_A2; in GetDeviceCapabilities()
959 state->m_deviceSpin = DRXK_SPIN_A3; in GetDeviceCapabilities()
963 state->m_deviceSpin = DRXK_SPIN_UNKNOWN; in GetDeviceCapabilities()
972 state->m_hasLNA = false; in GetDeviceCapabilities()
973 state->m_hasOOB = false; in GetDeviceCapabilities()
974 state->m_hasATV = false; in GetDeviceCapabilities()
975 state->m_hasAudio = false; in GetDeviceCapabilities()
976 state->m_hasDVBT = true; in GetDeviceCapabilities()
977 state->m_hasDVBC = true; in GetDeviceCapabilities()
978 state->m_hasSAWSW = true; in GetDeviceCapabilities()
979 state->m_hasGPIO2 = false; in GetDeviceCapabilities()
980 state->m_hasGPIO1 = false; in GetDeviceCapabilities()
981 state->m_hasIRQN = false; in GetDeviceCapabilities()
985 state->m_hasLNA = false; in GetDeviceCapabilities()
986 state->m_hasOOB = false; in GetDeviceCapabilities()
987 state->m_hasATV = true; in GetDeviceCapabilities()
988 state->m_hasAudio = false; in GetDeviceCapabilities()
989 state->m_hasDVBT = true; in GetDeviceCapabilities()
990 state->m_hasDVBC = false; in GetDeviceCapabilities()
991 state->m_hasSAWSW = true; in GetDeviceCapabilities()
992 state->m_hasGPIO2 = true; in GetDeviceCapabilities()
993 state->m_hasGPIO1 = true; in GetDeviceCapabilities()
994 state->m_hasIRQN = false; in GetDeviceCapabilities()
998 state->m_hasLNA = false; in GetDeviceCapabilities()
999 state->m_hasOOB = false; in GetDeviceCapabilities()
1000 state->m_hasATV = true; in GetDeviceCapabilities()
1001 state->m_hasAudio = false; in GetDeviceCapabilities()
1002 state->m_hasDVBT = true; in GetDeviceCapabilities()
1003 state->m_hasDVBC = false; in GetDeviceCapabilities()
1004 state->m_hasSAWSW = true; in GetDeviceCapabilities()
1005 state->m_hasGPIO2 = true; in GetDeviceCapabilities()
1006 state->m_hasGPIO1 = true; in GetDeviceCapabilities()
1007 state->m_hasIRQN = false; in GetDeviceCapabilities()
1011 state->m_hasLNA = false; in GetDeviceCapabilities()
1012 state->m_hasOOB = false; in GetDeviceCapabilities()
1013 state->m_hasATV = true; in GetDeviceCapabilities()
1014 state->m_hasAudio = true; in GetDeviceCapabilities()
1015 state->m_hasDVBT = true; in GetDeviceCapabilities()
1016 state->m_hasDVBC = false; in GetDeviceCapabilities()
1017 state->m_hasSAWSW = true; in GetDeviceCapabilities()
1018 state->m_hasGPIO2 = true; in GetDeviceCapabilities()
1019 state->m_hasGPIO1 = true; in GetDeviceCapabilities()
1020 state->m_hasIRQN = false; in GetDeviceCapabilities()
1024 state->m_hasLNA = false; in GetDeviceCapabilities()
1025 state->m_hasOOB = false; in GetDeviceCapabilities()
1026 state->m_hasATV = true; in GetDeviceCapabilities()
1027 state->m_hasAudio = true; in GetDeviceCapabilities()
1028 state->m_hasDVBT = true; in GetDeviceCapabilities()
1029 state->m_hasDVBC = true; in GetDeviceCapabilities()
1030 state->m_hasSAWSW = true; in GetDeviceCapabilities()
1031 state->m_hasGPIO2 = true; in GetDeviceCapabilities()
1032 state->m_hasGPIO1 = true; in GetDeviceCapabilities()
1033 state->m_hasIRQN = false; in GetDeviceCapabilities()
1037 state->m_hasLNA = false; in GetDeviceCapabilities()
1038 state->m_hasOOB = false; in GetDeviceCapabilities()
1039 state->m_hasATV = true; in GetDeviceCapabilities()
1040 state->m_hasAudio = true; in GetDeviceCapabilities()
1041 state->m_hasDVBT = true; in GetDeviceCapabilities()
1042 state->m_hasDVBC = true; in GetDeviceCapabilities()
1043 state->m_hasSAWSW = true; in GetDeviceCapabilities()
1044 state->m_hasGPIO2 = true; in GetDeviceCapabilities()
1045 state->m_hasGPIO1 = true; in GetDeviceCapabilities()
1046 state->m_hasIRQN = false; in GetDeviceCapabilities()
1050 state->m_hasLNA = false; in GetDeviceCapabilities()
1051 state->m_hasOOB = false; in GetDeviceCapabilities()
1052 state->m_hasATV = true; in GetDeviceCapabilities()
1053 state->m_hasAudio = true; in GetDeviceCapabilities()
1054 state->m_hasDVBT = true; in GetDeviceCapabilities()
1055 state->m_hasDVBC = true; in GetDeviceCapabilities()
1056 state->m_hasSAWSW = true; in GetDeviceCapabilities()
1057 state->m_hasGPIO2 = true; in GetDeviceCapabilities()
1058 state->m_hasGPIO1 = true; in GetDeviceCapabilities()
1059 state->m_hasIRQN = false; in GetDeviceCapabilities()
1063 state->m_hasLNA = false; in GetDeviceCapabilities()
1064 state->m_hasOOB = false; in GetDeviceCapabilities()
1065 state->m_hasATV = true; in GetDeviceCapabilities()
1066 state->m_hasAudio = false; in GetDeviceCapabilities()
1067 state->m_hasDVBT = true; in GetDeviceCapabilities()
1068 state->m_hasDVBC = true; in GetDeviceCapabilities()
1069 state->m_hasSAWSW = true; in GetDeviceCapabilities()
1070 state->m_hasGPIO2 = true; in GetDeviceCapabilities()
1071 state->m_hasGPIO1 = true; in GetDeviceCapabilities()
1072 state->m_hasIRQN = false; in GetDeviceCapabilities()
1084 state->m_oscClockFreq / 1000, in GetDeviceCapabilities()
1085 state->m_oscClockFreq % 1000); in GetDeviceCapabilities()
1095 static int HI_Command(struct drxk_state *state, u16 cmd, u16 *pResult) in HI_Command() argument
1103 status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd); in HI_Command()
1111 ((state->m_HICfgCtrl) & in HI_Command()
1122 status = read16(state, SIO_HI_RA_RAM_CMD__A, in HI_Command()
1128 status = read16(state, SIO_HI_RA_RAM_RES__A, pResult); in HI_Command()
1137 static int HI_CfgCommand(struct drxk_state *state) in HI_CfgCommand() argument
1143 mutex_lock(&state->mutex); in HI_CfgCommand()
1145 status = write16(state, SIO_HI_RA_RAM_PAR_6__A, state->m_HICfgTimeout); in HI_CfgCommand()
1148 status = write16(state, SIO_HI_RA_RAM_PAR_5__A, state->m_HICfgCtrl); in HI_CfgCommand()
1151 status = write16(state, SIO_HI_RA_RAM_PAR_4__A, state->m_HICfgWakeUpKey); in HI_CfgCommand()
1154 status = write16(state, SIO_HI_RA_RAM_PAR_3__A, state->m_HICfgBridgeDelay); in HI_CfgCommand()
1157 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, state->m_HICfgTimingDiv); in HI_CfgCommand()
1160 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY); in HI_CfgCommand()
1163 status = HI_Command(state, SIO_HI_RA_RAM_CMD_CONFIG, 0); in HI_CfgCommand()
1167 state->m_HICfgCtrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; in HI_CfgCommand()
1169 mutex_unlock(&state->mutex); in HI_CfgCommand()
1175 static int InitHI(struct drxk_state *state) in InitHI() argument
1179 state->m_HICfgWakeUpKey = (state->demod_address << 1); in InitHI()
1180 state->m_HICfgTimeout = 0x96FF; in InitHI()
1182 state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE; in InitHI()
1184 return HI_CfgCommand(state); in InitHI()
1187 static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable) in MPEGTSConfigurePins() argument
1195 state->m_enableParallel ? "parallel" : "serial"); in MPEGTSConfigurePins()
1198 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); in MPEGTSConfigurePins()
1203 status = write16(state, SIO_TOP_COMM_KEY__A, 0xFABA); in MPEGTSConfigurePins()
1209 status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000); in MPEGTSConfigurePins()
1212 status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000); in MPEGTSConfigurePins()
1215 status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000); in MPEGTSConfigurePins()
1218 status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000); in MPEGTSConfigurePins()
1221 status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000); in MPEGTSConfigurePins()
1224 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000); in MPEGTSConfigurePins()
1227 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000); in MPEGTSConfigurePins()
1230 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000); in MPEGTSConfigurePins()
1233 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000); in MPEGTSConfigurePins()
1236 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000); in MPEGTSConfigurePins()
1239 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000); in MPEGTSConfigurePins()
1242 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000); in MPEGTSConfigurePins()
1248 ((state->m_TSDataStrength << in MPEGTSConfigurePins()
1250 sioPdrMclkCfg = ((state->m_TSClockkStrength << in MPEGTSConfigurePins()
1254 status = write16(state, SIO_PDR_MSTRT_CFG__A, sioPdrMdxCfg); in MPEGTSConfigurePins()
1257 status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000); /* Disable */ in MPEGTSConfigurePins()
1260 status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000); /* Disable */ in MPEGTSConfigurePins()
1263 if (state->m_enableParallel == true) { in MPEGTSConfigurePins()
1265 status = write16(state, SIO_PDR_MD1_CFG__A, sioPdrMdxCfg); in MPEGTSConfigurePins()
1268 status = write16(state, SIO_PDR_MD2_CFG__A, sioPdrMdxCfg); in MPEGTSConfigurePins()
1271 status = write16(state, SIO_PDR_MD3_CFG__A, sioPdrMdxCfg); in MPEGTSConfigurePins()
1274 status = write16(state, SIO_PDR_MD4_CFG__A, sioPdrMdxCfg); in MPEGTSConfigurePins()
1277 status = write16(state, SIO_PDR_MD5_CFG__A, sioPdrMdxCfg); in MPEGTSConfigurePins()
1280 status = write16(state, SIO_PDR_MD6_CFG__A, sioPdrMdxCfg); in MPEGTSConfigurePins()
1283 status = write16(state, SIO_PDR_MD7_CFG__A, sioPdrMdxCfg); in MPEGTSConfigurePins()
1287 sioPdrMdxCfg = ((state->m_TSDataStrength << in MPEGTSConfigurePins()
1291 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000); in MPEGTSConfigurePins()
1294 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000); in MPEGTSConfigurePins()
1297 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000); in MPEGTSConfigurePins()
1300 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000); in MPEGTSConfigurePins()
1303 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000); in MPEGTSConfigurePins()
1306 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000); in MPEGTSConfigurePins()
1309 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000); in MPEGTSConfigurePins()
1313 status = write16(state, SIO_PDR_MCLK_CFG__A, sioPdrMclkCfg); in MPEGTSConfigurePins()
1316 status = write16(state, SIO_PDR_MD0_CFG__A, sioPdrMdxCfg); in MPEGTSConfigurePins()
1321 status = write16(state, SIO_PDR_MON_CFG__A, 0x0000); in MPEGTSConfigurePins()
1325 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000); in MPEGTSConfigurePins()
1332 static int MPEGTSDisable(struct drxk_state *state) in MPEGTSDisable() argument
1336 return MPEGTSConfigurePins(state, false); in MPEGTSDisable()
1339 static int BLChainCmd(struct drxk_state *state, in BLChainCmd() argument
1347 mutex_lock(&state->mutex); in BLChainCmd()
1348 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN); in BLChainCmd()
1351 status = write16(state, SIO_BL_CHAIN_ADDR__A, romOffset); in BLChainCmd()
1354 status = write16(state, SIO_BL_CHAIN_LEN__A, nrOfElements); in BLChainCmd()
1357 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON); in BLChainCmd()
1364 status = read16(state, SIO_BL_STATUS__A, &blStatus); in BLChainCmd()
1379 mutex_unlock(&state->mutex); in BLChainCmd()
1384 static int DownloadMicrocode(struct drxk_state *state, in DownloadMicrocode() argument
1431 status = write_block(state, Address, BlockSize, pSrc); in DownloadMicrocode()
1442 static int DVBTEnableOFDMTokenRing(struct drxk_state *state, bool enable) in DVBTEnableOFDMTokenRing() argument
1457 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data); in DVBTEnableOFDMTokenRing()
1463 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desiredCtrl); in DVBTEnableOFDMTokenRing()
1467 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data); in DVBTEnableOFDMTokenRing()
1479 static int MPEGTSStop(struct drxk_state *state) in MPEGTSStop() argument
1488 status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode); in MPEGTSStop()
1492 status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode); in MPEGTSStop()
1497 status = read16(state, FEC_OC_IPR_MODE__A, &fecOcIprMode); in MPEGTSStop()
1501 status = write16(state, FEC_OC_IPR_MODE__A, fecOcIprMode); in MPEGTSStop()
1510 static int scu_command(struct drxk_state *state, in scu_command() argument
1531 mutex_lock(&state->mutex); in scu_command()
1542 write_block(state, SCU_RAM_PARAM_0__A - in scu_command()
1548 status = read16(state, SCU_RAM_COMMAND__A, &curCmd); in scu_command()
1563 status = read16(state, SCU_RAM_PARAM_0__A - ii, &result[ii]); in scu_command()
1601 mutex_unlock(&state->mutex); in scu_command()
1605 static int SetIqmAf(struct drxk_state *state, bool active) in SetIqmAf() argument
1613 status = read16(state, IQM_AF_STDBY__A, &data); in SetIqmAf()
1631 status = write16(state, IQM_AF_STDBY__A, data); in SetIqmAf()
1639 static int CtrlPowerMode(struct drxk_state *state, enum DRXPowerMode *mode) in CtrlPowerMode() argument
1672 if (state->m_currentPowerMode == *mode) in CtrlPowerMode()
1676 if (state->m_currentPowerMode != DRX_POWER_UP) { in CtrlPowerMode()
1677 status = PowerUpDevice(state); in CtrlPowerMode()
1680 status = DVBTEnableOFDMTokenRing(state, true); in CtrlPowerMode()
1697 switch (state->m_OperationMode) { in CtrlPowerMode()
1699 status = MPEGTSStop(state); in CtrlPowerMode()
1702 status = PowerDownDVBT(state, false); in CtrlPowerMode()
1708 status = MPEGTSStop(state); in CtrlPowerMode()
1711 status = PowerDownQAM(state); in CtrlPowerMode()
1718 status = DVBTEnableOFDMTokenRing(state, false); in CtrlPowerMode()
1721 status = write16(state, SIO_CC_PWD_MODE__A, sioCcPwdMode); in CtrlPowerMode()
1724 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); in CtrlPowerMode()
1729 state->m_HICfgCtrl |= in CtrlPowerMode()
1731 status = HI_CfgCommand(state); in CtrlPowerMode()
1736 state->m_currentPowerMode = *mode; in CtrlPowerMode()
1745 static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode) in PowerDownDVBT() argument
1754 status = read16(state, SCU_COMM_EXEC__A, &data); in PowerDownDVBT()
1759 …status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NUL… in PowerDownDVBT()
1763 …status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NU… in PowerDownDVBT()
1769 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP); in PowerDownDVBT()
1772 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP); in PowerDownDVBT()
1775 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP); in PowerDownDVBT()
1780 status = SetIqmAf(state, false); in PowerDownDVBT()
1786 status = CtrlPowerMode(state, &powerMode); in PowerDownDVBT()
1796 static int SetOperationMode(struct drxk_state *state, in SetOperationMode() argument
1809 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); in SetOperationMode()
1814 if (state->m_OperationMode == oMode) in SetOperationMode()
1817 switch (state->m_OperationMode) { in SetOperationMode()
1822 status = MPEGTSStop(state); in SetOperationMode()
1825 status = PowerDownDVBT(state, true); in SetOperationMode()
1828 state->m_OperationMode = OM_NONE; in SetOperationMode()
1832 status = MPEGTSStop(state); in SetOperationMode()
1835 status = PowerDownQAM(state); in SetOperationMode()
1838 state->m_OperationMode = OM_NONE; in SetOperationMode()
1852 state->m_OperationMode = oMode; in SetOperationMode()
1853 status = SetDVBTStandard(state, oMode); in SetOperationMode()
1860 (state->m_OperationMode == OM_QAM_ITU_A) ? 'A' : 'C'); in SetOperationMode()
1861 state->m_OperationMode = oMode; in SetOperationMode()
1862 status = SetQAMStandard(state, oMode); in SetOperationMode()
1876 static int Start(struct drxk_state *state, s32 offsetFreq, in Start() argument
1885 if (state->m_DrxkState != DRXK_STOPPED && in Start()
1886 state->m_DrxkState != DRXK_DTV_STARTED) in Start()
1889 state->m_bMirrorFreqSpect = (state->props.inversion == INVERSION_ON); in Start()
1892 state->m_bMirrorFreqSpect = !state->m_bMirrorFreqSpect; in Start()
1896 switch (state->m_OperationMode) { in Start()
1900 status = SetQAM(state, IFreqkHz, OffsetkHz); in Start()
1903 state->m_DrxkState = DRXK_DTV_STARTED; in Start()
1907 status = MPEGTSStop(state); in Start()
1910 status = SetDVBT(state, IFreqkHz, OffsetkHz); in Start()
1913 status = DVBTStart(state); in Start()
1916 state->m_DrxkState = DRXK_DTV_STARTED; in Start()
1927 static int ShutDown(struct drxk_state *state) in ShutDown() argument
1931 MPEGTSStop(state); in ShutDown()
1935 static int GetLockStatus(struct drxk_state *state, u32 *pLockStatus, in GetLockStatus() argument
1948 switch (state->m_OperationMode) { in GetLockStatus()
1952 status = GetQAMLockStatus(state, pLockStatus); in GetLockStatus()
1955 status = GetDVBTLockStatus(state, pLockStatus); in GetLockStatus()
1966 static int MPEGTSStart(struct drxk_state *state) in MPEGTSStart() argument
1973 status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode); in MPEGTSStart()
1977 status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode); in MPEGTSStart()
1980 status = write16(state, FEC_OC_SNC_UNLOCK__A, 1); in MPEGTSStart()
1987 static int MPEGTSDtoInit(struct drxk_state *state) in MPEGTSDtoInit() argument
1994 status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000); in MPEGTSDtoInit()
1997 status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C); in MPEGTSDtoInit()
2000 status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A); in MPEGTSDtoInit()
2003 status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008); in MPEGTSDtoInit()
2006 status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006); in MPEGTSDtoInit()
2009 status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680); in MPEGTSDtoInit()
2012 status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080); in MPEGTSDtoInit()
2015 status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4); in MPEGTSDtoInit()
2020 status = write16(state, FEC_OC_OCR_INVERT__A, 0); in MPEGTSDtoInit()
2023 status = write16(state, FEC_OC_SNC_LWM__A, 2); in MPEGTSDtoInit()
2026 status = write16(state, FEC_OC_SNC_HWM__A, 12); in MPEGTSDtoInit()
2034 static int MPEGTSDtoSetup(struct drxk_state *state, in MPEGTSDtoSetup() argument
2054 status = read16(state, FEC_OC_MODE__A, &fecOcRegMode); in MPEGTSDtoSetup()
2057 status = read16(state, FEC_OC_IPR_MODE__A, &fecOcRegIprMode); in MPEGTSDtoSetup()
2062 if (state->m_insertRSByte == true) { in MPEGTSDtoSetup()
2073 if (state->m_enableParallel == false) { in MPEGTSDtoSetup()
2080 maxBitRate = state->m_DVBTBitrate; in MPEGTSDtoSetup()
2083 staticCLK = state->m_DVBTStaticCLK; in MPEGTSDtoSetup()
2089 maxBitRate = state->m_DVBCBitrate; in MPEGTSDtoSetup()
2090 staticCLK = state->m_DVBCStaticCLK; in MPEGTSDtoSetup()
2122 fecOcDtoPeriod = (u16) (((state->m_sysClockFreq) in MPEGTSDtoSetup()
2137 status = write16(state, FEC_OC_DTO_BURST_LEN__A, fecOcDtoBurstLen); in MPEGTSDtoSetup()
2140 status = write16(state, FEC_OC_DTO_PERIOD__A, fecOcDtoPeriod); in MPEGTSDtoSetup()
2143 status = write16(state, FEC_OC_DTO_MODE__A, fecOcDtoMode); in MPEGTSDtoSetup()
2146 status = write16(state, FEC_OC_FCT_MODE__A, fecOcFctMode); in MPEGTSDtoSetup()
2149 status = write16(state, FEC_OC_MODE__A, fecOcRegMode); in MPEGTSDtoSetup()
2152 status = write16(state, FEC_OC_IPR_MODE__A, fecOcRegIprMode); in MPEGTSDtoSetup()
2157 status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fecOcRcnCtlRate); in MPEGTSDtoSetup()
2160 status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A, fecOcTmdIntUpdRate); in MPEGTSDtoSetup()
2163 status = write16(state, FEC_OC_TMD_MODE__A, fecOcTmdMode); in MPEGTSDtoSetup()
2170 static int MPEGTSConfigurePolarity(struct drxk_state *state) in MPEGTSConfigurePolarity() argument
2185 if (state->m_invertDATA == true) in MPEGTSConfigurePolarity()
2188 if (state->m_invertERR == true) in MPEGTSConfigurePolarity()
2191 if (state->m_invertSTR == true) in MPEGTSConfigurePolarity()
2194 if (state->m_invertVAL == true) in MPEGTSConfigurePolarity()
2197 if (state->m_invertCLK == true) in MPEGTSConfigurePolarity()
2200 return write16(state, FEC_OC_IPR_INVERT__A, fecOcRegIprInvert); in MPEGTSConfigurePolarity()
2205 static int SetAgcRf(struct drxk_state *state, in SetAgcRf() argument
2220 status = read16(state, IQM_AF_STDBY__A, &data); in SetAgcRf()
2224 status = write16(state, IQM_AF_STDBY__A, data); in SetAgcRf()
2227 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); in SetAgcRf()
2235 if (state->m_RfAgcPol) in SetAgcRf()
2239 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); in SetAgcRf()
2244 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data); in SetAgcRf()
2253 status = write16(state, SCU_RAM_AGC_KI_RED__A, data); in SetAgcRf()
2257 if (IsDVBT(state)) in SetAgcRf()
2258 pIfAgcSettings = &state->m_dvbtIfAgcCfg; in SetAgcRf()
2259 else if (IsQAM(state)) in SetAgcRf()
2260 pIfAgcSettings = &state->m_qamIfAgcCfg; in SetAgcRf()
2262 pIfAgcSettings = &state->m_atvIfAgcCfg; in SetAgcRf()
2270 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->top); in SetAgcRf()
2275 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, pAgcCfg->cutOffCurrent); in SetAgcRf()
2280 status = write16(state, SCU_RAM_AGC_RF_MAX__A, pAgcCfg->maxOutputLevel); in SetAgcRf()
2288 status = read16(state, IQM_AF_STDBY__A, &data); in SetAgcRf()
2292 status = write16(state, IQM_AF_STDBY__A, data); in SetAgcRf()
2297 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); in SetAgcRf()
2301 if (state->m_RfAgcPol) in SetAgcRf()
2305 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); in SetAgcRf()
2310 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0); in SetAgcRf()
2315 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, pAgcCfg->outputLevel); in SetAgcRf()
2322 status = read16(state, IQM_AF_STDBY__A, &data); in SetAgcRf()
2326 status = write16(state, IQM_AF_STDBY__A, data); in SetAgcRf()
2331 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); in SetAgcRf()
2335 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); in SetAgcRf()
2352 static int SetAgcIf(struct drxk_state *state, in SetAgcIf() argument
2365 status = read16(state, IQM_AF_STDBY__A, &data); in SetAgcIf()
2369 status = write16(state, IQM_AF_STDBY__A, data); in SetAgcIf()
2373 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); in SetAgcIf()
2381 if (state->m_IfAgcPol) in SetAgcIf()
2385 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); in SetAgcIf()
2390 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data); in SetAgcIf()
2398 status = write16(state, SCU_RAM_AGC_KI_RED__A, data); in SetAgcIf()
2402 if (IsQAM(state)) in SetAgcIf()
2403 pRfAgcSettings = &state->m_qamRfAgcCfg; in SetAgcIf()
2405 pRfAgcSettings = &state->m_atvRfAgcCfg; in SetAgcIf()
2409 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pRfAgcSettings->top); in SetAgcIf()
2417 status = read16(state, IQM_AF_STDBY__A, &data); in SetAgcIf()
2421 status = write16(state, IQM_AF_STDBY__A, data); in SetAgcIf()
2425 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); in SetAgcIf()
2433 if (state->m_IfAgcPol) in SetAgcIf()
2437 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); in SetAgcIf()
2442 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->outputLevel); in SetAgcIf()
2450 status = read16(state, IQM_AF_STDBY__A, &data); in SetAgcIf()
2454 status = write16(state, IQM_AF_STDBY__A, data); in SetAgcIf()
2459 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); in SetAgcIf()
2463 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); in SetAgcIf()
2471 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, pAgcCfg->top); in SetAgcIf()
2478 static int ReadIFAgc(struct drxk_state *state, u32 *pValue) in ReadIFAgc() argument
2486 status = read16(state, IQM_AF_AGC_IF__A, &agcDacLvl); in ReadIFAgc()
2504 static int GetQAMSignalToNoise(struct drxk_state *state, in GetQAMSignalToNoise() argument
2519 status = read16(state, QAM_SL_ERR_POWER__A, &qamSlErrPower); in GetQAMSignalToNoise()
2525 switch (state->props.modulation) { in GetQAMSignalToNoise()
2553 static int GetDVBTSignalToNoise(struct drxk_state *state, in GetDVBTSignalToNoise() argument
2573 status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, &EqRegTdTpsPwrOfs); in GetDVBTSignalToNoise()
2576 status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, &EqRegTdReqSmbCnt); in GetDVBTSignalToNoise()
2579 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, &EqRegTdSqrErrExp); in GetDVBTSignalToNoise()
2582 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, ®Data); in GetDVBTSignalToNoise()
2591 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, ®Data); in GetDVBTSignalToNoise()
2600 status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A, &transmissionParams); in GetDVBTSignalToNoise()
2657 static int GetSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise) in GetSignalToNoise() argument
2662 switch (state->m_OperationMode) { in GetSignalToNoise()
2664 return GetDVBTSignalToNoise(state, pSignalToNoise); in GetSignalToNoise()
2667 return GetQAMSignalToNoise(state, pSignalToNoise); in GetSignalToNoise()
2675 static int GetDVBTQuality(struct drxk_state *state, s32 *pQuality)
2709 status = GetDVBTSignalToNoise(state, &SignalToNoise);
2712 status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A, &Constellation);
2717 status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A, &CodeRate);
2740 static int GetDVBCQuality(struct drxk_state *state, s32 *pQuality)
2752 status = GetQAMSignalToNoise(state, &SignalToNoise);
2756 switch (state->props.modulation) {
2787 static int GetQuality(struct drxk_state *state, s32 *pQuality)
2791 switch (state->m_OperationMode) {
2793 return GetDVBTQuality(state, pQuality);
2795 return GetDVBCQuality(state, pQuality);
2817 static int ConfigureI2CBridge(struct drxk_state *state, bool bEnableBridge) in ConfigureI2CBridge() argument
2823 if (state->m_DrxkState == DRXK_UNINITIALIZED) in ConfigureI2CBridge()
2825 if (state->m_DrxkState == DRXK_POWERED_DOWN) in ConfigureI2CBridge()
2828 if (state->no_i2c_bridge) in ConfigureI2CBridge()
2831 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY); in ConfigureI2CBridge()
2835 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED); in ConfigureI2CBridge()
2839 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN); in ConfigureI2CBridge()
2844 status = HI_Command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, 0); in ConfigureI2CBridge()
2852 static int SetPreSaw(struct drxk_state *state, in SetPreSaw() argument
2863 status = write16(state, IQM_AF_PDREF__A, pPreSawCfg->reference); in SetPreSaw()
2870 static int BLDirectCmd(struct drxk_state *state, u32 targetAddr, in BLDirectCmd() argument
2881 mutex_lock(&state->mutex); in BLDirectCmd()
2882 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT); in BLDirectCmd()
2885 status = write16(state, SIO_BL_TGT_HDR__A, blockbank); in BLDirectCmd()
2888 status = write16(state, SIO_BL_TGT_ADDR__A, offset); in BLDirectCmd()
2891 status = write16(state, SIO_BL_SRC_ADDR__A, romOffset); in BLDirectCmd()
2894 status = write16(state, SIO_BL_SRC_LEN__A, nrOfElements); in BLDirectCmd()
2897 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON); in BLDirectCmd()
2903 status = read16(state, SIO_BL_STATUS__A, &blStatus); in BLDirectCmd()
2916 mutex_unlock(&state->mutex); in BLDirectCmd()
2921 static int ADCSyncMeasurement(struct drxk_state *state, u16 *count) in ADCSyncMeasurement() argument
2929 status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE); in ADCSyncMeasurement()
2932 status = write16(state, IQM_AF_START_LOCK__A, 1); in ADCSyncMeasurement()
2937 status = read16(state, IQM_AF_PHASE0__A, &data); in ADCSyncMeasurement()
2942 status = read16(state, IQM_AF_PHASE1__A, &data); in ADCSyncMeasurement()
2947 status = read16(state, IQM_AF_PHASE2__A, &data); in ADCSyncMeasurement()
2959 static int ADCSynchronization(struct drxk_state *state) in ADCSynchronization() argument
2966 status = ADCSyncMeasurement(state, &count); in ADCSynchronization()
2974 status = read16(state, IQM_AF_CLKNEG__A, &clkNeg); in ADCSynchronization()
2987 status = write16(state, IQM_AF_CLKNEG__A, clkNeg); in ADCSynchronization()
2990 status = ADCSyncMeasurement(state, &count); in ADCSynchronization()
3003 static int SetFrequencyShifter(struct drxk_state *state, in SetFrequencyShifter() argument
3010 bool tunerMirror = !state->m_bMirrorFreqSpect; in SetFrequencyShifter()
3015 u32 samplingFrequency = (u32) (state->m_sysClockFreq / 3); in SetFrequencyShifter()
3026 if ((state->m_OperationMode == OM_QAM_ITU_A) || in SetFrequencyShifter()
3027 (state->m_OperationMode == OM_QAM_ITU_C) || in SetFrequencyShifter()
3028 (state->m_OperationMode == OM_DVBT)) in SetFrequencyShifter()
3052 imageToSelect = state->m_rfmirror ^ tunerMirror ^ in SetFrequencyShifter()
3054 state->m_IqmFsRateOfs = in SetFrequencyShifter()
3058 state->m_IqmFsRateOfs = ~state->m_IqmFsRateOfs + 1; in SetFrequencyShifter()
3062 status = write32(state, IQM_FS_RATE_OFS_LO__A, in SetFrequencyShifter()
3063 state->m_IqmFsRateOfs); in SetFrequencyShifter()
3069 static int InitAGC(struct drxk_state *state, bool isDTV) in InitAGC() argument
3099 if (!IsQAM(state)) { in InitAGC()
3100 printk(KERN_ERR "drxk: %s: mode %d is not DVB-C\n", __func__, state->m_OperationMode); in InitAGC()
3118 fastClpCtrlDelay = state->m_qamIfAgcCfg.FastClipCtrlDelay; in InitAGC()
3120 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, fastClpCtrlDelay); in InitAGC()
3124 status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clpCtrlMode); in InitAGC()
3127 status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingainTgt); in InitAGC()
3130 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingainTgtMin); in InitAGC()
3133 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingainTgtMax); in InitAGC()
3136 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, ifIaccuHiTgtMin); in InitAGC()
3139 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, ifIaccuHiTgtMax); in InitAGC()
3142 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0); in InitAGC()
3145 status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0); in InitAGC()
3148 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0); in InitAGC()
3151 status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0); in InitAGC()
3154 status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clpSumMax); in InitAGC()
3157 status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, snsSumMax); in InitAGC()
3161 status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, kiInnergainMin); in InitAGC()
3164 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, ifIaccuHiTgt); in InitAGC()
3167 status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clpCyclen); in InitAGC()
3171 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023); in InitAGC()
3174 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023); in InitAGC()
3177 status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50); in InitAGC()
3181 status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20); in InitAGC()
3184 status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clpSumMin); in InitAGC()
3187 status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, snsSumMin); in InitAGC()
3190 status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clpDirTo); in InitAGC()
3193 status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, snsDirTo); in InitAGC()
3196 status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff); in InitAGC()
3199 status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0); in InitAGC()
3202 status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117); in InitAGC()
3205 status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657); in InitAGC()
3208 status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0); in InitAGC()
3211 status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0); in InitAGC()
3214 status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0); in InitAGC()
3217 status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1); in InitAGC()
3220 status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0); in InitAGC()
3223 status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0); in InitAGC()
3226 status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0); in InitAGC()
3229 status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1); in InitAGC()
3232 status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500); in InitAGC()
3235 status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500); in InitAGC()
3240 status = read16(state, SCU_RAM_AGC_KI__A, &data); in InitAGC()
3250 status = write16(state, SCU_RAM_AGC_KI__A, data); in InitAGC()
3257 static int DVBTQAMGetAccPktErr(struct drxk_state *state, u16 *packetErr) in DVBTQAMGetAccPktErr() argument
3263 status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0); in DVBTQAMGetAccPktErr()
3265 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, packetErr); in DVBTQAMGetAccPktErr()
3271 static int DVBTScCommand(struct drxk_state *state, in DVBTScCommand() argument
3283 status = read16(state, OFDM_SC_COMM_EXEC__A, &scExec); in DVBTScCommand()
3295 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd); in DVBTScCommand()
3307 status = write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd); in DVBTScCommand()
3325 status = write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1); in DVBTScCommand()
3329 status = write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0); in DVBTScCommand()
3334 status = write16(state, OFDM_SC_RA_RAM_CMD__A, cmd); in DVBTScCommand()
3347 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd); in DVBTScCommand()
3354 status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &errCode); in DVBTScCommand()
3371 status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0)); in DVBTScCommand()
3391 static int PowerUpDVBT(struct drxk_state *state) in PowerUpDVBT() argument
3397 status = CtrlPowerMode(state, &powerMode); in PowerUpDVBT()
3403 static int DVBTCtrlSetIncEnable(struct drxk_state *state, bool *enabled) in DVBTCtrlSetIncEnable() argument
3409 status = write16(state, IQM_CF_BYPASSDET__A, 0); in DVBTCtrlSetIncEnable()
3411 status = write16(state, IQM_CF_BYPASSDET__A, 1); in DVBTCtrlSetIncEnable()
3418 static int DVBTCtrlSetFrEnable(struct drxk_state *state, bool *enabled) in DVBTCtrlSetFrEnable() argument
3426 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, in DVBTCtrlSetFrEnable()
3430 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0); in DVBTCtrlSetFrEnable()
3438 static int DVBTCtrlSetEchoThreshold(struct drxk_state *state, in DVBTCtrlSetEchoThreshold() argument
3445 status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data); in DVBTCtrlSetEchoThreshold()
3466 status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data); in DVBTCtrlSetEchoThreshold()
3473 static int DVBTCtrlSetSqiSpeed(struct drxk_state *state, in DVBTCtrlSetSqiSpeed() argument
3488 status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A, in DVBTCtrlSetSqiSpeed()
3506 static int DVBTActivatePresets(struct drxk_state *state) in DVBTActivatePresets() argument
3516 status = DVBTCtrlSetIncEnable(state, &setincenable); in DVBTActivatePresets()
3519 status = DVBTCtrlSetFrEnable(state, &setfrenable); in DVBTActivatePresets()
3522 status = DVBTCtrlSetEchoThreshold(state, &echoThres2k); in DVBTActivatePresets()
3525 status = DVBTCtrlSetEchoThreshold(state, &echoThres8k); in DVBTActivatePresets()
3528 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, state->m_dvbtIfAgcCfg.IngainTgtMax); in DVBTActivatePresets()
3545 static int SetDVBTStandard(struct drxk_state *state, in SetDVBTStandard() argument
3554 PowerUpDVBT(state); in SetDVBTStandard()
3556 SwitchAntennaToDVBT(state); in SetDVBTStandard()
3558 …status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NU… in SetDVBTStandard()
3563 …status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 0, … in SetDVBTStandard()
3568 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP); in SetDVBTStandard()
3571 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP); in SetDVBTStandard()
3574 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP); in SetDVBTStandard()
3580 status = write16(state, IQM_AF_UPD_SEL__A, 1); in SetDVBTStandard()
3584 status = write16(state, IQM_AF_CLP_LEN__A, 0); in SetDVBTStandard()
3588 status = write16(state, IQM_AF_SNS_LEN__A, 0); in SetDVBTStandard()
3592 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC); in SetDVBTStandard()
3595 status = SetIqmAf(state, true); in SetDVBTStandard()
3599 status = write16(state, IQM_AF_AGC_RF__A, 0); in SetDVBTStandard()
3604 status = write16(state, IQM_AF_INC_LCT__A, 0); /* crunch in IQM_CF */ in SetDVBTStandard()
3607 status = write16(state, IQM_CF_DET_LCT__A, 0); /* detect in IQM_CF */ in SetDVBTStandard()
3610 status = write16(state, IQM_CF_WND_LEN__A, 3); /* peak detector window length */ in SetDVBTStandard()
3614 status = write16(state, IQM_RC_STRETCH__A, 16); in SetDVBTStandard()
3617 status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */ in SetDVBTStandard()
3620 status = write16(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */ in SetDVBTStandard()
3623 status = write16(state, IQM_CF_SCALE__A, 1600); in SetDVBTStandard()
3626 status = write16(state, IQM_CF_SCALE_SH__A, 0); in SetDVBTStandard()
3631 status = write16(state, IQM_AF_CLP_TH__A, 448); in SetDVBTStandard()
3634 status = write16(state, IQM_CF_DATATH__A, 495); /* crunching threshold */ in SetDVBTStandard()
3638 …status = BLChainCmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIME… in SetDVBTStandard()
3642 status = write16(state, IQM_CF_PKDTH__A, 2); /* peak detector threshold */ in SetDVBTStandard()
3645 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2); in SetDVBTStandard()
3649 status = write16(state, IQM_CF_COMM_INT_MSK__A, 1); in SetDVBTStandard()
3652 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE); in SetDVBTStandard()
3657 status = ADCSynchronization(state); in SetDVBTStandard()
3660 status = SetPreSaw(state, &state->m_dvbtPreSawCfg); in SetDVBTStandard()
3665 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); in SetDVBTStandard()
3669 status = SetAgcRf(state, &state->m_dvbtRfAgcCfg, true); in SetDVBTStandard()
3672 status = SetAgcIf(state, &state->m_dvbtIfAgcCfg, true); in SetDVBTStandard()
3677 status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data); in SetDVBTStandard()
3681 status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data); in SetDVBTStandard()
3686 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); in SetDVBTStandard()
3690 if (!state->m_DRXK_A3_ROM_CODE) { in SetDVBTStandard()
3692 …status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, state->m_dvbtIfAgcCfg.FastClipCtrlDela… in SetDVBTStandard()
3699 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1); in SetDVBTStandard()
3702 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2); in SetDVBTStandard()
3708 status = write16(state, FEC_DI_INPUT_CTL__A, 1); /* OFDM input */ in SetDVBTStandard()
3714 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400); in SetDVBTStandard()
3718 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000); in SetDVBTStandard()
3722 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001); in SetDVBTStandard()
3727 status = MPEGTSDtoSetup(state, OM_DVBT); in SetDVBTStandard()
3731 status = DVBTActivatePresets(state); in SetDVBTStandard()
3747 static int DVBTStart(struct drxk_state *state) in DVBTStart() argument
3757 …status = DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0, OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK_… in DVBTStart()
3761 status = MPEGTSStart(state); in DVBTStart()
3764 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE); in DVBTStart()
3782 static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz, in SetDVBT() argument
3795 …status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NUL… in SetDVBT()
3800 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); in SetDVBT()
3805 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP); in SetDVBT()
3808 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP); in SetDVBT()
3814 status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP); in SetDVBT()
3821 switch (state->props.transmission_mode) { in SetDVBT()
3835 switch (state->props.guard_interval) { in SetDVBT()
3855 switch (state->props.hierarchy) { in SetDVBT()
3876 switch (state->props.modulation) { in SetDVBT()
3913 status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI); in SetDVBT()
3919 switch (state->props.code_rate_HP) { in SetDVBT()
3948 switch (state->props.bandwidth_hz) { in SetDVBT()
3950 state->props.bandwidth_hz = 8000000; in SetDVBT()
3954 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3052); in SetDVBT()
3958 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 7); in SetDVBT()
3961 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 7); in SetDVBT()
3964 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 7); in SetDVBT()
3967 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1); in SetDVBT()
3973 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3491); in SetDVBT()
3977 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 8); in SetDVBT()
3980 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 8); in SetDVBT()
3983 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 4); in SetDVBT()
3986 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1); in SetDVBT()
3992 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 4073); in SetDVBT()
3996 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 19); in SetDVBT()
3999 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 19); in SetDVBT()
4002 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 14); in SetDVBT()
4005 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1); in SetDVBT()
4025 ((state->m_sysClockFreq * in SetDVBT()
4038 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRateOfs); in SetDVBT()
4049 status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true); in SetDVBT()
4056 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); in SetDVBT()
4061 status = write16(state, OFDM_SC_COMM_STATE__A, 0); in SetDVBT()
4064 status = write16(state, OFDM_SC_COMM_EXEC__A, 1); in SetDVBT()
4069 …status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NU… in SetDVBT()
4079 status = DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM, in SetDVBT()
4084 if (!state->m_DRXK_A3_ROM_CODE) in SetDVBT()
4085 status = DVBTCtrlSetSqiSpeed(state, &state->m_sqiSpeed); in SetDVBT()
4103 static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus) in GetDVBTLockStatus() argument
4119 status = read16(state, OFDM_SC_COMM_EXEC__A, &ScCommExec); in GetDVBTLockStatus()
4125 status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &ScRaRamLock); in GetDVBTLockStatus()
4144 static int PowerUpQAM(struct drxk_state *state) in PowerUpQAM() argument
4150 status = CtrlPowerMode(state, &powerMode); in PowerUpQAM()
4159 static int PowerDownQAM(struct drxk_state *state) in PowerDownQAM() argument
4166 status = read16(state, SCU_COMM_EXEC__A, &data); in PowerDownQAM()
4175 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP); in PowerDownQAM()
4178 …status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL… in PowerDownQAM()
4183 status = SetIqmAf(state, false); in PowerDownQAM()
4205 static int SetQAMMeasurement(struct drxk_state *state, in SetQAMMeasurement() argument
4266 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fecRsPeriod); in SetQAMMeasurement()
4269 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, fecRsPrescale); in SetQAMMeasurement()
4272 status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fecRsPeriod); in SetQAMMeasurement()
4279 static int SetQAM16(struct drxk_state *state) in SetQAM16() argument
4286 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517); in SetQAM16()
4289 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517); in SetQAM16()
4292 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517); in SetQAM16()
4295 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517); in SetQAM16()
4298 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517); in SetQAM16()
4301 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517); in SetQAM16()
4305 status = write16(state, QAM_DQ_QUAL_FUN0__A, 2); in SetQAM16()
4308 status = write16(state, QAM_DQ_QUAL_FUN1__A, 2); in SetQAM16()
4311 status = write16(state, QAM_DQ_QUAL_FUN2__A, 2); in SetQAM16()
4314 status = write16(state, QAM_DQ_QUAL_FUN3__A, 2); in SetQAM16()
4317 status = write16(state, QAM_DQ_QUAL_FUN4__A, 2); in SetQAM16()
4320 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); in SetQAM16()
4324 status = write16(state, QAM_SY_SYNC_HWM__A, 5); in SetQAM16()
4327 status = write16(state, QAM_SY_SYNC_AWM__A, 4); in SetQAM16()
4330 status = write16(state, QAM_SY_SYNC_LWM__A, 3); in SetQAM16()
4335 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM16); in SetQAM16()
4340 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); in SetQAM16()
4343 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); in SetQAM16()
4346 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); in SetQAM16()
4349 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); in SetQAM16()
4352 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); in SetQAM16()
4355 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); in SetQAM16()
4358 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); in SetQAM16()
4361 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); in SetQAM16()
4365 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); in SetQAM16()
4368 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20); in SetQAM16()
4371 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80); in SetQAM16()
4374 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); in SetQAM16()
4377 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20); in SetQAM16()
4380 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50); in SetQAM16()
4383 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); in SetQAM16()
4386 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16); in SetQAM16()
4389 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32); in SetQAM16()
4392 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); in SetQAM16()
4395 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); in SetQAM16()
4398 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10); in SetQAM16()
4403 /* QAM State Machine (FSM) Thresholds */ in SetQAM16()
4405 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140); in SetQAM16()
4408 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50); in SetQAM16()
4411 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95); in SetQAM16()
4414 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120); in SetQAM16()
4417 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230); in SetQAM16()
4420 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105); in SetQAM16()
4424 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); in SetQAM16()
4427 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); in SetQAM16()
4430 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24); in SetQAM16()
4437 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16); in SetQAM16()
4440 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220); in SetQAM16()
4443 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25); in SetQAM16()
4446 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6); in SetQAM16()
4449 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24); in SetQAM16()
4452 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65); in SetQAM16()
4455 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127); in SetQAM16()
4472 static int SetQAM32(struct drxk_state *state) in SetQAM32() argument
4480 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707); in SetQAM32()
4483 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707); in SetQAM32()
4486 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707); in SetQAM32()
4489 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707); in SetQAM32()
4492 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707); in SetQAM32()
4495 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707); in SetQAM32()
4500 status = write16(state, QAM_DQ_QUAL_FUN0__A, 3); in SetQAM32()
4503 status = write16(state, QAM_DQ_QUAL_FUN1__A, 3); in SetQAM32()
4506 status = write16(state, QAM_DQ_QUAL_FUN2__A, 3); in SetQAM32()
4509 status = write16(state, QAM_DQ_QUAL_FUN3__A, 3); in SetQAM32()
4512 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3); in SetQAM32()
4515 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); in SetQAM32()
4519 status = write16(state, QAM_SY_SYNC_HWM__A, 6); in SetQAM32()
4522 status = write16(state, QAM_SY_SYNC_AWM__A, 5); in SetQAM32()
4525 status = write16(state, QAM_SY_SYNC_LWM__A, 3); in SetQAM32()
4531 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM32); in SetQAM32()
4538 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); in SetQAM32()
4541 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); in SetQAM32()
4544 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); in SetQAM32()
4547 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); in SetQAM32()
4550 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); in SetQAM32()
4553 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); in SetQAM32()
4556 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); in SetQAM32()
4559 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); in SetQAM32()
4563 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); in SetQAM32()
4566 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20); in SetQAM32()
4569 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80); in SetQAM32()
4572 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); in SetQAM32()
4575 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20); in SetQAM32()
4578 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50); in SetQAM32()
4581 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); in SetQAM32()
4584 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16); in SetQAM32()
4587 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16); in SetQAM32()
4590 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); in SetQAM32()
4593 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); in SetQAM32()
4596 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0); in SetQAM32()
4601 /* QAM State Machine (FSM) Thresholds */ in SetQAM32()
4603 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90); in SetQAM32()
4606 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50); in SetQAM32()
4609 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80); in SetQAM32()
4612 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100); in SetQAM32()
4615 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170); in SetQAM32()
4618 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100); in SetQAM32()
4622 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); in SetQAM32()
4625 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); in SetQAM32()
4628 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10); in SetQAM32()
4635 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12); in SetQAM32()
4638 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140); in SetQAM32()
4641 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8); in SetQAM32()
4644 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16); in SetQAM32()
4647 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26); in SetQAM32()
4650 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56); in SetQAM32()
4653 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86); in SetQAM32()
4667 static int SetQAM64(struct drxk_state *state) in SetQAM64() argument
4674 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336); in SetQAM64()
4677 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618); in SetQAM64()
4680 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988); in SetQAM64()
4683 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809); in SetQAM64()
4686 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809); in SetQAM64()
4689 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609); in SetQAM64()
4694 status = write16(state, QAM_DQ_QUAL_FUN0__A, 4); in SetQAM64()
4697 status = write16(state, QAM_DQ_QUAL_FUN1__A, 4); in SetQAM64()
4700 status = write16(state, QAM_DQ_QUAL_FUN2__A, 4); in SetQAM64()
4703 status = write16(state, QAM_DQ_QUAL_FUN3__A, 4); in SetQAM64()
4706 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3); in SetQAM64()
4709 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); in SetQAM64()
4713 status = write16(state, QAM_SY_SYNC_HWM__A, 5); in SetQAM64()
4716 status = write16(state, QAM_SY_SYNC_AWM__A, 4); in SetQAM64()
4719 status = write16(state, QAM_SY_SYNC_LWM__A, 3); in SetQAM64()
4724 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM64); in SetQAM64()
4731 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); in SetQAM64()
4734 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); in SetQAM64()
4737 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); in SetQAM64()
4740 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); in SetQAM64()
4743 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); in SetQAM64()
4746 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); in SetQAM64()
4749 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); in SetQAM64()
4752 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); in SetQAM64()
4756 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); in SetQAM64()
4759 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30); in SetQAM64()
4762 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100); in SetQAM64()
4765 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); in SetQAM64()
4768 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30); in SetQAM64()
4771 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50); in SetQAM64()
4774 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); in SetQAM64()
4777 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25); in SetQAM64()
4780 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48); in SetQAM64()
4783 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); in SetQAM64()
4786 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); in SetQAM64()
4789 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10); in SetQAM64()
4794 /* QAM State Machine (FSM) Thresholds */ in SetQAM64()
4796 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100); in SetQAM64()
4799 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60); in SetQAM64()
4802 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80); in SetQAM64()
4805 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110); in SetQAM64()
4808 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200); in SetQAM64()
4811 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95); in SetQAM64()
4815 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); in SetQAM64()
4818 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); in SetQAM64()
4821 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15); in SetQAM64()
4828 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12); in SetQAM64()
4831 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141); in SetQAM64()
4834 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7); in SetQAM64()
4837 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0); in SetQAM64()
4840 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15); in SetQAM64()
4843 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45); in SetQAM64()
4846 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80); in SetQAM64()
4861 static int SetQAM128(struct drxk_state *state) in SetQAM128() argument
4868 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564); in SetQAM128()
4871 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598); in SetQAM128()
4874 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394); in SetQAM128()
4877 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409); in SetQAM128()
4880 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656); in SetQAM128()
4883 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238); in SetQAM128()
4888 status = write16(state, QAM_DQ_QUAL_FUN0__A, 6); in SetQAM128()
4891 status = write16(state, QAM_DQ_QUAL_FUN1__A, 6); in SetQAM128()
4894 status = write16(state, QAM_DQ_QUAL_FUN2__A, 6); in SetQAM128()
4897 status = write16(state, QAM_DQ_QUAL_FUN3__A, 6); in SetQAM128()
4900 status = write16(state, QAM_DQ_QUAL_FUN4__A, 5); in SetQAM128()
4903 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); in SetQAM128()
4907 status = write16(state, QAM_SY_SYNC_HWM__A, 6); in SetQAM128()
4910 status = write16(state, QAM_SY_SYNC_AWM__A, 5); in SetQAM128()
4913 status = write16(state, QAM_SY_SYNC_LWM__A, 3); in SetQAM128()
4920 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM128); in SetQAM128()
4927 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); in SetQAM128()
4930 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); in SetQAM128()
4933 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); in SetQAM128()
4936 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); in SetQAM128()
4939 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); in SetQAM128()
4942 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); in SetQAM128()
4945 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); in SetQAM128()
4948 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); in SetQAM128()
4952 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); in SetQAM128()
4955 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40); in SetQAM128()
4958 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120); in SetQAM128()
4961 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); in SetQAM128()
4964 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40); in SetQAM128()
4967 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60); in SetQAM128()
4970 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); in SetQAM128()
4973 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25); in SetQAM128()
4976 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64); in SetQAM128()
4979 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); in SetQAM128()
4982 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); in SetQAM128()
4985 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0); in SetQAM128()
4990 /* QAM State Machine (FSM) Thresholds */ in SetQAM128()
4992 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50); in SetQAM128()
4995 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60); in SetQAM128()
4998 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80); in SetQAM128()
5001 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100); in SetQAM128()
5004 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140); in SetQAM128()
5007 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100); in SetQAM128()
5011 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); in SetQAM128()
5014 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5); in SetQAM128()
5018 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12); in SetQAM128()
5024 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8); in SetQAM128()
5027 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65); in SetQAM128()
5030 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5); in SetQAM128()
5033 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3); in SetQAM128()
5036 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1); in SetQAM128()
5039 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12); in SetQAM128()
5042 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23); in SetQAM128()
5057 static int SetQAM256(struct drxk_state *state) in SetQAM256() argument
5064 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502); in SetQAM256()
5067 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084); in SetQAM256()
5070 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543); in SetQAM256()
5073 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931); in SetQAM256()
5076 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629); in SetQAM256()
5079 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385); in SetQAM256()
5084 status = write16(state, QAM_DQ_QUAL_FUN0__A, 8); in SetQAM256()
5087 status = write16(state, QAM_DQ_QUAL_FUN1__A, 8); in SetQAM256()
5090 status = write16(state, QAM_DQ_QUAL_FUN2__A, 8); in SetQAM256()
5093 status = write16(state, QAM_DQ_QUAL_FUN3__A, 8); in SetQAM256()
5096 status = write16(state, QAM_DQ_QUAL_FUN4__A, 6); in SetQAM256()
5099 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); in SetQAM256()
5103 status = write16(state, QAM_SY_SYNC_HWM__A, 5); in SetQAM256()
5106 status = write16(state, QAM_SY_SYNC_AWM__A, 4); in SetQAM256()
5109 status = write16(state, QAM_SY_SYNC_LWM__A, 3); in SetQAM256()
5115 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM256); in SetQAM256()
5122 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); in SetQAM256()
5125 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); in SetQAM256()
5128 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); in SetQAM256()
5131 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); in SetQAM256()
5134 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); in SetQAM256()
5137 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); in SetQAM256()
5140 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); in SetQAM256()
5143 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); in SetQAM256()
5147 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); in SetQAM256()
5150 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50); in SetQAM256()
5153 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250); in SetQAM256()
5156 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); in SetQAM256()
5159 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50); in SetQAM256()
5162 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125); in SetQAM256()
5165 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); in SetQAM256()
5168 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25); in SetQAM256()
5171 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48); in SetQAM256()
5174 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); in SetQAM256()
5177 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); in SetQAM256()
5180 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10); in SetQAM256()
5185 /* QAM State Machine (FSM) Thresholds */ in SetQAM256()
5187 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50); in SetQAM256()
5190 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60); in SetQAM256()
5193 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80); in SetQAM256()
5196 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100); in SetQAM256()
5199 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150); in SetQAM256()
5202 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110); in SetQAM256()
5206 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); in SetQAM256()
5209 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); in SetQAM256()
5212 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12); in SetQAM256()
5219 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8); in SetQAM256()
5222 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74); in SetQAM256()
5225 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18); in SetQAM256()
5228 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13); in SetQAM256()
5231 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7); in SetQAM256()
5234 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0); in SetQAM256()
5237 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8); in SetQAM256()
5252 static int QAMResetQAM(struct drxk_state *state) in QAMResetQAM() argument
5259 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP); in QAMResetQAM()
5263 …status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NUL… in QAMResetQAM()
5278 static int QAMSetSymbolrate(struct drxk_state *state) in QAMSetSymbolrate() argument
5289 adcFrequency = (state->m_sysClockFreq * 1000) / 3; in QAMSetSymbolrate()
5291 /* printk(KERN_DEBUG "drxk: SR %d\n", state->props.symbol_rate); */ in QAMSetSymbolrate()
5292 if (state->props.symbol_rate <= 1188750) in QAMSetSymbolrate()
5294 else if (state->props.symbol_rate <= 2377500) in QAMSetSymbolrate()
5296 else if (state->props.symbol_rate <= 4755000) in QAMSetSymbolrate()
5298 status = write16(state, IQM_FD_RATESEL__A, ratesel); in QAMSetSymbolrate()
5305 symbFreq = state->props.symbol_rate * (1 << ratesel); in QAMSetSymbolrate()
5314 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRate); in QAMSetSymbolrate()
5317 state->m_iqmRcRate = iqmRcRate; in QAMSetSymbolrate()
5321 symbFreq = state->props.symbol_rate; in QAMSetSymbolrate()
5332 status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lcSymbRate); in QAMSetSymbolrate()
5349 static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus) in GetQAMLockStatus() argument
5356 status = scu_command(state, in GetQAMLockStatus()
5388 static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz, in SetQAM() argument
5402 status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP); in SetQAM()
5405 status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP); in SetQAM()
5408 status = QAMResetQAM(state); in SetQAM()
5417 status = QAMSetSymbolrate(state); in SetQAM()
5422 switch (state->props.modulation) { in SetQAM()
5424 state->m_Constellation = DRX_CONSTELLATION_QAM256; in SetQAM()
5428 state->m_Constellation = DRX_CONSTELLATION_QAM64; in SetQAM()
5431 state->m_Constellation = DRX_CONSTELLATION_QAM16; in SetQAM()
5434 state->m_Constellation = DRX_CONSTELLATION_QAM32; in SetQAM()
5437 state->m_Constellation = DRX_CONSTELLATION_QAM128; in SetQAM()
5445 setParamParameters[0] = state->m_Constellation; /* modulation */ in SetQAM()
5447 if (state->m_OperationMode == OM_QAM_ITU_C) in SetQAM()
5456 …status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, 4,… in SetQAM()
5459 if (state->m_OperationMode == OM_QAM_ITU_C) in SetQAM()
5463 …status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 1, s… in SetQAM()
5467 setParamParameters[0] = state->m_Constellation; /* modulation */ in SetQAM()
5469 …status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, 2,… in SetQAM()
5483 status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true); in SetQAM()
5488 status = SetQAMMeasurement(state, state->m_Constellation, state->props.symbol_rate); in SetQAM()
5493 status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE); in SetQAM()
5496 status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE); in SetQAM()
5501 status = write16(state, QAM_LC_RATE_LIMIT__A, 3); in SetQAM()
5504 status = write16(state, QAM_LC_LPF_FACTORP__A, 4); in SetQAM()
5507 status = write16(state, QAM_LC_LPF_FACTORI__A, 4); in SetQAM()
5510 status = write16(state, QAM_LC_MODE__A, 7); in SetQAM()
5514 status = write16(state, QAM_LC_QUAL_TAB0__A, 1); in SetQAM()
5517 status = write16(state, QAM_LC_QUAL_TAB1__A, 1); in SetQAM()
5520 status = write16(state, QAM_LC_QUAL_TAB2__A, 1); in SetQAM()
5523 status = write16(state, QAM_LC_QUAL_TAB3__A, 1); in SetQAM()
5526 status = write16(state, QAM_LC_QUAL_TAB4__A, 2); in SetQAM()
5529 status = write16(state, QAM_LC_QUAL_TAB5__A, 2); in SetQAM()
5532 status = write16(state, QAM_LC_QUAL_TAB6__A, 2); in SetQAM()
5535 status = write16(state, QAM_LC_QUAL_TAB8__A, 2); in SetQAM()
5538 status = write16(state, QAM_LC_QUAL_TAB9__A, 2); in SetQAM()
5541 status = write16(state, QAM_LC_QUAL_TAB10__A, 2); in SetQAM()
5544 status = write16(state, QAM_LC_QUAL_TAB12__A, 2); in SetQAM()
5547 status = write16(state, QAM_LC_QUAL_TAB15__A, 3); in SetQAM()
5550 status = write16(state, QAM_LC_QUAL_TAB16__A, 3); in SetQAM()
5553 status = write16(state, QAM_LC_QUAL_TAB20__A, 4); in SetQAM()
5556 status = write16(state, QAM_LC_QUAL_TAB25__A, 4); in SetQAM()
5561 status = write16(state, QAM_SY_SP_INV__A, QAM_SY_SP_INV_SPECTRUM_INV_DIS); in SetQAM()
5566 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); in SetQAM()
5571 switch (state->props.modulation) { in SetQAM()
5573 status = SetQAM16(state); in SetQAM()
5576 status = SetQAM32(state); in SetQAM()
5580 status = SetQAM64(state); in SetQAM()
5583 status = SetQAM128(state); in SetQAM()
5586 status = SetQAM256(state); in SetQAM()
5596 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); in SetQAM()
5603 status = MPEGTSDtoSetup(state, state->m_OperationMode); in SetQAM()
5608 status = MPEGTSStart(state); in SetQAM()
5611 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE); in SetQAM()
5614 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE); in SetQAM()
5617 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE); in SetQAM()
5622 …status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NUL… in SetQAM()
5635 static int SetQAMStandard(struct drxk_state *state, in SetQAMStandard() argument
5648 SwitchAntennaToQAM(state); in SetQAMStandard()
5651 status = PowerUpQAM(state); in SetQAMStandard()
5655 status = QAMResetQAM(state); in SetQAMStandard()
5661 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP); in SetQAMStandard()
5664 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC); in SetQAMStandard()
5672 …status = BLChainCmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIM… in SetQAMStandard()
5675 …status = BLDirectCmd(state, IQM_CF_TAP_RE0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENT… in SetQAMStandard()
5678 …status = BLDirectCmd(state, IQM_CF_TAP_IM0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENT… in SetQAMStandard()
5686 status = write16(state, IQM_CF_OUT_ENA__A, (1 << IQM_CF_OUT_ENA_QAM__B)); in SetQAMStandard()
5689 status = write16(state, IQM_CF_SYMMETRIC__A, 0); in SetQAMStandard()
5692 …status = write16(state, IQM_CF_MIDTAP__A, ((1 << IQM_CF_MIDTAP_RE__B) | (1 << IQM_CF_MIDTAP_IM__B)… in SetQAMStandard()
5696 status = write16(state, IQM_RC_STRETCH__A, 21); in SetQAMStandard()
5699 status = write16(state, IQM_AF_CLP_LEN__A, 0); in SetQAMStandard()
5702 status = write16(state, IQM_AF_CLP_TH__A, 448); in SetQAMStandard()
5705 status = write16(state, IQM_AF_SNS_LEN__A, 0); in SetQAMStandard()
5708 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0); in SetQAMStandard()
5712 status = write16(state, IQM_FS_ADJ_SEL__A, 1); in SetQAMStandard()
5715 status = write16(state, IQM_RC_ADJ_SEL__A, 1); in SetQAMStandard()
5718 status = write16(state, IQM_CF_ADJ_SEL__A, 1); in SetQAMStandard()
5721 status = write16(state, IQM_AF_UPD_SEL__A, 0); in SetQAMStandard()
5726 status = write16(state, IQM_CF_CLP_VAL__A, 500); in SetQAMStandard()
5729 status = write16(state, IQM_CF_DATATH__A, 1000); in SetQAMStandard()
5732 status = write16(state, IQM_CF_BYPASSDET__A, 1); in SetQAMStandard()
5735 status = write16(state, IQM_CF_DET_LCT__A, 0); in SetQAMStandard()
5738 status = write16(state, IQM_CF_WND_LEN__A, 1); in SetQAMStandard()
5741 status = write16(state, IQM_CF_PKDTH__A, 1); in SetQAMStandard()
5744 status = write16(state, IQM_AF_INC_BYPASS__A, 1); in SetQAMStandard()
5749 status = SetIqmAf(state, true); in SetQAMStandard()
5752 status = write16(state, IQM_AF_START_LOCK__A, 0x01); in SetQAMStandard()
5757 status = ADCSynchronization(state); in SetQAMStandard()
5762 status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000); in SetQAMStandard()
5767 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); in SetQAMStandard()
5774 status = InitAGC(state, true); in SetQAMStandard()
5777 status = SetPreSaw(state, &(state->m_qamPreSawCfg)); in SetQAMStandard()
5782 status = SetAgcRf(state, &(state->m_qamRfAgcCfg), true); in SetQAMStandard()
5785 status = SetAgcIf(state, &(state->m_qamIfAgcCfg), true); in SetQAMStandard()
5790 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); in SetQAMStandard()
5797 static int WriteGPIO(struct drxk_state *state) in WriteGPIO() argument
5804 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); in WriteGPIO()
5809 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); in WriteGPIO()
5813 if (state->m_hasSAWSW) { in WriteGPIO()
5814 if (state->UIO_mask & 0x0001) { /* UIO-1 */ in WriteGPIO()
5816 status = write16(state, SIO_PDR_SMA_TX_CFG__A, state->m_GPIOCfg); in WriteGPIO()
5821 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value); in WriteGPIO()
5824 if ((state->m_GPIO & 0x0001) == 0) in WriteGPIO()
5829 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value); in WriteGPIO()
5833 if (state->UIO_mask & 0x0002) { /* UIO-2 */ in WriteGPIO()
5835 status = write16(state, SIO_PDR_SMA_TX_CFG__A, state->m_GPIOCfg); in WriteGPIO()
5840 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value); in WriteGPIO()
5843 if ((state->m_GPIO & 0x0002) == 0) in WriteGPIO()
5848 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value); in WriteGPIO()
5852 if (state->UIO_mask & 0x0004) { /* UIO-3 */ in WriteGPIO()
5854 status = write16(state, SIO_PDR_SMA_TX_CFG__A, state->m_GPIOCfg); in WriteGPIO()
5859 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value); in WriteGPIO()
5862 if ((state->m_GPIO & 0x0004) == 0) in WriteGPIO()
5867 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value); in WriteGPIO()
5873 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000); in WriteGPIO()
5880 static int SwitchAntennaToQAM(struct drxk_state *state) in SwitchAntennaToQAM() argument
5887 if (!state->antenna_gpio) in SwitchAntennaToQAM()
5890 gpio_state = state->m_GPIO & state->antenna_gpio; in SwitchAntennaToQAM()
5892 if (state->antenna_dvbt ^ gpio_state) { in SwitchAntennaToQAM()
5894 if (state->antenna_dvbt) in SwitchAntennaToQAM()
5895 state->m_GPIO &= ~state->antenna_gpio; in SwitchAntennaToQAM()
5897 state->m_GPIO |= state->antenna_gpio; in SwitchAntennaToQAM()
5898 status = WriteGPIO(state); in SwitchAntennaToQAM()
5905 static int SwitchAntennaToDVBT(struct drxk_state *state) in SwitchAntennaToDVBT() argument
5912 if (!state->antenna_gpio) in SwitchAntennaToDVBT()
5915 gpio_state = state->m_GPIO & state->antenna_gpio; in SwitchAntennaToDVBT()
5917 if (!(state->antenna_dvbt ^ gpio_state)) { in SwitchAntennaToDVBT()
5919 if (state->antenna_dvbt) in SwitchAntennaToDVBT()
5920 state->m_GPIO |= state->antenna_gpio; in SwitchAntennaToDVBT()
5922 state->m_GPIO &= ~state->antenna_gpio; in SwitchAntennaToDVBT()
5923 status = WriteGPIO(state); in SwitchAntennaToDVBT()
5931 static int PowerDownDevice(struct drxk_state *state) in PowerDownDevice() argument
5942 if (state->m_bPDownOpenBridge) { in PowerDownDevice()
5944 status = ConfigureI2CBridge(state, true); in PowerDownDevice()
5949 status = DVBTEnableOFDMTokenRing(state, false); in PowerDownDevice()
5953 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_CLOCK); in PowerDownDevice()
5956 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); in PowerDownDevice()
5959 state->m_HICfgCtrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; in PowerDownDevice()
5960 status = HI_CfgCommand(state); in PowerDownDevice()
5968 static int load_microcode(struct drxk_state *state, const char *mc_name) in load_microcode() argument
5975 err = request_firmware(&fw, mc_name, state->i2c->dev.parent); in load_microcode()
5983 err = DownloadMicrocode(state, fw->data, fw->size); in load_microcode()
5988 static int init_drxk(struct drxk_state *state) in init_drxk() argument
5995 if ((state->m_DrxkState == DRXK_UNINITIALIZED)) { in init_drxk()
5996 status = PowerUpDevice(state); in init_drxk()
5999 status = DRXX_Open(state); in init_drxk()
6003 …status = write16(state, SIO_CC_SOFT_RST__A, SIO_CC_SOFT_RST_OFDM__M | SIO_CC_SOFT_RST_SYS__M | SIO… in init_drxk()
6006 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); in init_drxk()
6011 state->m_DRXK_A3_PATCH_CODE = true; in init_drxk()
6012 status = GetDeviceCapabilities(state); in init_drxk()
6019 state->m_HICfgBridgeDelay = in init_drxk()
6020 (u16) ((state->m_oscClockFreq / 1000) * in init_drxk()
6023 if (state->m_HICfgBridgeDelay > in init_drxk()
6025 state->m_HICfgBridgeDelay = in init_drxk()
6029 state->m_HICfgBridgeDelay += in init_drxk()
6030 state->m_HICfgBridgeDelay << in init_drxk()
6033 status = InitHI(state); in init_drxk()
6038 if (!(state->m_DRXK_A1_ROM_CODE) in init_drxk()
6039 && !(state->m_DRXK_A2_ROM_CODE)) in init_drxk()
6042 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); in init_drxk()
6048 status = MPEGTSDisable(state); in init_drxk()
6053 status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP); in init_drxk()
6056 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP); in init_drxk()
6061 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_ON); in init_drxk()
6066 status = write16(state, SIO_BL_COMM_EXEC__A, SIO_BL_COMM_EXEC_ACTIVE); in init_drxk()
6069 status = BLChainCmd(state, 0, 6, 100); in init_drxk()
6073 if (!state->microcode_name) in init_drxk()
6074 load_microcode(state, "drxk_a3.mc"); in init_drxk()
6076 load_microcode(state, state->microcode_name); in init_drxk()
6079 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_OFF); in init_drxk()
6084 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); in init_drxk()
6087 status = DRXX_Open(state); in init_drxk()
6094 status = CtrlPowerMode(state, &powerMode); in init_drxk()
6109 status = write16(state, SCU_RAM_DRIVER_VER_HI__A, driverVersion); in init_drxk()
6117 status = write16(state, SCU_RAM_DRIVER_VER_LO__A, driverVersion); in init_drxk()
6133 status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0); in init_drxk()
6139 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP); in init_drxk()
6143 status = MPEGTSDtoInit(state); in init_drxk()
6146 status = MPEGTSStop(state); in init_drxk()
6149 status = MPEGTSConfigurePolarity(state); in init_drxk()
6152 status = MPEGTSConfigurePins(state, state->m_enableMPEGOutput); in init_drxk()
6156 status = WriteGPIO(state); in init_drxk()
6160 state->m_DrxkState = DRXK_STOPPED; in init_drxk()
6162 if (state->m_bPowerDown) { in init_drxk()
6163 status = PowerDownDevice(state); in init_drxk()
6166 state->m_DrxkState = DRXK_POWERED_DOWN; in init_drxk()
6168 state->m_DrxkState = DRXK_STOPPED; in init_drxk()
6179 struct drxk_state *state = fe->demodulator_priv; in drxk_release() local
6182 kfree(state); in drxk_release()
6187 struct drxk_state *state = fe->demodulator_priv; in drxk_sleep() local
6190 ShutDown(state); in drxk_sleep()
6196 struct drxk_state *state = fe->demodulator_priv; in drxk_gate_ctrl() local
6199 return ConfigureI2CBridge(state, enable ? true : false); in drxk_gate_ctrl()
6206 struct drxk_state *state = fe->demodulator_priv; in drxk_set_parameters() local
6224 old_delsys = state->props.delivery_system; in drxk_set_parameters()
6225 state->props = *p; in drxk_set_parameters()
6228 ShutDown(state); in drxk_set_parameters()
6232 if (!state->m_hasDVBC) in drxk_set_parameters()
6234 state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ? true : false; in drxk_set_parameters()
6235 if (state->m_itut_annex_c) in drxk_set_parameters()
6236 SetOperationMode(state, OM_QAM_ITU_C); in drxk_set_parameters()
6238 SetOperationMode(state, OM_QAM_ITU_A); in drxk_set_parameters()
6241 if (!state->m_hasDVBT) in drxk_set_parameters()
6243 SetOperationMode(state, OM_DVBT); in drxk_set_parameters()
6251 Start(state, 0, IF); in drxk_set_parameters()
6260 struct drxk_state *state = fe->demodulator_priv; in drxk_read_status() local
6265 GetLockStatus(state, &stat, 0); in drxk_read_status()
6286 struct drxk_state *state = fe->demodulator_priv; in drxk_read_signal_strength() local
6290 ReadIFAgc(state, &val); in drxk_read_signal_strength()
6297 struct drxk_state *state = fe->demodulator_priv; in drxk_read_snr() local
6301 GetSignalToNoise(state, &snr2); in drxk_read_snr()
6308 struct drxk_state *state = fe->demodulator_priv; in drxk_read_ucblocks() local
6312 DVBTQAMGetAccPktErr(state, &err); in drxk_read_ucblocks()
6378 struct drxk_state *state = NULL; in drxk_attach() local
6382 state = kzalloc(sizeof(struct drxk_state), GFP_KERNEL); in drxk_attach()
6383 if (!state) in drxk_attach()
6386 state->i2c = i2c; in drxk_attach()
6387 state->demod_address = adr; in drxk_attach()
6388 state->single_master = config->single_master; in drxk_attach()
6389 state->microcode_name = config->microcode_name; in drxk_attach()
6390 state->no_i2c_bridge = config->no_i2c_bridge; in drxk_attach()
6391 state->antenna_gpio = config->antenna_gpio; in drxk_attach()
6392 state->antenna_dvbt = config->antenna_dvbt; in drxk_attach()
6393 state->m_ChunkSize = config->chunk_size; in drxk_attach()
6396 state->m_enableParallel = true; in drxk_attach()
6398 state->m_enableParallel = false; in drxk_attach()
6401 state->UIO_mask = config->antenna_gpio; in drxk_attach()
6404 if (!state->antenna_dvbt && state->antenna_gpio) in drxk_attach()
6405 state->m_GPIO |= state->antenna_gpio; in drxk_attach()
6407 state->m_GPIO &= ~state->antenna_gpio; in drxk_attach()
6409 mutex_init(&state->mutex); in drxk_attach()
6411 memcpy(&state->frontend.ops, &drxk_ops, sizeof(drxk_ops)); in drxk_attach()
6412 state->frontend.demodulator_priv = state; in drxk_attach()
6414 init_state(state); in drxk_attach()
6415 if (init_drxk(state) < 0) in drxk_attach()
6420 if (state->m_hasDVBC) { in drxk_attach()
6421 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_A; in drxk_attach()
6422 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_C; in drxk_attach()
6423 strlcat(state->frontend.ops.info.name, " DVB-C", in drxk_attach()
6424 sizeof(state->frontend.ops.info.name)); in drxk_attach()
6426 if (state->m_hasDVBT) { in drxk_attach()
6427 state->frontend.ops.delsys[n++] = SYS_DVBT; in drxk_attach()
6428 strlcat(state->frontend.ops.info.name, " DVB-T", in drxk_attach()
6429 sizeof(state->frontend.ops.info.name)); in drxk_attach()
6433 return &state->frontend; in drxk_attach()
6437 kfree(state); in drxk_attach()