Lines Matching full:state
121 static u16 dib8000_read_word(struct dib8000_state *state, u16 reg) in dib8000_read_word() argument
125 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { in dib8000_read_word()
130 state->i2c_write_buffer[0] = reg >> 8; in dib8000_read_word()
131 state->i2c_write_buffer[1] = reg & 0xff; in dib8000_read_word()
133 memset(state->msg, 0, 2 * sizeof(struct i2c_msg)); in dib8000_read_word()
134 state->msg[0].addr = state->i2c.addr >> 1; in dib8000_read_word()
135 state->msg[0].flags = 0; in dib8000_read_word()
136 state->msg[0].buf = state->i2c_write_buffer; in dib8000_read_word()
137 state->msg[0].len = 2; in dib8000_read_word()
138 state->msg[1].addr = state->i2c.addr >> 1; in dib8000_read_word()
139 state->msg[1].flags = I2C_M_RD; in dib8000_read_word()
140 state->msg[1].buf = state->i2c_read_buffer; in dib8000_read_word()
141 state->msg[1].len = 2; in dib8000_read_word()
143 if (i2c_transfer(state->i2c.adap, state->msg, 2) != 2) in dib8000_read_word()
146 ret = (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1]; in dib8000_read_word()
147 mutex_unlock(&state->i2c_buffer_lock); in dib8000_read_word()
152 static u32 dib8000_read32(struct dib8000_state *state, u16 reg) in dib8000_read32() argument
156 rw[0] = dib8000_read_word(state, reg + 0); in dib8000_read32()
157 rw[1] = dib8000_read_word(state, reg + 1); in dib8000_read32()
184 static int dib8000_write_word(struct dib8000_state *state, u16 reg, u16 val) in dib8000_write_word() argument
188 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { in dib8000_write_word()
193 state->i2c_write_buffer[0] = (reg >> 8) & 0xff; in dib8000_write_word()
194 state->i2c_write_buffer[1] = reg & 0xff; in dib8000_write_word()
195 state->i2c_write_buffer[2] = (val >> 8) & 0xff; in dib8000_write_word()
196 state->i2c_write_buffer[3] = val & 0xff; in dib8000_write_word()
198 memset(&state->msg[0], 0, sizeof(struct i2c_msg)); in dib8000_write_word()
199 state->msg[0].addr = state->i2c.addr >> 1; in dib8000_write_word()
200 state->msg[0].flags = 0; in dib8000_write_word()
201 state->msg[0].buf = state->i2c_write_buffer; in dib8000_write_word()
202 state->msg[0].len = 4; in dib8000_write_word()
204 ret = (i2c_transfer(state->i2c.adap, state->msg, 1) != 1 ? in dib8000_write_word()
206 mutex_unlock(&state->i2c_buffer_lock); in dib8000_write_word()
312 static u16 fft_to_mode(struct dib8000_state *state) in fft_to_mode() argument
315 switch (state->fe[0]->dtv_property_cache.transmission_mode) { in fft_to_mode()
331 static void dib8000_set_acquisition_mode(struct dib8000_state *state) in dib8000_set_acquisition_mode() argument
333 u16 nud = dib8000_read_word(state, 298); in dib8000_set_acquisition_mode()
336 dib8000_write_word(state, 298, nud); in dib8000_set_acquisition_mode()
340 struct dib8000_state *state = fe->demodulator_priv; in dib8000_set_output_mode() local
346 smo_mode = (dib8000_read_word(state, 299) & 0x0050) | (1 << 1); in dib8000_set_output_mode()
349 &state->fe[0], mode); in dib8000_set_output_mode()
362 if (state->cfg.hostbus_diversity) { in dib8000_set_output_mode()
379 dib8000_set_acquisition_mode(state); in dib8000_set_output_mode()
384 &state->fe[0]); in dib8000_set_output_mode()
388 if (state->cfg.output_mpeg2_in_188_bytes) in dib8000_set_output_mode()
391 dib8000_write_word(state, 299, smo_mode); in dib8000_set_output_mode()
392 dib8000_write_word(state, 300, fifo_threshold); /* synchronous fread */ in dib8000_set_output_mode()
393 dib8000_write_word(state, 1286, outreg); in dib8000_set_output_mode()
394 dib8000_write_word(state, 1291, sram); in dib8000_set_output_mode()
401 struct dib8000_state *state = fe->demodulator_priv; in dib8000_set_diversity_in() local
402 u16 sync_wait = dib8000_read_word(state, 273) & 0xfff0; in dib8000_set_diversity_in()
404 if (!state->differential_constellation) { in dib8000_set_diversity_in()
405 dib8000_write_word(state, 272, 1 << 9); //dvsy_off_lmod4 = 1 in dib8000_set_diversity_in()
406 dib8000_write_word(state, 273, sync_wait | (1 << 2) | 2); // sync_enable = 1; comb_mode = 2 in dib8000_set_diversity_in()
408 dib8000_write_word(state, 272, 0); //dvsy_off_lmod4 = 0 in dib8000_set_diversity_in()
409 dib8000_write_word(state, 273, sync_wait); // sync_enable = 0; comb_mode = 0 in dib8000_set_diversity_in()
411 state->diversity_onoff = onoff; in dib8000_set_diversity_in()
415 dib8000_write_word(state, 270, 1); in dib8000_set_diversity_in()
416 dib8000_write_word(state, 271, 0); in dib8000_set_diversity_in()
419 dib8000_write_word(state, 270, 6); in dib8000_set_diversity_in()
420 dib8000_write_word(state, 271, 6); in dib8000_set_diversity_in()
423 dib8000_write_word(state, 270, 0); in dib8000_set_diversity_in()
424 dib8000_write_word(state, 271, 1); in dib8000_set_diversity_in()
430 static void dib8000_set_power_mode(struct dib8000_state *state, enum dib8000_power_mode mode) in dib8000_set_power_mode() argument
434 reg_900 = (dib8000_read_word(state, 900) & 0xfffc) | 0x3, in dib8000_set_power_mode()
437 if (state->revision != 0x8090) in dib8000_set_power_mode()
438 reg_1280 = (dib8000_read_word(state, 1280) & 0x00ff) | 0xff00; in dib8000_set_power_mode()
440 reg_1280 = (dib8000_read_word(state, 1280) & 0x707f) | 0x8f80; in dib8000_set_power_mode()
450 if (state->revision != 0x8090) in dib8000_set_power_mode()
456 if (state->revision != 0x8090) in dib8000_set_power_mode()
464 dib8000_write_word(state, 774, reg_774); in dib8000_set_power_mode()
465 dib8000_write_word(state, 775, reg_775); in dib8000_set_power_mode()
466 dib8000_write_word(state, 776, reg_776); in dib8000_set_power_mode()
467 dib8000_write_word(state, 900, reg_900); in dib8000_set_power_mode()
468 dib8000_write_word(state, 1280, reg_1280); in dib8000_set_power_mode()
471 static int dib8000_init_sdram(struct dib8000_state *state) in dib8000_init_sdram() argument
476 reg = dib8000_read_word(state, 274)&0xfff0; in dib8000_init_sdram()
478 dib8000_write_word(state, 274, reg | 0x7); in dib8000_init_sdram()
480 dib8000_write_word(state, 1803, (7<<2)); in dib8000_init_sdram()
482 reg = dib8000_read_word(state, 1280); in dib8000_init_sdram()
484 dib8000_write_word(state, 1280, reg | (1<<2)); in dib8000_init_sdram()
487 dib8000_write_word(state, 1280, reg); in dib8000_init_sdram()
492 static int dib8000_set_adc_state(struct dib8000_state *state, enum dibx000_adc_states no) in dib8000_set_adc_state() argument
495 u16 reg, reg_907 = dib8000_read_word(state, 907); in dib8000_set_adc_state()
496 u16 reg_908 = dib8000_read_word(state, 908); in dib8000_set_adc_state()
500 if (state->revision != 0x8090) { in dib8000_set_adc_state()
502 ret |= dib8000_write_word(state, 908, reg_908); in dib8000_set_adc_state()
505 reg = dib8000_read_word(state, 1925); in dib8000_set_adc_state()
507 dib8000_write_word(state, 1925, reg | in dib8000_set_adc_state()
511 reg = dib8000_read_word(state, 1925); in dib8000_set_adc_state()
514 dib8000_write_word(state, 1925, reg & ~(1<<4)); in dib8000_set_adc_state()
516 reg = dib8000_read_word(state, 921) & ~((0x3 << 14) in dib8000_set_adc_state()
520 dib8000_write_word(state, 921, reg | (1 << 14) in dib8000_set_adc_state()
526 if (state->revision == 0x8090) { in dib8000_set_adc_state()
527 reg = dib8000_read_word(state, 1925); in dib8000_set_adc_state()
529 dib8000_write_word(state, 1925, in dib8000_set_adc_state()
557 ret |= dib8000_write_word(state, 907, reg_907); in dib8000_set_adc_state()
558 ret |= dib8000_write_word(state, 908, reg_908); in dib8000_set_adc_state()
565 struct dib8000_state *state = fe->demodulator_priv; in dib8000_set_bandwidth() local
571 if (state->timf == 0) { in dib8000_set_bandwidth()
573 timf = state->timf_default; in dib8000_set_bandwidth()
576 timf = state->timf; in dib8000_set_bandwidth()
579 dib8000_write_word(state, 29, (u16) ((timf >> 16) & 0xffff)); in dib8000_set_bandwidth()
580 dib8000_write_word(state, 30, (u16) ((timf) & 0xffff)); in dib8000_set_bandwidth()
585 static int dib8000_sad_calib(struct dib8000_state *state) in dib8000_sad_calib() argument
587 if (state->revision == 0x8090) { in dib8000_sad_calib()
593 dib8000_write_word(state, 923, (0 << 1) | (0 << 0)); in dib8000_sad_calib()
594 dib8000_write_word(state, 924, 776); // 0.625*3.3 / 4096 in dib8000_sad_calib()
597 dib8000_write_word(state, 923, (1 << 0)); in dib8000_sad_calib()
598 dib8000_write_word(state, 923, (0 << 0)); in dib8000_sad_calib()
606 struct dib8000_state *state = fe->demodulator_priv; in dib8000_set_wbd_ref() local
609 state->wbd_ref = value; in dib8000_set_wbd_ref()
610 return dib8000_write_word(state, 106, value); in dib8000_set_wbd_ref()
614 static void dib8000_reset_pll_common(struct dib8000_state *state, const struct dibx000_bandwidth_co… in dib8000_reset_pll_common() argument
617 if (state->revision != 0x8090) { in dib8000_reset_pll_common()
618 dib8000_write_word(state, 23, in dib8000_reset_pll_common()
620 dib8000_write_word(state, 24, in dib8000_reset_pll_common()
623 dib8000_write_word(state, 23, (u16) (((bw->internal / 2 * 1000) >> 16) & 0xffff)); in dib8000_reset_pll_common()
624 dib8000_write_word(state, 24, in dib8000_reset_pll_common()
627 dib8000_write_word(state, 27, (u16) ((bw->ifreq >> 16) & 0x01ff)); in dib8000_reset_pll_common()
628 dib8000_write_word(state, 28, (u16) (bw->ifreq & 0xffff)); in dib8000_reset_pll_common()
629 dib8000_write_word(state, 26, (u16) ((bw->ifreq >> 25) & 0x0003)); in dib8000_reset_pll_common()
631 if (state->revision != 0x8090) in dib8000_reset_pll_common()
632 dib8000_write_word(state, 922, bw->sad_cfg); in dib8000_reset_pll_common()
635 static void dib8000_reset_pll(struct dib8000_state *state) in dib8000_reset_pll() argument
637 const struct dibx000_bandwidth_config *pll = state->cfg.pll; in dib8000_reset_pll()
640 if (state->revision != 0x8090) { in dib8000_reset_pll()
641 dib8000_write_word(state, 901, in dib8000_reset_pll()
649 dib8000_write_word(state, 902, clk_cfg1); in dib8000_reset_pll()
651 dib8000_write_word(state, 902, clk_cfg1); in dib8000_reset_pll()
656 if (state->cfg.pll->ADClkSrc == 0) in dib8000_reset_pll()
657 dib8000_write_word(state, 904, in dib8000_reset_pll()
661 else if (state->cfg.refclksel != 0) in dib8000_reset_pll()
662 dib8000_write_word(state, 904, (0 << 15) | (1 << 12) | in dib8000_reset_pll()
663 ((state->cfg.refclksel & 0x3) << 10) | in dib8000_reset_pll()
667 dib8000_write_word(state, 904, (0 << 15) | (1 << 12) | in dib8000_reset_pll()
671 dib8000_write_word(state, 1856, (!pll->pll_reset<<13) | in dib8000_reset_pll()
675 reg = dib8000_read_word(state, 1857); in dib8000_reset_pll()
676 dib8000_write_word(state, 1857, reg|(!pll->pll_bypass<<15)); in dib8000_reset_pll()
678 reg = dib8000_read_word(state, 1858); /* Force clk out pll /2 */ in dib8000_reset_pll()
679 dib8000_write_word(state, 1858, reg | 1); in dib8000_reset_pll()
681 dib8000_write_word(state, 904, (pll->modulo << 8)); in dib8000_reset_pll()
684 dib8000_reset_pll_common(state, pll); in dib8000_reset_pll()
690 struct dib8000_state *state = fe->demodulator_priv; in dib8000_update_pll() local
691 u16 reg_1857, reg_1856 = dib8000_read_word(state, 1856); in dib8000_update_pll()
703 reg_1857 = dib8000_read_word(state, 1857); in dib8000_update_pll()
705 dib8000_write_word(state, 1857, reg_1857 & ~(1 << 15)); in dib8000_update_pll()
707 dib8000_write_word(state, 1856, reg_1856 | in dib8000_update_pll()
712 internal = dib8000_read32(state, 23) / 1000; in dib8000_update_pll()
719 dib8000_write_word(state, 23, in dib8000_update_pll()
721 dib8000_write_word(state, 24, (u16) ((internal / 2) & 0xffff)); in dib8000_update_pll()
723 dib8000_write_word(state, 1857, reg_1857 | (1 << 15)); in dib8000_update_pll()
725 while (((dib8000_read_word(state, 1856)>>15)&0x1) != 1) in dib8000_update_pll()
729 reg_1856 = dib8000_read_word(state, 1856); in dib8000_update_pll()
773 struct dib8000_state *state = fe->demodulator_priv; in dib8000_set_gpio() local
774 return dib8000_cfg_gpio(state, num, dir, val); in dib8000_set_gpio()
914 struct dib8000_state *state = fe->demodulator_priv; in dib8000_reset() local
916 if ((state->revision = dib8000_identify(&state->i2c)) == 0) in dib8000_reset()
920 if (state->revision != 0x8090) in dib8000_reset()
921 dib8000_write_word(state, 1287, 0x0003); in dib8000_reset()
923 if (state->revision == 0x8000) in dib8000_reset()
926 dibx000_reset_i2c_master(&state->i2c_master); in dib8000_reset()
928 dib8000_set_power_mode(state, DIB8000_POWER_ALL); in dib8000_reset()
931 dib8000_set_adc_state(state, DIBX000_VBG_ENABLE); in dib8000_reset()
934 dib8000_write_word(state, 770, 0xffff); in dib8000_reset()
935 dib8000_write_word(state, 771, 0xffff); in dib8000_reset()
936 dib8000_write_word(state, 772, 0xfffc); in dib8000_reset()
937 if (state->revision == 0x8090) in dib8000_reset()
938 dib8000_write_word(state, 1280, 0x0045); in dib8000_reset()
940 dib8000_write_word(state, 1280, 0x004d); in dib8000_reset()
941 dib8000_write_word(state, 1281, 0x000c); in dib8000_reset()
943 dib8000_write_word(state, 770, 0x0000); in dib8000_reset()
944 dib8000_write_word(state, 771, 0x0000); in dib8000_reset()
945 dib8000_write_word(state, 772, 0x0000); in dib8000_reset()
946 dib8000_write_word(state, 898, 0x0004); // sad in dib8000_reset()
947 dib8000_write_word(state, 1280, 0x0000); in dib8000_reset()
948 dib8000_write_word(state, 1281, 0x0000); in dib8000_reset()
951 if (state->revision != 0x8090) { in dib8000_reset()
952 if (state->cfg.drives) in dib8000_reset()
953 dib8000_write_word(state, 906, state->cfg.drives); in dib8000_reset()
957 dib8000_write_word(state, 906, 0x2d98); in dib8000_reset()
961 dib8000_reset_pll(state); in dib8000_reset()
962 if (state->revision != 0x8090) in dib8000_reset()
963 dib8000_write_word(state, 898, 0x0004); in dib8000_reset()
965 if (dib8000_reset_gpio(state) != 0) in dib8000_reset()
968 if ((state->revision != 0x8090) && in dib8000_reset()
972 state->current_agc = NULL; in dib8000_reset()
976 if (state->cfg.pll->ifreq == 0) in dib8000_reset()
977 dib8000_write_word(state, 40, 0x0755); /* P_iqc_corr_inh = 0 enable IQcorr block */ in dib8000_reset()
979 dib8000_write_word(state, 40, 0x1f55); /* P_iqc_corr_inh = 1 disable IQcorr block */ in dib8000_reset()
989 dib8000_write_word(state, r, *n++); in dib8000_reset()
995 if (state->revision != 0x8090) in dib8000_reset()
996 dib8000_write_word(state, 903, (0 << 4) | 2); in dib8000_reset()
997 state->isdbt_cfg_loaded = 0; in dib8000_reset()
1000 if (state->cfg.div_cfg != 0) in dib8000_reset()
1001 dib8000_write_word(state, 903, state->cfg.div_cfg); in dib8000_reset()
1004 dib8000_write_word(state, 1285, dib8000_read_word(state, 1285) & ~(1 << 1)); in dib8000_reset()
1008 dib8000_set_adc_state(state, DIBX000_SLOW_ADC_ON); in dib8000_reset()
1009 if (state->revision != 0x8090) { in dib8000_reset()
1010 dib8000_sad_calib(state); in dib8000_reset()
1011 dib8000_set_adc_state(state, DIBX000_SLOW_ADC_OFF); in dib8000_reset()
1014 dib8000_set_power_mode(state, DIB8000_POWER_INTERFACE_ONLY); in dib8000_reset()
1019 static void dib8000_restart_agc(struct dib8000_state *state) in dib8000_restart_agc() argument
1022 dib8000_write_word(state, 770, 0x0a00); in dib8000_restart_agc()
1023 dib8000_write_word(state, 770, 0x0000); in dib8000_restart_agc()
1026 static int dib8000_update_lna(struct dib8000_state *state) in dib8000_update_lna() argument
1030 if (state->cfg.update_lna) { in dib8000_update_lna()
1032 dyn_gain = dib8000_read_word(state, 390); in dib8000_update_lna()
1034 if (state->cfg.update_lna(state->fe[0], dyn_gain)) { in dib8000_update_lna()
1035 dib8000_restart_agc(state); in dib8000_update_lna()
1042 static int dib8000_set_agc_config(struct dib8000_state *state, u8 band) in dib8000_set_agc_config() argument
1048 if (state->current_band == band && state->current_agc != NULL) in dib8000_set_agc_config()
1050 state->current_band = band; in dib8000_set_agc_config()
1052 for (i = 0; i < state->cfg.agc_config_count; i++) in dib8000_set_agc_config()
1053 if (state->cfg.agc[i].band_caps & band) { in dib8000_set_agc_config()
1054 agc = &state->cfg.agc[i]; in dib8000_set_agc_config()
1063 state->current_agc = agc; in dib8000_set_agc_config()
1066 dib8000_write_word(state, 76, agc->setup); in dib8000_set_agc_config()
1067 dib8000_write_word(state, 77, agc->inv_gain); in dib8000_set_agc_config()
1068 dib8000_write_word(state, 78, agc->time_stabiliz); in dib8000_set_agc_config()
1069 dib8000_write_word(state, 101, (agc->alpha_level << 12) | agc->thlock); in dib8000_set_agc_config()
1072 dib8000_write_word(state, 102, (agc->alpha_mant << 5) | agc->alpha_exp); in dib8000_set_agc_config()
1073 dib8000_write_word(state, 103, (agc->beta_mant << 6) | agc->beta_exp); in dib8000_set_agc_config()
1076 …state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, ag… in dib8000_set_agc_config()
1079 if (state->wbd_ref != 0) in dib8000_set_agc_config()
1080 dib8000_write_word(state, 106, state->wbd_ref); in dib8000_set_agc_config()
1082 dib8000_write_word(state, 106, agc->wbd_ref); in dib8000_set_agc_config()
1084 if (state->revision == 0x8090) { in dib8000_set_agc_config()
1085 reg = dib8000_read_word(state, 922) & (0x3 << 2); in dib8000_set_agc_config()
1086 dib8000_write_word(state, 922, reg | (agc->wbd_sel << 2)); in dib8000_set_agc_config()
1089 dib8000_write_word(state, 107, (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8)); in dib8000_set_agc_config()
1090 dib8000_write_word(state, 108, agc->agc1_max); in dib8000_set_agc_config()
1091 dib8000_write_word(state, 109, agc->agc1_min); in dib8000_set_agc_config()
1092 dib8000_write_word(state, 110, agc->agc2_max); in dib8000_set_agc_config()
1093 dib8000_write_word(state, 111, agc->agc2_min); in dib8000_set_agc_config()
1094 dib8000_write_word(state, 112, (agc->agc1_pt1 << 8) | agc->agc1_pt2); in dib8000_set_agc_config()
1095 dib8000_write_word(state, 113, (agc->agc1_slope1 << 8) | agc->agc1_slope2); in dib8000_set_agc_config()
1096 dib8000_write_word(state, 114, (agc->agc2_pt1 << 8) | agc->agc2_pt2); in dib8000_set_agc_config()
1097 dib8000_write_word(state, 115, (agc->agc2_slope1 << 8) | agc->agc2_slope2); in dib8000_set_agc_config()
1099 dib8000_write_word(state, 75, agc->agc1_pt3); in dib8000_set_agc_config()
1100 if (state->revision != 0x8090) in dib8000_set_agc_config()
1101 dib8000_write_word(state, 923, in dib8000_set_agc_config()
1102 (dib8000_read_word(state, 923) & 0xffe3) | in dib8000_set_agc_config()
1110 struct dib8000_state *state = fe->demodulator_priv; in dib8000_pwm_agc_reset() local
1111 dib8000_set_adc_state(state, DIBX000_ADC_ON); in dib8000_pwm_agc_reset()
1112 …dib8000_set_agc_config(state, (unsigned char)(BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency /… in dib8000_pwm_agc_reset()
1116 static int dib8000_agc_soft_split(struct dib8000_state *state) in dib8000_agc_soft_split() argument
1120 …if (!state->current_agc || !state->current_agc->perform_agc_softsplit || state->current_agc->split… in dib8000_agc_soft_split()
1124 agc = dib8000_read_word(state, 390); in dib8000_agc_soft_split()
1126 if (agc > state->current_agc->split.min_thres) in dib8000_agc_soft_split()
1127 split_offset = state->current_agc->split.min; in dib8000_agc_soft_split()
1128 else if (agc < state->current_agc->split.max_thres) in dib8000_agc_soft_split()
1129 split_offset = state->current_agc->split.max; in dib8000_agc_soft_split()
1131 split_offset = state->current_agc->split.max * in dib8000_agc_soft_split()
1132 (agc - state->current_agc->split.min_thres) / in dib8000_agc_soft_split()
1133 (state->current_agc->split.max_thres - state->current_agc->split.min_thres); in dib8000_agc_soft_split()
1138 dib8000_write_word(state, 107, (dib8000_read_word(state, 107) & 0xff00) | split_offset); in dib8000_agc_soft_split()
1144 struct dib8000_state *state = fe->demodulator_priv; in dib8000_agc_startup() local
1145 enum frontend_tune_state *tune_state = &state->tune_state; in dib8000_agc_startup()
1153 if (state->revision != 0x8090) in dib8000_agc_startup()
1154 dib8000_set_adc_state(state, DIBX000_ADC_ON); in dib8000_agc_startup()
1156 dib8000_set_power_mode(state, DIB8000_POWER_ALL); in dib8000_agc_startup()
1158 reg = dib8000_read_word(state, 1947)&0xff00; in dib8000_agc_startup()
1159 dib8000_write_word(state, 1946, in dib8000_agc_startup()
1162 dib8000_write_word(state, 1947, reg | (1<<14) | in dib8000_agc_startup()
1166 reg = dib8000_read_word(state, 1920); in dib8000_agc_startup()
1167 dib8000_write_word(state, 1920, (reg | 0x3) & in dib8000_agc_startup()
1171 …if (dib8000_set_agc_config(state, (unsigned char)(BAND_OF_FREQUENCY(fe->dtv_property_cache.frequen… in dib8000_agc_startup()
1173 state->status = FE_STATUS_TUNE_FAILED; in dib8000_agc_startup()
1183 if (state->cfg.agc_control) in dib8000_agc_startup()
1184 state->cfg.agc_control(fe, 1); in dib8000_agc_startup()
1186 dib8000_restart_agc(state); in dib8000_agc_startup()
1197 if (dib8000_update_lna(state)) in dib8000_agc_startup()
1205 dib8000_agc_soft_split(state); in dib8000_agc_startup()
1207 if (state->cfg.agc_control) in dib8000_agc_startup()
1208 state->cfg.agc_control(fe, 0); in dib8000_agc_startup()
1213 ret = dib8000_agc_soft_split(state); in dib8000_agc_startup()
1220 static void dib8096p_host_bus_drive(struct dib8000_state *state, u8 drive) in dib8096p_host_bus_drive() argument
1227 reg = dib8000_read_word(state, 1798) & in dib8096p_host_bus_drive()
1230 dib8000_write_word(state, 1798, reg); in dib8096p_host_bus_drive()
1233 reg = dib8000_read_word(state, 1799) & ~((0x7 << 2) | (0x7 << 8)); in dib8096p_host_bus_drive()
1235 dib8000_write_word(state, 1799, reg); in dib8096p_host_bus_drive()
1238 reg = dib8000_read_word(state, 1800) & in dib8096p_host_bus_drive()
1241 dib8000_write_word(state, 1800, reg); in dib8096p_host_bus_drive()
1244 reg = dib8000_read_word(state, 1801) & ~((0x7 << 2) | (0x7 << 8)); in dib8096p_host_bus_drive()
1246 dib8000_write_word(state, 1801, reg); in dib8096p_host_bus_drive()
1249 reg = dib8000_read_word(state, 1802) & in dib8096p_host_bus_drive()
1252 dib8000_write_word(state, 1802, reg); in dib8096p_host_bus_drive()
1274 static void dib8096p_cfg_DibTx(struct dib8000_state *state, u32 P_Kin, in dib8096p_cfg_DibTx() argument
1280 dib8000_write_word(state, 1615, 1); in dib8096p_cfg_DibTx()
1281 dib8000_write_word(state, 1603, P_Kin); in dib8096p_cfg_DibTx()
1282 dib8000_write_word(state, 1605, P_Kout); in dib8096p_cfg_DibTx()
1283 dib8000_write_word(state, 1606, insertExtSynchro); in dib8096p_cfg_DibTx()
1284 dib8000_write_word(state, 1608, synchroMode); in dib8096p_cfg_DibTx()
1285 dib8000_write_word(state, 1609, (syncWord >> 16) & 0xffff); in dib8096p_cfg_DibTx()
1286 dib8000_write_word(state, 1610, syncWord & 0xffff); in dib8096p_cfg_DibTx()
1287 dib8000_write_word(state, 1612, syncSize); in dib8096p_cfg_DibTx()
1288 dib8000_write_word(state, 1615, 0); in dib8096p_cfg_DibTx()
1291 static void dib8096p_cfg_DibRx(struct dib8000_state *state, u32 P_Kin, in dib8096p_cfg_DibRx() argument
1302 dib8000_write_word(state, 1542, syncFreq); in dib8096p_cfg_DibRx()
1305 dib8000_write_word(state, 1554, 1); in dib8096p_cfg_DibRx()
1306 dib8000_write_word(state, 1536, P_Kin); in dib8096p_cfg_DibRx()
1307 dib8000_write_word(state, 1537, P_Kout); in dib8096p_cfg_DibRx()
1308 dib8000_write_word(state, 1539, synchroMode); in dib8096p_cfg_DibRx()
1309 dib8000_write_word(state, 1540, (syncWord >> 16) & 0xffff); in dib8096p_cfg_DibRx()
1310 dib8000_write_word(state, 1541, syncWord & 0xffff); in dib8096p_cfg_DibRx()
1311 dib8000_write_word(state, 1543, syncSize); in dib8096p_cfg_DibRx()
1312 dib8000_write_word(state, 1544, dataOutRate); in dib8096p_cfg_DibRx()
1313 dib8000_write_word(state, 1554, 0); in dib8096p_cfg_DibRx()
1316 static void dib8096p_enMpegMux(struct dib8000_state *state, int onoff) in dib8096p_enMpegMux() argument
1320 reg_1287 = dib8000_read_word(state, 1287); in dib8096p_enMpegMux()
1331 dib8000_write_word(state, 1287, reg_1287); in dib8096p_enMpegMux()
1334 static void dib8096p_configMpegMux(struct dib8000_state *state, in dib8096p_configMpegMux() argument
1341 dib8096p_enMpegMux(state, 0); in dib8096p_configMpegMux()
1344 if ((enSerialMode == 1) && (state->input_mode_mpeg == 1)) in dib8096p_configMpegMux()
1349 dib8000_write_word(state, 1287, reg_1287); in dib8096p_configMpegMux()
1351 dib8096p_enMpegMux(state, 1); in dib8096p_configMpegMux()
1354 static void dib8096p_setDibTxMux(struct dib8000_state *state, int mode) in dib8096p_setDibTxMux() argument
1356 u16 reg_1288 = dib8000_read_word(state, 1288) & ~(0x7 << 7); in dib8096p_setDibTxMux()
1361 dib8096p_cfg_DibTx(state, 8, 5, 0, 0, 0, 0); in dib8096p_setDibTxMux()
1365 dib8096p_cfg_DibTx(state, 5, 5, 0, 0, 0, 0); in dib8096p_setDibTxMux()
1369 dib8096p_cfg_DibTx(state, 20, 5, 10, 0, 0, 0); in dib8096p_setDibTxMux()
1374 dib8000_write_word(state, 1288, reg_1288); in dib8096p_setDibTxMux()
1377 static void dib8096p_setHostBusMux(struct dib8000_state *state, int mode) in dib8096p_setHostBusMux() argument
1379 u16 reg_1288 = dib8000_read_word(state, 1288) & ~(0x7 << 4); in dib8096p_setHostBusMux()
1384 dib8096p_enMpegMux(state, 0); in dib8096p_setHostBusMux()
1389 dib8096p_enMpegMux(state, 0); in dib8096p_setHostBusMux()
1399 dib8000_write_word(state, 1288, reg_1288); in dib8096p_setHostBusMux()
1404 struct dib8000_state *state = fe->demodulator_priv; in dib8096p_set_diversity_in() local
1412 dib8096p_cfg_DibRx(state, 8, 5, 0, 0, 0, 8, 0); in dib8096p_set_diversity_in()
1416 reg_1287 = dib8000_read_word(state, 1287); in dib8096p_set_diversity_in()
1421 dib8000_write_word(state, 1287, reg_1287); in dib8096p_set_diversity_in()
1423 state->input_mode_mpeg = 1; in dib8096p_set_diversity_in()
1428 dib8096p_cfg_DibRx(state, 5, 5, 0, 0, 0, 0, 0); in dib8096p_set_diversity_in()
1429 state->input_mode_mpeg = 0; in dib8096p_set_diversity_in()
1433 dib8000_set_diversity_in(state->fe[0], onoff); in dib8096p_set_diversity_in()
1439 struct dib8000_state *state = fe->demodulator_priv; in dib8096p_set_output_mode() local
1444 dib8096p_host_bus_drive(state, 1); in dib8096p_set_output_mode()
1447 smo_mode = (dib8000_read_word(state, 299) & 0x0050) | (1 << 1); in dib8096p_set_output_mode()
1448 outreg = dib8000_read_word(state, 1286) & in dib8096p_set_output_mode()
1459 dib8096p_configMpegMux(state, 3, 1, 1); in dib8096p_set_output_mode()
1460 dib8096p_setHostBusMux(state, MPEG_ON_HOSTBUS); in dib8096p_set_output_mode()
1463 dib8096p_setHostBusMux(state, in dib8096p_set_output_mode()
1472 dib8096p_configMpegMux(state, 2, 0, 0); in dib8096p_set_output_mode()
1473 dib8096p_setHostBusMux(state, MPEG_ON_HOSTBUS); in dib8096p_set_output_mode()
1476 dib8096p_setHostBusMux(state, in dib8096p_set_output_mode()
1484 dib8096p_setHostBusMux(state, DEMOUT_ON_HOSTBUS); in dib8096p_set_output_mode()
1492 dib8096p_setHostBusMux(state, DEMOUT_ON_HOSTBUS); in dib8096p_set_output_mode()
1500 dib8096p_setDibTxMux(state, DIV_ON_DIBTX); in dib8096p_set_output_mode()
1501 dib8096p_setHostBusMux(state, DIBTX_ON_HOSTBUS); in dib8096p_set_output_mode()
1506 dib8096p_setDibTxMux(state, ADC_ON_DIBTX); in dib8096p_set_output_mode()
1507 dib8096p_setHostBusMux(state, DIBTX_ON_HOSTBUS); in dib8096p_set_output_mode()
1515 state->cfg.output_mpeg2_in_188_bytes); in dib8096p_set_output_mode()
1516 if (state->cfg.output_mpeg2_in_188_bytes) in dib8096p_set_output_mode()
1519 ret |= dib8000_write_word(state, 299, smo_mode); in dib8096p_set_output_mode()
1521 ret |= dib8000_write_word(state, 299 + 1, fifo_threshold); in dib8096p_set_output_mode()
1522 ret |= dib8000_write_word(state, 1286, outreg); in dib8096p_set_output_mode()
1551 struct dib8000_state *state = i2c_get_adapdata(i2c_adap); in dib8096p_tuner_write_serpar() local
1557 n_overflow = (dib8000_read_word(state, 1984) >> 1) & 0x1; in dib8096p_tuner_write_serpar()
1562 dib8000_write_word(state, 1985, (1 << 6) | (serpar_num & 0x3f)); in dib8096p_tuner_write_serpar()
1563 dib8000_write_word(state, 1986, (msg[0].buf[1] << 8) | msg[0].buf[2]); in dib8096p_tuner_write_serpar()
1571 struct dib8000_state *state = i2c_get_adapdata(i2c_adap); in dib8096p_tuner_read_serpar() local
1578 n_overflow = (dib8000_read_word(state, 1984) >> 1) & 0x1; in dib8096p_tuner_read_serpar()
1583 dib8000_write_word(state, 1985, (0<<6) | (serpar_num&0x3f)); in dib8096p_tuner_read_serpar()
1587 n_empty = dib8000_read_word(state, 1984)&0x1; in dib8096p_tuner_read_serpar()
1593 read_word = dib8000_read_word(state, 1987); in dib8096p_tuner_read_serpar()
1615 struct dib8000_state *state = i2c_get_adapdata(i2c_adap); in dib8096p_rw_on_apb() local
1619 dib8000_write_word(state, apb_address, in dib8096p_rw_on_apb()
1622 word = dib8000_read_word(state, apb_address); in dib8096p_rw_on_apb()
1632 struct dib8000_state *state = i2c_get_adapdata(i2c_adap); in dib8096p_tuner_xfer() local
1723 i = ((dib8000_read_word(state, 921) >> 12)&0x3); in dib8096p_tuner_xfer()
1724 word = dib8000_read_word(state, 924+i); in dib8096p_tuner_xfer()
1734 word = (dib8000_read_word(state, 921) & in dib8096p_tuner_xfer()
1737 dib8000_write_word(state, 921, word); in dib8096p_tuner_xfer()
1769 struct dib8000_state *state = fe->demodulator_priv; in dib8096p_tuner_sleep() local
1774 en_cur_state = dib8000_read_word(state, 1922); in dib8096p_tuner_sleep()
1778 state->tuner_enable = en_cur_state ; in dib8096p_tuner_sleep()
1783 if (state->tuner_enable != 0) in dib8096p_tuner_sleep()
1784 en_cur_state = state->tuner_enable; in dib8096p_tuner_sleep()
1787 dib8000_write_word(state, 1922, en_cur_state); in dib8096p_tuner_sleep()
1800 struct dib8000_state *state = fe->demodulator_priv; in dib8000_get_adc_power() local
1804 val = dib8000_read32(state, 384); in dib8000_get_adc_power()
1820 struct dib8000_state *state = fe->demodulator_priv; in dib8090p_get_dc_power() local
1825 val = dib8000_read_word(state, 403); in dib8090p_get_dc_power()
1828 val = dib8000_read_word(state, 404); in dib8090p_get_dc_power()
1838 static void dib8000_update_timf(struct dib8000_state *state) in dib8000_update_timf() argument
1840 u32 timf = state->timf = dib8000_read32(state, 435); in dib8000_update_timf()
1842 dib8000_write_word(state, 29, (u16) (timf >> 16)); in dib8000_update_timf()
1843 dib8000_write_word(state, 30, (u16) (timf & 0xffff)); in dib8000_update_timf()
1844 dprintk("Updated timing frequency: %d (default: %d)", state->timf, state->timf_default); in dib8000_update_timf()
1849 struct dib8000_state *state = fe->demodulator_priv; in dib8000_ctrl_timf() local
1853 state->timf = timf; in dib8000_ctrl_timf()
1856 dib8000_update_timf(state); in dib8000_ctrl_timf()
1861 dib8000_set_bandwidth(state->fe[0], 6000); in dib8000_ctrl_timf()
1863 return state->timf; in dib8000_ctrl_timf()
1882 static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosearching) in dib8000_set_channel() argument
1893 if (state->revision == 0x8090) in dib8000_set_channel()
1894 dib8000_init_sdram(state); in dib8000_set_channel()
1896 if (state->ber_monitored_layer != LAYER_ALL) in dib8000_set_channel()
1897 …dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & 0x60) | state->ber_monitored_layer… in dib8000_set_channel()
1899 dib8000_write_word(state, 285, dib8000_read_word(state, 285) & 0x60); in dib8000_set_channel()
1901 i = dib8000_read_word(state, 26) & 1; // P_dds_invspec in dib8000_set_channel()
1902 dib8000_write_word(state, 26, state->fe[0]->dtv_property_cache.inversion^i); in dib8000_set_channel()
1904 if (state->fe[0]->dtv_property_cache.isdbt_sb_mode) { in dib8000_set_channel()
1907 state->fe[0]->dtv_property_cache.isdbt_sb_segment_idx - in dib8000_set_channel()
1908 (state->fe[0]->dtv_property_cache.isdbt_sb_segment_count / 2) - in dib8000_set_channel()
1909 (state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2); in dib8000_set_channel()
1910 int clk = state->cfg.pll->internal; in dib8000_set_channel()
1914 if ((state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2) == 0) in dib8000_set_channel()
1917 if (state->cfg.pll->ifreq == 0) { in dib8000_set_channel()
1918 if ((state->fe[0]->dtv_property_cache.inversion ^ i) == 0) { in dib8000_set_channel()
1919 dib8000_write_word(state, 26, dib8000_read_word(state, 26) | 1); in dib8000_set_channel()
1928 if ((state->fe[0]->dtv_property_cache.delivery_system == SYS_ISDBT) in dib8000_set_channel()
1929 && (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) in dib8000_set_channel()
1930 && (((state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2) in dib8000_set_channel()
1931 && (state->fe[0]->dtv_property_cache.isdbt_sb_segment_idx == in dib8000_set_channel()
1932 ((state->fe[0]->dtv_property_cache.isdbt_sb_segment_count / 2) + 1))) in dib8000_set_channel()
1933 || (((state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2) == 0) in dib8000_set_channel()
1934 …&& (state->fe[0]->dtv_property_cache.isdbt_sb_segment_idx == (state->fe[0]->dtv_property_cache.isd… in dib8000_set_channel()
1935 || (((state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2) == 0) in dib8000_set_channel()
1936 && (state->fe[0]->dtv_property_cache.isdbt_sb_segment_idx == in dib8000_set_channel()
1937 ((state->fe[0]->dtv_property_cache.isdbt_sb_segment_count / 2) + 1))) in dib8000_set_channel()
1942 if ((state->fe[0]->dtv_property_cache.inversion ^ i) == 0) in dib8000_set_channel()
1943 new_dds = state->cfg.pll->ifreq - dds_offset; in dib8000_set_channel()
1945 new_dds = state->cfg.pll->ifreq + dds_offset; in dib8000_set_channel()
1947 dib8000_write_word(state, 27, (u16) ((new_dds >> 16) & 0x01ff)); in dib8000_set_channel()
1948 dib8000_write_word(state, 28, (u16) (new_dds & 0xffff)); in dib8000_set_channel()
1949 if (state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2) in dib8000_set_channel()
1950 …sub_channel = ((state->fe[0]->dtv_property_cache.isdbt_sb_subchannel + (3 * seg_offset) + 1) % 41)… in dib8000_set_channel()
1952 …sub_channel = ((state->fe[0]->dtv_property_cache.isdbt_sb_subchannel + (3 * seg_offset)) % 41) / 3; in dib8000_set_channel()
1955 if (state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_2K in dib8000_set_channel()
1956 || state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_4K) { in dib8000_set_channel()
1957 dib8000_write_word(state, 219, dib8000_read_word(state, 219) | 0x1); //adp_pass =1 in dib8000_set_channel()
1958 …dib8000_write_word(state, 190, dib8000_read_word(state, 190) | (0x1 << 14)); //pha3_force_pha_shif… in dib8000_set_channel()
1960 dib8000_write_word(state, 219, dib8000_read_word(state, 219) & 0xfffe); //adp_pass =0 in dib8000_set_channel()
1961 … dib8000_write_word(state, 190, dib8000_read_word(state, 190) & 0xbfff); //pha3_force_pha_shift = 0 in dib8000_set_channel()
1964 switch (state->fe[0]->dtv_property_cache.transmission_mode) { in dib8000_set_channel()
2111 dib8000_write_word(state, 27, (u16) ((state->cfg.pll->ifreq >> 16) & 0x01ff)); in dib8000_set_channel()
2112 dib8000_write_word(state, 28, (u16) (state->cfg.pll->ifreq & 0xffff)); in dib8000_set_channel()
2113 dib8000_write_word(state, 26, (u16) ((state->cfg.pll->ifreq >> 25) & 0x0003)); in dib8000_set_channel()
2116 dib8000_write_word(state, 10, (seq << 4)); in dib8000_set_channel()
2117 // dib8000_write_word(state, 287, (dib8000_read_word(state, 287) & 0xe000) | 0x1000); in dib8000_set_channel()
2119 switch (state->fe[0]->dtv_property_cache.guard_interval) { in dib8000_set_channel()
2135 dib8000_write_word(state, 1, (init_prbs << 2) | (guard & 0x3)); // ADDR 1 in dib8000_set_channel()
2139 switch (state->fe[0]->dtv_property_cache.layer[i].modulation) { in dib8000_set_channel()
2155 switch (state->fe[0]->dtv_property_cache.layer[i].fec) { in dib8000_set_channel()
2174 if ((state->fe[0]->dtv_property_cache.layer[i].interleaving > 0) && in dib8000_set_channel()
2175 ((state->fe[0]->dtv_property_cache.layer[i].interleaving <= 3) || in dib8000_set_channel()
2176 …(state->fe[0]->dtv_property_cache.layer[i].interleaving == 4 && state->fe[0]->dtv_property_cache.i… in dib8000_set_channel()
2178 timeI = state->fe[0]->dtv_property_cache.layer[i].interleaving; in dib8000_set_channel()
2181 …dib8000_write_word(state, 2 + i, (constellation << 10) | ((state->fe[0]->dtv_property_cache.layer[… in dib8000_set_channel()
2183 if (state->fe[0]->dtv_property_cache.layer[i].segment_count > 0) { in dib8000_set_channel()
2187 if (state->fe[0]->dtv_property_cache.layer[i].modulation == QAM_16 || in dib8000_set_channel()
2188 state->fe[0]->dtv_property_cache.layer[i].modulation == QAM_64) in dib8000_set_channel()
2189 max_constellation = state->fe[0]->dtv_property_cache.layer[i].modulation; in dib8000_set_channel()
2192 if (state->fe[0]->dtv_property_cache.layer[i].modulation == QAM_64) in dib8000_set_channel()
2193 max_constellation = state->fe[0]->dtv_property_cache.layer[i].modulation; in dib8000_set_channel()
2199 mode = fft_to_mode(state); in dib8000_set_channel()
2201 //dib8000_write_word(state, 5, 13); /*p_last_seg = 13*/ in dib8000_set_channel()
2203 dib8000_write_word(state, 274, (dib8000_read_word(state, 274) & 0xffcf) | in dib8000_set_channel()
2204 …((state->fe[0]->dtv_property_cache.isdbt_partial_reception & 1) << 5) | ((state->fe[0]->dtv_proper… in dib8000_set_channel()
2207 dprintk("mode = %d ; guard = %d", mode, state->fe[0]->dtv_property_cache.guard_interval); in dib8000_set_channel()
2211 if (state->fe[0]->dtv_property_cache.isdbt_partial_reception) { in dib8000_set_channel()
2212 seg_diff_mask = (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK) << permu_seg[0]; in dib8000_set_channel()
2215 …(state->fe[0]->dtv_property_cache.layer[i].modulation == DQPSK) * state->fe[0]->dtv_property_cache… in dib8000_set_channel()
2221 …(state->fe[0]->dtv_property_cache.layer[i].modulation == DQPSK) * state->fe[0]->dtv_property_cache… in dib8000_set_channel()
2227 state->differential_constellation = (seg_diff_mask != 0); in dib8000_set_channel()
2228 if (state->revision != 0x8090) in dib8000_set_channel()
2229 dib8000_set_diversity_in(state->fe[0], state->diversity_onoff); in dib8000_set_channel()
2231 dib8096p_set_diversity_in(state->fe[0], state->diversity_onoff); in dib8000_set_channel()
2233 if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) { in dib8000_set_channel()
2234 if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 1) in dib8000_set_channel()
2242 dib8000_write_word(state, 0, (mode << 13) | seg_diff_mask); in dib8000_set_channel()
2244 if ((seg_diff_mask) || (state->fe[0]->dtv_property_cache.isdbt_sb_mode)) in dib8000_set_channel()
2245 dib8000_write_word(state, 268, (dib8000_read_word(state, 268) & 0xF9FF) | 0x0200); in dib8000_set_channel()
2247 dib8000_write_word(state, 268, (2 << 9) | 39); //init value in dib8000_set_channel()
2251 dib8000_write_word(state, 352, seg_diff_mask); // ADDR 352 in dib8000_set_channel()
2253 dib8000_write_word(state, 353, seg_mask13); // ADDR 353 in dib8000_set_channel()
2258 if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) { in dib8000_set_channel()
2259 switch (state->fe[0]->dtv_property_cache.transmission_mode) { in dib8000_set_channel()
2261 if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) { in dib8000_set_channel()
2262 if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK) in dib8000_set_channel()
2267 if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK) { in dib8000_set_channel()
2268 if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK) in dib8000_set_channel()
2273 if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK) in dib8000_set_channel()
2282 if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) { in dib8000_set_channel()
2283 if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK) in dib8000_set_channel()
2288 if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK) { in dib8000_set_channel()
2289 if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK) { in dib8000_set_channel()
2295 if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK) { in dib8000_set_channel()
2306 if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) { in dib8000_set_channel()
2307 if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK) in dib8000_set_channel()
2312 if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK) { in dib8000_set_channel()
2313 if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK) { in dib8000_set_channel()
2319 if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK) { in dib8000_set_channel()
2328 dib8000_write_word(state, 343 + i, ncoeff[i]); in dib8000_set_channel()
2332 dib8000_write_word(state, 351, in dib8000_set_channel()
2333 …(state->fe[0]->dtv_property_cache.isdbt_sb_mode << 9) | (state->fe[0]->dtv_property_cache.isdbt_sb… in dib8000_set_channel()
2337 if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) { in dib8000_set_channel()
2341 dib8000_write_word(state, 187, in dib8000_set_channel()
2342 …(4 << 12) | (0 << 11) | (63 << 5) | (0x3 << 3) | ((~state->fe[0]->dtv_property_cache.isdbt_partial… in dib8000_set_channel()
2346 /* dib8000_write_word(state, 351, dib8000_read_word(state, 351) | 0x200); */ in dib8000_set_channel()
2348 if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) { in dib8000_set_channel()
2352 dib8000_write_word(state, 180, 0x1fcf | ((mode - 1) << 14)); in dib8000_set_channel()
2354 dib8000_write_word(state, 180, 0x0fcf | ((mode - 1) << 14)); in dib8000_set_channel()
2357 dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (5 << 5) | 4); in dib8000_set_channel()
2359 dib8000_write_word(state, 340, (16 << 6) | (8 << 0)); in dib8000_set_channel()
2361 dib8000_write_word(state, 341, (6 << 3) | (1 << 2) | (1 << 1) | (1 << 0)); in dib8000_set_channel()
2364 dib8000_write_word(state, 181, 300); in dib8000_set_channel()
2365 dib8000_write_word(state, 182, 150); in dib8000_set_channel()
2366 dib8000_write_word(state, 183, 80); in dib8000_set_channel()
2367 dib8000_write_word(state, 184, 300); in dib8000_set_channel()
2368 dib8000_write_word(state, 185, 150); in dib8000_set_channel()
2369 dib8000_write_word(state, 186, 80); in dib8000_set_channel()
2373 /* dib8000_write_word(state, 180, 0x2fca | ((0) << 14)); */ in dib8000_set_channel()
2375 /* dib8000_write_word(state, 180, 0x2fca | ((1) << 14)); */ in dib8000_set_channel()
2376 dib8000_write_word(state, 180, 0x1fcf | (1 << 14)); in dib8000_set_channel()
2380 dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (4 << 5) | 4); in dib8000_set_channel()
2382 dib8000_write_word(state, 340, (16 << 6) | (8 << 0)); in dib8000_set_channel()
2384 dib8000_write_word(state, 341, (6 << 3) | (1 << 2) | (1 << 1) | (1 << 0)); in dib8000_set_channel()
2387 dib8000_write_word(state, 181, 350); in dib8000_set_channel()
2388 dib8000_write_word(state, 182, 300); in dib8000_set_channel()
2389 dib8000_write_word(state, 183, 250); in dib8000_set_channel()
2390 dib8000_write_word(state, 184, 350); in dib8000_set_channel()
2391 dib8000_write_word(state, 185, 300); in dib8000_set_channel()
2392 dib8000_write_word(state, 186, 250); in dib8000_set_channel()
2395 …} else if (state->isdbt_cfg_loaded == 0) { // if not Sound Broadcasting mode : put default values … in dib8000_set_channel()
2396 dib8000_write_word(state, 180, (16 << 6) | 9); in dib8000_set_channel()
2397 dib8000_write_word(state, 187, (4 << 12) | (8 << 5) | 0x2); in dib8000_set_channel()
2400 dib8000_write_word(state, 181 + i, coff_pow); in dib8000_set_channel()
2404 dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (3 << 5) | 1); in dib8000_set_channel()
2407 dib8000_write_word(state, 340, (8 << 6) | (6 << 0)); in dib8000_set_channel()
2409 dib8000_write_word(state, 341, (4 << 3) | (1 << 2) | (1 << 1) | (1 << 0)); in dib8000_set_channel()
2412 …if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1 && state->fe[0]->dtv_property_cache.isdbt_… in dib8000_set_channel()
2413 dib8000_write_word(state, 178, 64); // P_fft_powrange=64 in dib8000_set_channel()
2415 dib8000_write_word(state, 178, 32); // P_fft_powrange=32 in dib8000_set_channel()
2421 dib8000_write_word(state, 187, (dib8000_read_word(state, 187) & 0xfffb) | (1 << 3)); */ in dib8000_set_channel()
2423 dib8000_write_word(state, 189, ~seg_mask13 | seg_diff_mask); /* P_lmod4_seg_inh */ in dib8000_set_channel()
2424 dib8000_write_word(state, 192, ~seg_mask13 | seg_diff_mask); /* P_pha3_seg_inh */ in dib8000_set_channel()
2425 dib8000_write_word(state, 225, ~seg_mask13 | seg_diff_mask); /* P_tac_seg_inh */ in dib8000_set_channel()
2426 if ((!state->fe[0]->dtv_property_cache.isdbt_sb_mode) && (state->cfg.pll->ifreq == 0)) in dib8000_set_channel()
2427 dib8000_write_word(state, 266, ~seg_mask13 | seg_diff_mask | 0x40); /* P_equal_noise_seg_inh */ in dib8000_set_channel()
2429 dib8000_write_word(state, 266, ~seg_mask13 | seg_diff_mask); /* P_equal_noise_seg_inh */ in dib8000_set_channel()
2430 dib8000_write_word(state, 287, ~seg_mask13 | 0x1000); /* P_tmcc_seg_inh */ in dib8000_set_channel()
2431 //dib8000_write_word(state, 288, ~seg_mask13 | seg_diff_mask); /* P_tmcc_seg_eq_inh */ in dib8000_set_channel()
2433 dib8000_write_word(state, 288, (~seg_mask13 | seg_diff_mask) & 0x1fff); /* P_tmcc_seg_eq_inh */ in dib8000_set_channel()
2435 …dib8000_write_word(state, 288, 0x1fff); //disable equalisation of the tmcc when autosearch to be a… in dib8000_set_channel()
2438 dib8000_write_word(state, 211, seg_mask13 & (~seg_diff_mask)); /* P_des_seg_enabled */ in dib8000_set_channel()
2441 if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) { in dib8000_set_channel()
2442 if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) in dib8000_set_channel()
2444 dib8000_write_word(state, 32, ((11 - mode) << 12) | (6 << 8) | 0x40); in dib8000_set_channel()
2448 dib8000_write_word(state, 32, ((10 - mode) << 12) | (6 << 8) | 0x60); in dib8000_set_channel()
2452 dib8000_write_word(state, 32, ((9 - mode) << 12) | (6 << 8) | 0x80); in dib8000_set_channel()
2454 if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) { in dib8000_set_channel()
2455 if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) in dib8000_set_channel()
2457 dib8000_write_word(state, 37, (3 << 5) | (0 << 4) | (10 - mode)); in dib8000_set_channel()
2461 dib8000_write_word(state, 37, (3 << 5) | (0 << 4) | (9 - mode)); in dib8000_set_channel()
2464 dib8000_write_word(state, 37, (3 << 5) | (0 << 4) | (8 - mode)); in dib8000_set_channel()
2467 switch (state->fe[0]->dtv_property_cache.transmission_mode) { in dib8000_set_channel()
2479 if (state->cfg.diversity_delay == 0) in dib8000_set_channel()
2482 …mode = (mode * (1 << (guard)) * 3) / 2 + state->cfg.diversity_delay; // add 50% SFN margin + compe… in dib8000_set_channel()
2484 dib8000_write_word(state, 273, (dib8000_read_word(state, 273) & 0x000f) | mode); in dib8000_set_channel()
2494 …//if (!state->cfg.hostbus_diversity) //if diversity, we should prehaps use the configuration of th… in dib8000_set_channel()
2502 //if (!((state->cfg.hostbus_diversity) && (max_constellation == QAM_16))) in dib8000_set_channel()
2513 dib8000_write_word(state, 215 + mode, coeff[mode]); in dib8000_set_channel()
2516 dib8000_write_word(state, 116, ana_gain); in dib8000_set_channel()
2520 dib8000_write_word(state, 80 + i, adc_target_16dB[i]); in dib8000_set_channel()
2523 dib8000_write_word(state, 80 + i, adc_target_16dB[i] - 355); in dib8000_set_channel()
2527 if (state->fe[0]->dtv_property_cache.isdbt_sb_mode) { in dib8000_set_channel()
2528 if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 1) in dib8000_set_channel()
2535 if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1 || state->isdbt_cfg_loaded == 0) in dib8000_set_channel()
2537 dib8000_write_word(state, 117 + mode, ana_fe[mode]); in dib8000_set_channel()
2546 dib8000_write_word(state, 222, P_cfr_left_edge); // P_cfr_left_edge in dib8000_set_channel()
2547 dib8000_write_word(state, 223, P_cfr_right_edge); // P_cfr_right_edge in dib8000_set_channel()
2551 if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) { in dib8000_set_channel()
2552 dib8000_write_word(state, 228, 1); // P_2d_mode_byp=1 in dib8000_set_channel()
2553 dib8000_write_word(state, 205, dib8000_read_word(state, 205) & 0xfff0); // P_cspu_win_cut = 0 in dib8000_set_channel()
2554 if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0 in dib8000_set_channel()
2555 && state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_2K) { in dib8000_set_channel()
2556 //dib8000_write_word(state, 219, dib8000_read_word(state, 219) & 0xfffe); // P_adp_pass = 0 in dib8000_set_channel()
2557 dib8000_write_word(state, 265, 15); // P_equal_noise_sel = 15 in dib8000_set_channel()
2559 } else if (state->isdbt_cfg_loaded == 0) { in dib8000_set_channel()
2560 dib8000_write_word(state, 228, 0); // default value in dib8000_set_channel()
2561 dib8000_write_word(state, 265, 31); // default value in dib8000_set_channel()
2562 dib8000_write_word(state, 205, 0x200f); // init value in dib8000_set_channel()
2567 …(((state->fe[0]->dtv_property_cache.layer[i].modulation == DQPSK) * 4 + 1) * state->fe[0]->dtv_pro… in dib8000_set_channel()
2572 dib8000_write_word(state, 290, tmcc_pow); // P_tmcc_dec_thres_2k in dib8000_set_channel()
2573 dib8000_write_word(state, 291, tmcc_pow); // P_tmcc_dec_thres_4k in dib8000_set_channel()
2574 dib8000_write_word(state, 292, tmcc_pow); // P_tmcc_dec_thres_8k in dib8000_set_channel()
2575 //dib8000_write_word(state, 287, (1 << 13) | 0x1000 ); in dib8000_set_channel()
2578 if (state->isdbt_cfg_loaded == 0) in dib8000_set_channel()
2579 dib8000_write_word(state, 250, 3285); /*p_2d_hspeed_thr0 */ in dib8000_set_channel()
2581 if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) in dib8000_set_channel()
2582 state->isdbt_cfg_loaded = 0; in dib8000_set_channel()
2584 state->isdbt_cfg_loaded = 1; in dib8000_set_channel()
2592 struct dib8000_state *state = fe->demodulator_priv; in dib8000_autosearch_start() local
2596 state->fe[0]->dtv_property_cache.inversion = 0; in dib8000_autosearch_start()
2597 if (!state->fe[0]->dtv_property_cache.isdbt_sb_mode) in dib8000_autosearch_start()
2598 state->fe[0]->dtv_property_cache.layer[0].segment_count = 13; in dib8000_autosearch_start()
2599 state->fe[0]->dtv_property_cache.layer[0].modulation = QAM_64; in dib8000_autosearch_start()
2600 state->fe[0]->dtv_property_cache.layer[0].fec = FEC_2_3; in dib8000_autosearch_start()
2601 state->fe[0]->dtv_property_cache.layer[0].interleaving = 0; in dib8000_autosearch_start()
2604 if (state->fe[0]->dtv_property_cache.isdbt_sb_mode) { in dib8000_autosearch_start()
2605 state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_8K; in dib8000_autosearch_start()
2606 state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_8; in dib8000_autosearch_start()
2608 dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); in dib8000_autosearch_start()
2610 if (state->fe[0]->dtv_property_cache.guard_interval == GUARD_INTERVAL_AUTO) { in dib8000_autosearch_start()
2611 if (state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_AUTO) { in dib8000_autosearch_start()
2613 …dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); // P_mode = 1 to… in dib8000_autosearch_start()
2617 if (state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_AUTO) { in dib8000_autosearch_start()
2619 dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); // P_mode = 1 in dib8000_autosearch_start()
2624 if (state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_AUTO) in dib8000_autosearch_start()
2625 state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_8K; in dib8000_autosearch_start()
2626 if (state->fe[0]->dtv_property_cache.guard_interval == GUARD_INTERVAL_AUTO) in dib8000_autosearch_start()
2627 state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_8; in dib8000_autosearch_start()
2630 dib8000_set_channel(state, (unsigned char)slist, 1); in dib8000_autosearch_start()
2631 //dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); // P_mode = 1 in dib8000_autosearch_start()
2636 dib8000_write_word(state, 6, 0x4); in dib8000_autosearch_start()
2637 dib8000_write_word(state, 7, 0x8); in dib8000_autosearch_start()
2638 dib8000_write_word(state, 8, 0x1000); in dib8000_autosearch_start()
2641 value = 50 * state->cfg.pll->internal * factor; in dib8000_autosearch_start()
2642 dib8000_write_word(state, 11, (u16) ((value >> 16) & 0xffff)); // lock0 wait time in dib8000_autosearch_start()
2643 dib8000_write_word(state, 12, (u16) (value & 0xffff)); // lock0 wait time in dib8000_autosearch_start()
2644 value = 100 * state->cfg.pll->internal * factor; in dib8000_autosearch_start()
2645 dib8000_write_word(state, 13, (u16) ((value >> 16) & 0xffff)); // lock1 wait time in dib8000_autosearch_start()
2646 dib8000_write_word(state, 14, (u16) (value & 0xffff)); // lock1 wait time in dib8000_autosearch_start()
2647 value = 1000 * state->cfg.pll->internal * factor; in dib8000_autosearch_start()
2648 dib8000_write_word(state, 15, (u16) ((value >> 16) & 0xffff)); // lock2 wait time in dib8000_autosearch_start()
2649 dib8000_write_word(state, 16, (u16) (value & 0xffff)); // lock2 wait time in dib8000_autosearch_start()
2651 value = dib8000_read_word(state, 0); in dib8000_autosearch_start()
2652 dib8000_write_word(state, 0, (u16) ((1 << 15) | value)); in dib8000_autosearch_start()
2653 dib8000_read_word(state, 1284); // reset the INT. n_irq_pending in dib8000_autosearch_start()
2654 dib8000_write_word(state, 0, (u16) value); in dib8000_autosearch_start()
2663 struct dib8000_state *state = fe->demodulator_priv; in dib8000_autosearch_irq() local
2664 u16 irq_pending = dib8000_read_word(state, 1284); in dib8000_autosearch_irq()
2681 struct dib8000_state *state = fe->demodulator_priv; in dib8000_tune() local
2683 u16 lock, value, mode = fft_to_mode(state); in dib8000_tune()
2686 if (state == NULL) in dib8000_tune()
2689 dib8000_set_bandwidth(fe, state->fe[0]->dtv_property_cache.bandwidth_hz / 1000); in dib8000_tune()
2690 dib8000_set_channel(state, 0, 0); in dib8000_tune()
2693 ret |= dib8000_write_word(state, 770, 0x4000); in dib8000_tune()
2694 ret |= dib8000_write_word(state, 770, 0x0000); in dib8000_tune()
2698 …/* ret |= dib8000_write_word(state, 29, (0 << 9) | (4 << 5) | (0 << 4) | (3 << 0) ); workaround … in dib8000_tune()
2701 if (state->timf == 0) { in dib8000_tune()
2702 if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) { in dib8000_tune()
2703 if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) in dib8000_tune()
2710 if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) { in dib8000_tune()
2711 if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) { in dib8000_tune()
2714 dib8000_write_word(state, 32, ((13 - mode) << 12) | (6 << 8) | 0x40); in dib8000_tune()
2715 //dib8000_write_word(state, 32, (8 << 12) | (6 << 8) | 0x80); in dib8000_tune()
2718 ret |= dib8000_write_word(state, 37, (12 - mode) | ((5 + mode) << 5)); in dib8000_tune()
2723 dib8000_write_word(state, 32, ((12 - mode) << 12) | (6 << 8) | 0x60); in dib8000_tune()
2725 ret |= dib8000_write_word(state, 37, (11 - mode) | ((5 + mode) << 5)); in dib8000_tune()
2730 dib8000_write_word(state, 32, ((11 - mode) << 12) | (6 << 8) | 0x80); in dib8000_tune()
2732 ret |= dib8000_write_word(state, 37, (10 - mode) | ((5 + mode) << 5)); in dib8000_tune()
2737 if (state->revision != 0x8090) in dib8000_tune()
2738 lock = dib8000_read_word(state, 568); in dib8000_tune()
2740 lock = dib8000_read_word(state, 570); in dib8000_tune()
2742 dib8000_update_timf(state); in dib8000_tune()
2745 dib8000_write_word(state, 6, 0x200); in dib8000_tune()
2747 if (state->revision == 0x8002) { in dib8000_tune()
2748 value = dib8000_read_word(state, 903); in dib8000_tune()
2749 dib8000_write_word(state, 903, value & ~(1 << 3)); in dib8000_tune()
2751 dib8000_write_word(state, 903, value | (1 << 3)); in dib8000_tune()
2759 struct dib8000_state *state = fe->demodulator_priv; in dib8000_wakeup() local
2763 dib8000_set_power_mode(state, DIB8000_POWER_ALL); in dib8000_wakeup()
2764 dib8000_set_adc_state(state, DIBX000_ADC_ON); in dib8000_wakeup()
2765 if (dib8000_set_adc_state(state, DIBX000_SLOW_ADC_ON) != 0) in dib8000_wakeup()
2768 if (state->revision != 0x8090) in dib8000_wakeup()
2769 dib8000_sad_calib(state); in dib8000_wakeup()
2771 …for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] … in dib8000_wakeup()
2772 ret = state->fe[index_frontend]->ops.init(state->fe[index_frontend]); in dib8000_wakeup()
2782 struct dib8000_state *state = fe->demodulator_priv; in dib8000_sleep() local
2786 …for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] … in dib8000_sleep()
2787 ret = state->fe[index_frontend]->ops.sleep(state->fe[index_frontend]); in dib8000_sleep()
2792 if (state->revision != 0x8090) in dib8000_sleep()
2794 dib8000_set_power_mode(state, DIB8000_POWER_INTERFACE_ONLY); in dib8000_sleep()
2795 …return dib8000_set_adc_state(state, DIBX000_SLOW_ADC_OFF) | dib8000_set_adc_state(state, DIBX000_A… in dib8000_sleep()
2800 struct dib8000_state *state = fe->demodulator_priv; in dib8000_get_tune_state() local
2801 return state->tune_state; in dib8000_get_tune_state()
2807 struct dib8000_state *state = fe->demodulator_priv; in dib8000_set_tune_state() local
2808 state->tune_state = tune_state; in dib8000_set_tune_state()
2815 struct dib8000_state *state = fe->demodulator_priv; in dib8000_get_frontend() local
2822 …for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] … in dib8000_get_frontend()
2823 state->fe[index_frontend]->ops.read_status(state->fe[index_frontend], &stat); in dib8000_get_frontend()
2827 state->fe[index_frontend]->ops.get_frontend(state->fe[index_frontend]); in dib8000_get_frontend()
2828 …for (sub_index_frontend = 0; (sub_index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[sub_inde… in dib8000_get_frontend()
2830 …state->fe[sub_index_frontend]->dtv_property_cache.isdbt_sb_mode = state->fe[index_frontend]->dtv_p… in dib8000_get_frontend()
2831 …state->fe[sub_index_frontend]->dtv_property_cache.inversion = state->fe[index_frontend]->dtv_prope… in dib8000_get_frontend()
2832 …state->fe[sub_index_frontend]->dtv_property_cache.transmission_mode = state->fe[index_frontend]->d… in dib8000_get_frontend()
2833 …state->fe[sub_index_frontend]->dtv_property_cache.guard_interval = state->fe[index_frontend]->dtv_… in dib8000_get_frontend()
2834 …state->fe[sub_index_frontend]->dtv_property_cache.isdbt_partial_reception = state->fe[index_fronte… in dib8000_get_frontend()
2836 …state->fe[sub_index_frontend]->dtv_property_cache.layer[i].segment_count = state->fe[index_fronten… in dib8000_get_frontend()
2837 …state->fe[sub_index_frontend]->dtv_property_cache.layer[i].interleaving = state->fe[index_frontend… in dib8000_get_frontend()
2838 …state->fe[sub_index_frontend]->dtv_property_cache.layer[i].fec = state->fe[index_frontend]->dtv_pr… in dib8000_get_frontend()
2839 …state->fe[sub_index_frontend]->dtv_property_cache.layer[i].modulation = state->fe[index_frontend]-… in dib8000_get_frontend()
2847 fe->dtv_property_cache.isdbt_sb_mode = dib8000_read_word(state, 508) & 0x1; in dib8000_get_frontend()
2849 if (state->revision == 0x8090) in dib8000_get_frontend()
2850 val = dib8000_read_word(state, 572); in dib8000_get_frontend()
2852 val = dib8000_read_word(state, 570); in dib8000_get_frontend()
2883 val = dib8000_read_word(state, 505); in dib8000_get_frontend()
2888 val = dib8000_read_word(state, 493 + i); in dib8000_get_frontend()
2892 val = dib8000_read_word(state, 499 + i); in dib8000_get_frontend()
2896 val = dib8000_read_word(state, 481 + i); in dib8000_get_frontend()
2920 val = dib8000_read_word(state, 487 + i); in dib8000_get_frontend()
2943 …for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] … in dib8000_get_frontend()
2944 …state->fe[index_frontend]->dtv_property_cache.isdbt_sb_mode = fe->dtv_property_cache.isdbt_sb_mode; in dib8000_get_frontend()
2945 state->fe[index_frontend]->dtv_property_cache.inversion = fe->dtv_property_cache.inversion; in dib8000_get_frontend()
2946 …state->fe[index_frontend]->dtv_property_cache.transmission_mode = fe->dtv_property_cache.transmiss… in dib8000_get_frontend()
2947 …state->fe[index_frontend]->dtv_property_cache.guard_interval = fe->dtv_property_cache.guard_interv… in dib8000_get_frontend()
2948 …state->fe[index_frontend]->dtv_property_cache.isdbt_partial_reception = fe->dtv_property_cache.isd… in dib8000_get_frontend()
2950 …state->fe[index_frontend]->dtv_property_cache.layer[i].segment_count = fe->dtv_property_cache.laye… in dib8000_get_frontend()
2951 …state->fe[index_frontend]->dtv_property_cache.layer[i].interleaving = fe->dtv_property_cache.layer… in dib8000_get_frontend()
2952 state->fe[index_frontend]->dtv_property_cache.layer[i].fec = fe->dtv_property_cache.layer[i].fec; in dib8000_get_frontend()
2953 …state->fe[index_frontend]->dtv_property_cache.layer[i].modulation = fe->dtv_property_cache.layer[i… in dib8000_get_frontend()
2961 struct dib8000_state *state = fe->demodulator_priv; in dib8000_set_frontend() local
2967 if (state->fe[0]->dtv_property_cache.frequency == 0) { in dib8000_set_frontend()
2972 if (state->fe[0]->dtv_property_cache.bandwidth_hz == 0) { in dib8000_set_frontend()
2974 state->fe[0]->dtv_property_cache.bandwidth_hz = 6000000; in dib8000_set_frontend()
2977 …for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] … in dib8000_set_frontend()
2979 state->fe[index_frontend]->dtv_property_cache.delivery_system = SYS_ISDBT; in dib8000_set_frontend()
2980 …memcpy(&state->fe[index_frontend]->dtv_property_cache, &fe->dtv_property_cache, sizeof(struct dtv_… in dib8000_set_frontend()
2982 if (state->revision != 0x8090) in dib8000_set_frontend()
2983 dib8000_set_output_mode(state->fe[index_frontend], in dib8000_set_frontend()
2986 dib8096p_set_output_mode(state->fe[index_frontend], in dib8000_set_frontend()
2988 if (state->fe[index_frontend]->ops.tuner_ops.set_params) in dib8000_set_frontend()
2989 state->fe[index_frontend]->ops.tuner_ops.set_params(state->fe[index_frontend]); in dib8000_set_frontend()
2991 dib8000_set_tune_state(state->fe[index_frontend], CT_AGC_START); in dib8000_set_frontend()
2996 time = dib8000_agc_startup(state->fe[0]); in dib8000_set_frontend()
2997 …for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] … in dib8000_set_frontend()
2998 time_slave = dib8000_agc_startup(state->fe[index_frontend]); in dib8000_set_frontend()
3009 …for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] … in dib8000_set_frontend()
3010 if (dib8000_get_tune_state(state->fe[index_frontend]) != CT_AGC_STOP) { in dib8000_set_frontend()
3017 …for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] … in dib8000_set_frontend()
3018 dib8000_set_tune_state(state->fe[index_frontend], CT_DEMOD_START); in dib8000_set_frontend()
3020 if ((state->fe[0]->dtv_property_cache.delivery_system != SYS_ISDBT) || in dib8000_set_frontend()
3021 (state->fe[0]->dtv_property_cache.inversion == INVERSION_AUTO) || in dib8000_set_frontend()
3022 (state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_AUTO) || in dib8000_set_frontend()
3023 (state->fe[0]->dtv_property_cache.guard_interval == GUARD_INTERVAL_AUTO) || in dib8000_set_frontend()
3024 (((state->fe[0]->dtv_property_cache.isdbt_layer_enabled & (1 << 0)) != 0) && in dib8000_set_frontend()
3025 (state->fe[0]->dtv_property_cache.layer[0].segment_count != 0xff) && in dib8000_set_frontend()
3026 (state->fe[0]->dtv_property_cache.layer[0].segment_count != 0) && in dib8000_set_frontend()
3027 ((state->fe[0]->dtv_property_cache.layer[0].modulation == QAM_AUTO) || in dib8000_set_frontend()
3028 (state->fe[0]->dtv_property_cache.layer[0].fec == FEC_AUTO))) || in dib8000_set_frontend()
3029 (((state->fe[0]->dtv_property_cache.isdbt_layer_enabled & (1 << 1)) != 0) && in dib8000_set_frontend()
3030 (state->fe[0]->dtv_property_cache.layer[1].segment_count != 0xff) && in dib8000_set_frontend()
3031 (state->fe[0]->dtv_property_cache.layer[1].segment_count != 0) && in dib8000_set_frontend()
3032 ((state->fe[0]->dtv_property_cache.layer[1].modulation == QAM_AUTO) || in dib8000_set_frontend()
3033 (state->fe[0]->dtv_property_cache.layer[1].fec == FEC_AUTO))) || in dib8000_set_frontend()
3034 (((state->fe[0]->dtv_property_cache.isdbt_layer_enabled & (1 << 2)) != 0) && in dib8000_set_frontend()
3035 (state->fe[0]->dtv_property_cache.layer[2].segment_count != 0xff) && in dib8000_set_frontend()
3036 (state->fe[0]->dtv_property_cache.layer[2].segment_count != 0) && in dib8000_set_frontend()
3037 ((state->fe[0]->dtv_property_cache.layer[2].modulation == QAM_AUTO) || in dib8000_set_frontend()
3038 (state->fe[0]->dtv_property_cache.layer[2].fec == FEC_AUTO))) || in dib8000_set_frontend()
3039 (((state->fe[0]->dtv_property_cache.layer[0].segment_count == 0) || in dib8000_set_frontend()
3040 ((state->fe[0]->dtv_property_cache.isdbt_layer_enabled & (1 << 0)) == 0)) && in dib8000_set_frontend()
3041 ((state->fe[0]->dtv_property_cache.layer[1].segment_count == 0) || in dib8000_set_frontend()
3042 ((state->fe[0]->dtv_property_cache.isdbt_layer_enabled & (2 << 0)) == 0)) && in dib8000_set_frontend()
3043 …((state->fe[0]->dtv_property_cache.layer[2].segment_count == 0) || ((state->fe[0]->dtv_property_ca… in dib8000_set_frontend()
3048 …for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] … in dib8000_set_frontend()
3049 dib8000_set_bandwidth(state->fe[index_frontend], fe->dtv_property_cache.bandwidth_hz / 1000); in dib8000_set_frontend()
3050 dib8000_autosearch_start(state->fe[index_frontend]); in dib8000_set_frontend()
3057 …for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] … in dib8000_set_frontend()
3059 found = dib8000_autosearch_irq(state->fe[index_frontend]); in dib8000_set_frontend()
3094 … 0, ret = 0; (ret >= 0) && (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend… in dib8000_set_frontend()
3095 ret = dib8000_tune(state->fe[index_frontend]); in dib8000_set_frontend()
3098 if (state->revision != 0x8090) { in dib8000_set_frontend()
3099 dib8000_set_output_mode(state->fe[0], state->cfg.output_mode); in dib8000_set_frontend()
3102 (state->fe[index_frontend] != NULL); in dib8000_set_frontend()
3104 dib8000_set_output_mode(state->fe[index_frontend], in dib8000_set_frontend()
3106 dib8000_set_diversity_in(state->fe[index_frontend-1], 1); in dib8000_set_frontend()
3110 dib8000_set_diversity_in(state->fe[index_frontend-1], 0); in dib8000_set_frontend()
3112 dib8096p_set_output_mode(state->fe[0], state->cfg.output_mode); in dib8000_set_frontend()
3113 if (state->cfg.enMpegOutput == 0) { in dib8000_set_frontend()
3114 dib8096p_setDibTxMux(state, MPEG_ON_DIBTX); in dib8000_set_frontend()
3115 dib8096p_setHostBusMux(state, DIBTX_ON_HOSTBUS); in dib8000_set_frontend()
3119 (state->fe[index_frontend] != NULL); in dib8000_set_frontend()
3121 dib8096p_set_output_mode(state->fe[index_frontend], in dib8000_set_frontend()
3123 dib8096p_set_diversity_in(state->fe[index_frontend-1], 1); in dib8000_set_frontend()
3127 dib8096p_set_diversity_in(state->fe[index_frontend-1], 0); in dib8000_set_frontend()
3135 struct dib8000_state *state = fe->demodulator_priv; in dib8000_read_lock() local
3137 if (state->revision == 0x8090) in dib8000_read_lock()
3138 return dib8000_read_word(state, 570); in dib8000_read_lock()
3139 return dib8000_read_word(state, 568); in dib8000_read_lock()
3144 struct dib8000_state *state = fe->demodulator_priv; in dib8000_read_status() local
3148 if (state->revision == 0x8090) in dib8000_read_status()
3149 lock = dib8000_read_word(state, 570); in dib8000_read_status()
3151 lock = dib8000_read_word(state, 568); in dib8000_read_status()
3153 …for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] … in dib8000_read_status()
3154 lock_slave |= dib8000_read_lock(state->fe[index_frontend]); in dib8000_read_status()
3171 lock = dib8000_read_word(state, 554); /* Viterbi Layer A */ in dib8000_read_status()
3175 lock = dib8000_read_word(state, 555); /* Viterbi Layer B */ in dib8000_read_status()
3179 lock = dib8000_read_word(state, 556); /* Viterbi Layer C */ in dib8000_read_status()
3189 struct dib8000_state *state = fe->demodulator_priv; in dib8000_read_ber() local
3192 if (state->revision == 0x8090) in dib8000_read_ber()
3193 *ber = (dib8000_read_word(state, 562) << 16) | in dib8000_read_ber()
3194 dib8000_read_word(state, 563); in dib8000_read_ber()
3196 *ber = (dib8000_read_word(state, 560) << 16) | in dib8000_read_ber()
3197 dib8000_read_word(state, 561); in dib8000_read_ber()
3203 struct dib8000_state *state = fe->demodulator_priv; in dib8000_read_unc_blocks() local
3206 if (state->revision == 0x8090) in dib8000_read_unc_blocks()
3207 *unc = dib8000_read_word(state, 567); in dib8000_read_unc_blocks()
3209 *unc = dib8000_read_word(state, 565); in dib8000_read_unc_blocks()
3215 struct dib8000_state *state = fe->demodulator_priv; in dib8000_read_signal_strength() local
3220 …for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] … in dib8000_read_signal_strength()
3221 state->fe[index_frontend]->ops.read_signal_strength(state->fe[index_frontend], &val); in dib8000_read_signal_strength()
3228 val = 65535 - dib8000_read_word(state, 390); in dib8000_read_signal_strength()
3238 struct dib8000_state *state = fe->demodulator_priv; in dib8000_get_snr() local
3242 if (state->revision != 0x8090) in dib8000_get_snr()
3243 val = dib8000_read_word(state, 542); in dib8000_get_snr()
3245 val = dib8000_read_word(state, 544); in dib8000_get_snr()
3252 if (state->revision != 0x8090) in dib8000_get_snr()
3253 val = dib8000_read_word(state, 543); in dib8000_get_snr()
3255 val = dib8000_read_word(state, 545); in dib8000_get_snr()
3271 struct dib8000_state *state = fe->demodulator_priv; in dib8000_read_snr() local
3276 …for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] … in dib8000_read_snr()
3277 snr_master += dib8000_get_snr(state->fe[index_frontend]); in dib8000_read_snr()
3291 struct dib8000_state *state = fe->demodulator_priv; in dib8000_set_slave_frontend() local
3294 while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL)) in dib8000_set_slave_frontend()
3298 state->fe[index_frontend] = fe_slave; in dib8000_set_slave_frontend()
3309 struct dib8000_state *state = fe->demodulator_priv; in dib8000_remove_slave_frontend() local
3312 while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL)) in dib8000_remove_slave_frontend()
3315 dprintk("remove slave fe %p (index %i)", state->fe[index_frontend-1], index_frontend-1); in dib8000_remove_slave_frontend()
3316 state->fe[index_frontend] = NULL; in dib8000_remove_slave_frontend()
3327 struct dib8000_state *state = fe->demodulator_priv; in dib8000_get_slave_frontend() local
3331 return state->fe[slave_index]; in dib8000_get_slave_frontend()
3496 struct dib8000_state *state; in dib8000_attach() local
3500 state = kzalloc(sizeof(struct dib8000_state), GFP_KERNEL); in dib8000_attach()
3501 if (state == NULL) in dib8000_attach()
3507 memcpy(&state->cfg, cfg, sizeof(struct dib8000_config)); in dib8000_attach()
3508 state->i2c.adap = i2c_adap; in dib8000_attach()
3509 state->i2c.addr = i2c_addr; in dib8000_attach()
3510 state->i2c.i2c_write_buffer = state->i2c_write_buffer; in dib8000_attach()
3511 state->i2c.i2c_read_buffer = state->i2c_read_buffer; in dib8000_attach()
3512 mutex_init(&state->i2c_buffer_lock); in dib8000_attach()
3513 state->i2c.i2c_buffer_lock = &state->i2c_buffer_lock; in dib8000_attach()
3514 state->gpio_val = cfg->gpio_val; in dib8000_attach()
3515 state->gpio_dir = cfg->gpio_dir; in dib8000_attach()
3520 …if ((state->cfg.output_mode != OUTMODE_MPEG2_SERIAL) && (state->cfg.output_mode != OUTMODE_MPEG2_P… in dib8000_attach()
3521 state->cfg.output_mode = OUTMODE_MPEG2_FIFO; in dib8000_attach()
3523 state->fe[0] = fe; in dib8000_attach()
3524 fe->demodulator_priv = state; in dib8000_attach()
3525 memcpy(&state->fe[0]->ops, &dib8000_ops, sizeof(struct dvb_frontend_ops)); in dib8000_attach()
3527 state->timf_default = cfg->pll->timf; in dib8000_attach()
3529 if (dib8000_identify(&state->i2c) == 0) in dib8000_attach()
3532 dibx000_init_i2c_master(&state->i2c_master, DIB8000, state->i2c.adap, state->i2c.addr); in dib8000_attach()
3535 strncpy(state->dib8096p_tuner_adap.name, "DiB8096P tuner interface", in dib8000_attach()
3536 sizeof(state->dib8096p_tuner_adap.name)); in dib8000_attach()
3537 state->dib8096p_tuner_adap.algo = &dib8096p_tuner_xfer_algo; in dib8000_attach()
3538 state->dib8096p_tuner_adap.algo_data = NULL; in dib8000_attach()
3539 state->dib8096p_tuner_adap.dev.parent = state->i2c.adap->dev.parent; in dib8000_attach()
3540 i2c_set_adapdata(&state->dib8096p_tuner_adap, state); in dib8000_attach()
3541 i2c_add_adapter(&state->dib8096p_tuner_adap); in dib8000_attach()
3545 …dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & ~0x60) | (3 << 5)); /* ber_rs_len … in dib8000_attach()
3550 kfree(state); in dib8000_attach()