Lines Matching full:state
72 static u16 dib7000m_read_word(struct dib7000m_state *state, u16 reg) in dib7000m_read_word() argument
76 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { in dib7000m_read_word()
81 state->i2c_write_buffer[0] = (reg >> 8) | 0x80; in dib7000m_read_word()
82 state->i2c_write_buffer[1] = reg & 0xff; in dib7000m_read_word()
84 memset(state->msg, 0, 2 * sizeof(struct i2c_msg)); in dib7000m_read_word()
85 state->msg[0].addr = state->i2c_addr >> 1; in dib7000m_read_word()
86 state->msg[0].flags = 0; in dib7000m_read_word()
87 state->msg[0].buf = state->i2c_write_buffer; in dib7000m_read_word()
88 state->msg[0].len = 2; in dib7000m_read_word()
89 state->msg[1].addr = state->i2c_addr >> 1; in dib7000m_read_word()
90 state->msg[1].flags = I2C_M_RD; in dib7000m_read_word()
91 state->msg[1].buf = state->i2c_read_buffer; in dib7000m_read_word()
92 state->msg[1].len = 2; in dib7000m_read_word()
94 if (i2c_transfer(state->i2c_adap, state->msg, 2) != 2) in dib7000m_read_word()
97 ret = (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1]; in dib7000m_read_word()
98 mutex_unlock(&state->i2c_buffer_lock); in dib7000m_read_word()
103 static int dib7000m_write_word(struct dib7000m_state *state, u16 reg, u16 val) in dib7000m_write_word() argument
107 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { in dib7000m_write_word()
112 state->i2c_write_buffer[0] = (reg >> 8) & 0xff; in dib7000m_write_word()
113 state->i2c_write_buffer[1] = reg & 0xff; in dib7000m_write_word()
114 state->i2c_write_buffer[2] = (val >> 8) & 0xff; in dib7000m_write_word()
115 state->i2c_write_buffer[3] = val & 0xff; in dib7000m_write_word()
117 memset(&state->msg[0], 0, sizeof(struct i2c_msg)); in dib7000m_write_word()
118 state->msg[0].addr = state->i2c_addr >> 1; in dib7000m_write_word()
119 state->msg[0].flags = 0; in dib7000m_write_word()
120 state->msg[0].buf = state->i2c_write_buffer; in dib7000m_write_word()
121 state->msg[0].len = 4; in dib7000m_write_word()
123 ret = (i2c_transfer(state->i2c_adap, state->msg, 1) != 1 ? in dib7000m_write_word()
125 mutex_unlock(&state->i2c_buffer_lock); in dib7000m_write_word()
128 static void dib7000m_write_tab(struct dib7000m_state *state, u16 *buf) in dib7000m_write_tab() argument
136 if (state->reg_offs && (r >= 112 && r <= 331)) // compensate for 7000MC in dib7000m_write_tab()
140 dib7000m_write_word(state, r, *n++); in dib7000m_write_tab()
147 static int dib7000m_set_output_mode(struct dib7000m_state *state, int mode) in dib7000m_set_output_mode() argument
155 smo_mode = (dib7000m_read_word(state, 294 + state->reg_offs) & 0x0010) | (1 << 1); in dib7000m_set_output_mode()
157 dprintk( "setting output mode for demod %p to %d", &state->demod, mode); in dib7000m_set_output_mode()
170 if (state->cfg.hostbus_diversity) in dib7000m_set_output_mode()
184 dprintk( "Unhandled output_mode passed to be set for demod %p",&state->demod); in dib7000m_set_output_mode()
188 if (state->cfg.output_mpeg2_in_188_bytes) in dib7000m_set_output_mode()
191 ret |= dib7000m_write_word(state, 294 + state->reg_offs, smo_mode); in dib7000m_set_output_mode()
192 ret |= dib7000m_write_word(state, 295 + state->reg_offs, fifo_threshold); /* synchronous fread */ in dib7000m_set_output_mode()
193 ret |= dib7000m_write_word(state, 1795, outreg); in dib7000m_set_output_mode()
194 ret |= dib7000m_write_word(state, 1805, sram); in dib7000m_set_output_mode()
196 if (state->revision == 0x4003) { in dib7000m_set_output_mode()
197 u16 clk_cfg1 = dib7000m_read_word(state, 909) & 0xfffd; in dib7000m_set_output_mode()
200 dib7000m_write_word(state, 909, clk_cfg1); in dib7000m_set_output_mode()
205 static void dib7000m_set_power_mode(struct dib7000m_state *state, enum dib7000m_power_mode mode) in dib7000m_set_power_mode() argument
241 if (!state->cfg.mobile_mode) in dib7000m_set_power_mode()
245 if (state->revision != 0x4000) in dib7000m_set_power_mode()
248 if (state->revision == 0x4003) in dib7000m_set_power_mode()
251 dib7000m_write_word(state, 903 + offset, reg_903); in dib7000m_set_power_mode()
252 dib7000m_write_word(state, 904 + offset, reg_904); in dib7000m_set_power_mode()
253 dib7000m_write_word(state, 905 + offset, reg_905); in dib7000m_set_power_mode()
254 dib7000m_write_word(state, 906 + offset, reg_906); in dib7000m_set_power_mode()
257 static int dib7000m_set_adc_state(struct dib7000m_state *state, enum dibx000_adc_states no) in dib7000m_set_adc_state() argument
260 u16 reg_913 = dib7000m_read_word(state, 913), in dib7000m_set_adc_state()
261 reg_914 = dib7000m_read_word(state, 914); in dib7000m_set_adc_state()
266 ret |= dib7000m_write_word(state, 914, reg_914); in dib7000m_set_adc_state()
275 if (state->revision == 0x4000) { // workaround for PA/MA in dib7000m_set_adc_state()
277 dib7000m_write_word(state, 913, 0); in dib7000m_set_adc_state()
278 dib7000m_write_word(state, 914, reg_914 & 0x3); in dib7000m_set_adc_state()
280 dib7000m_write_word(state, 913, (1 << 15)); in dib7000m_set_adc_state()
281 dib7000m_write_word(state, 914, reg_914 & 0x3); in dib7000m_set_adc_state()
306 ret |= dib7000m_write_word(state, 913, reg_913); in dib7000m_set_adc_state()
307 ret |= dib7000m_write_word(state, 914, reg_914); in dib7000m_set_adc_state()
312 static int dib7000m_set_bandwidth(struct dib7000m_state *state, u32 bw) in dib7000m_set_bandwidth() argument
320 state->current_bandwidth = bw; in dib7000m_set_bandwidth()
322 if (state->timf == 0) { in dib7000m_set_bandwidth()
324 timf = state->timf_default; in dib7000m_set_bandwidth()
327 timf = state->timf; in dib7000m_set_bandwidth()
332 dib7000m_write_word(state, 23, (u16) ((timf >> 16) & 0xffff)); in dib7000m_set_bandwidth()
333 dib7000m_write_word(state, 24, (u16) ((timf ) & 0xffff)); in dib7000m_set_bandwidth()
340 struct dib7000m_state *state = demod->demodulator_priv; in dib7000m_set_diversity_in() local
342 if (state->div_force_off) { in dib7000m_set_diversity_in()
346 state->div_state = (u8)onoff; in dib7000m_set_diversity_in()
349 dib7000m_write_word(state, 263 + state->reg_offs, 6); in dib7000m_set_diversity_in()
350 dib7000m_write_word(state, 264 + state->reg_offs, 6); in dib7000m_set_diversity_in()
351 …dib7000m_write_word(state, 266 + state->reg_offs, (state->div_sync_wait << 4) | (1 << 2) | (2 << 0… in dib7000m_set_diversity_in()
353 dib7000m_write_word(state, 263 + state->reg_offs, 1); in dib7000m_set_diversity_in()
354 dib7000m_write_word(state, 264 + state->reg_offs, 0); in dib7000m_set_diversity_in()
355 dib7000m_write_word(state, 266 + state->reg_offs, 0); in dib7000m_set_diversity_in()
361 static int dib7000m_sad_calib(struct dib7000m_state *state) in dib7000m_sad_calib() argument
365 // dib7000m_write_word(state, 928, (3 << 14) | (1 << 12) | (524 << 0)); // sampling clock of the SA… in dib7000m_sad_calib()
366 dib7000m_write_word(state, 929, (0 << 1) | (0 << 0)); in dib7000m_sad_calib()
367 dib7000m_write_word(state, 930, 776); // 0.625*3.3 / 4096 in dib7000m_sad_calib()
370 dib7000m_write_word(state, 929, (1 << 0)); in dib7000m_sad_calib()
371 dib7000m_write_word(state, 929, (0 << 0)); in dib7000m_sad_calib()
378 static void dib7000m_reset_pll_common(struct dib7000m_state *state, const struct dibx000_bandwidth_… in dib7000m_reset_pll_common() argument
380 dib7000m_write_word(state, 18, (u16) (((bw->internal*1000) >> 16) & 0xffff)); in dib7000m_reset_pll_common()
381 dib7000m_write_word(state, 19, (u16) ( (bw->internal*1000) & 0xffff)); in dib7000m_reset_pll_common()
382 dib7000m_write_word(state, 21, (u16) ( (bw->ifreq >> 16) & 0xffff)); in dib7000m_reset_pll_common()
383 dib7000m_write_word(state, 22, (u16) ( bw->ifreq & 0xffff)); in dib7000m_reset_pll_common()
385 dib7000m_write_word(state, 928, bw->sad_cfg); in dib7000m_reset_pll_common()
388 static void dib7000m_reset_pll(struct dib7000m_state *state) in dib7000m_reset_pll() argument
390 const struct dibx000_bandwidth_config *bw = state->cfg.bw; in dib7000m_reset_pll()
401 if (!state->cfg.quartz_direct) { in dib7000m_reset_pll()
405 if(state->cfg.input_clk_is_div_2) in dib7000m_reset_pll()
414 dib7000m_write_word(state, 910, reg_910); // pll cfg in dib7000m_reset_pll()
415 dib7000m_write_word(state, 907, reg_907); // clk cfg0 in dib7000m_reset_pll()
416 dib7000m_write_word(state, 908, 0x0006); // clk_cfg1 in dib7000m_reset_pll()
418 dib7000m_reset_pll_common(state, bw); in dib7000m_reset_pll()
421 static void dib7000mc_reset_pll(struct dib7000m_state *state) in dib7000mc_reset_pll() argument
423 const struct dibx000_bandwidth_config *bw = state->cfg.bw; in dib7000mc_reset_pll()
427 dib7000m_write_word(state, 907, (bw->pll_prediv << 8) | (bw->pll_ratio << 0)); in dib7000mc_reset_pll()
430 //dib7000m_write_word(state, 908, (1 << 14) | (3 << 12) |(0 << 11) | in dib7000mc_reset_pll()
434 dib7000m_write_word(state, 908, clk_cfg1); in dib7000mc_reset_pll()
436 dib7000m_write_word(state, 908, clk_cfg1); in dib7000mc_reset_pll()
439 dib7000m_write_word(state, 910, (1 << 12) | (2 << 10) | (bw->modulo << 8) | (bw->ADClkSrc << 7)); in dib7000mc_reset_pll()
441 dib7000m_reset_pll_common(state, bw); in dib7000mc_reset_pll()
559 static int dib7000m_demod_reset(struct dib7000m_state *state) in dib7000m_demod_reset() argument
561 dib7000m_set_power_mode(state, DIB7000M_POWER_ALL); in dib7000m_demod_reset()
564 dib7000m_set_adc_state(state, DIBX000_VBG_ENABLE); in dib7000m_demod_reset()
567 dib7000m_write_word(state, 898, 0xffff); in dib7000m_demod_reset()
568 dib7000m_write_word(state, 899, 0xffff); in dib7000m_demod_reset()
569 dib7000m_write_word(state, 900, 0xff0f); in dib7000m_demod_reset()
570 dib7000m_write_word(state, 901, 0xfffc); in dib7000m_demod_reset()
572 dib7000m_write_word(state, 898, 0); in dib7000m_demod_reset()
573 dib7000m_write_word(state, 899, 0); in dib7000m_demod_reset()
574 dib7000m_write_word(state, 900, 0); in dib7000m_demod_reset()
575 dib7000m_write_word(state, 901, 0); in dib7000m_demod_reset()
577 if (state->revision == 0x4000) in dib7000m_demod_reset()
578 dib7000m_reset_pll(state); in dib7000m_demod_reset()
580 dib7000mc_reset_pll(state); in dib7000m_demod_reset()
582 if (dib7000m_reset_gpio(state) != 0) in dib7000m_demod_reset()
585 if (dib7000m_set_output_mode(state, OUTMODE_HIGH_Z) != 0) in dib7000m_demod_reset()
589 dib7000m_write_word(state, 1794, dib7000m_read_word(state, 1794) & ~(1 << 1) ); in dib7000m_demod_reset()
591 dib7000m_set_bandwidth(state, 8000); in dib7000m_demod_reset()
593 dib7000m_set_adc_state(state, DIBX000_SLOW_ADC_ON); in dib7000m_demod_reset()
594 dib7000m_sad_calib(state); in dib7000m_demod_reset()
595 dib7000m_set_adc_state(state, DIBX000_SLOW_ADC_OFF); in dib7000m_demod_reset()
597 if (state->cfg.dvbt_mode) in dib7000m_demod_reset()
598 dib7000m_write_word(state, 1796, 0x0); // select DVB-T output in dib7000m_demod_reset()
600 if (state->cfg.mobile_mode) in dib7000m_demod_reset()
601 dib7000m_write_word(state, 261 + state->reg_offs, 2); in dib7000m_demod_reset()
603 dib7000m_write_word(state, 224 + state->reg_offs, 1); in dib7000m_demod_reset()
606 if(state->cfg.tuner_is_baseband) in dib7000m_demod_reset()
607 dib7000m_write_word(state, 36, 0x0755); in dib7000m_demod_reset()
609 dib7000m_write_word(state, 36, 0x1f55); in dib7000m_demod_reset()
612 if (state->revision == 0x4000) in dib7000m_demod_reset()
613 dib7000m_write_word(state, 909, (3 << 10) | (1 << 6)); in dib7000m_demod_reset()
615 dib7000m_write_word(state, 909, (3 << 4) | 1); in dib7000m_demod_reset()
617 dib7000m_write_tab(state, dib7000m_defaults_common); in dib7000m_demod_reset()
618 dib7000m_write_tab(state, dib7000m_defaults); in dib7000m_demod_reset()
620 dib7000m_set_power_mode(state, DIB7000M_POWER_INTERFACE_ONLY); in dib7000m_demod_reset()
622 state->internal_clk = state->cfg.bw->internal; in dib7000m_demod_reset()
627 static void dib7000m_restart_agc(struct dib7000m_state *state) in dib7000m_restart_agc() argument
630 dib7000m_write_word(state, 898, 0x0c00); in dib7000m_restart_agc()
631 dib7000m_write_word(state, 898, 0x0000); in dib7000m_restart_agc()
634 static int dib7000m_agc_soft_split(struct dib7000m_state *state) in dib7000m_agc_soft_split() argument
638 …if(!state->current_agc || !state->current_agc->perform_agc_softsplit || state->current_agc->split.… in dib7000m_agc_soft_split()
642 agc = dib7000m_read_word(state, 390); in dib7000m_agc_soft_split()
644 if (agc > state->current_agc->split.min_thres) in dib7000m_agc_soft_split()
645 split_offset = state->current_agc->split.min; in dib7000m_agc_soft_split()
646 else if (agc < state->current_agc->split.max_thres) in dib7000m_agc_soft_split()
647 split_offset = state->current_agc->split.max; in dib7000m_agc_soft_split()
649 split_offset = state->current_agc->split.max * in dib7000m_agc_soft_split()
650 (agc - state->current_agc->split.min_thres) / in dib7000m_agc_soft_split()
651 (state->current_agc->split.max_thres - state->current_agc->split.min_thres); in dib7000m_agc_soft_split()
656 return dib7000m_write_word(state, 103, (dib7000m_read_word(state, 103) & 0xff00) | split_offset); in dib7000m_agc_soft_split()
659 static int dib7000m_update_lna(struct dib7000m_state *state) in dib7000m_update_lna() argument
663 if (state->cfg.update_lna) { in dib7000m_update_lna()
665 dyn_gain = dib7000m_read_word(state, 390); in dib7000m_update_lna()
667 if (state->cfg.update_lna(&state->demod,dyn_gain)) { // LNA has changed in dib7000m_update_lna()
668 dib7000m_restart_agc(state); in dib7000m_update_lna()
675 static int dib7000m_set_agc_config(struct dib7000m_state *state, u8 band) in dib7000m_set_agc_config() argument
679 if (state->current_band == band && state->current_agc != NULL) in dib7000m_set_agc_config()
681 state->current_band = band; in dib7000m_set_agc_config()
683 for (i = 0; i < state->cfg.agc_config_count; i++) in dib7000m_set_agc_config()
684 if (state->cfg.agc[i].band_caps & band) { in dib7000m_set_agc_config()
685 agc = &state->cfg.agc[i]; in dib7000m_set_agc_config()
694 state->current_agc = agc; in dib7000m_set_agc_config()
697 dib7000m_write_word(state, 72 , agc->setup); in dib7000m_set_agc_config()
698 dib7000m_write_word(state, 73 , agc->inv_gain); in dib7000m_set_agc_config()
699 dib7000m_write_word(state, 74 , agc->time_stabiliz); in dib7000m_set_agc_config()
700 dib7000m_write_word(state, 97 , (agc->alpha_level << 12) | agc->thlock); in dib7000m_set_agc_config()
703 dib7000m_write_word(state, 98, (agc->alpha_mant << 5) | agc->alpha_exp); in dib7000m_set_agc_config()
704 dib7000m_write_word(state, 99, (agc->beta_mant << 6) | agc->beta_exp); in dib7000m_set_agc_config()
707 …state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, ag… in dib7000m_set_agc_config()
710 if (state->wbd_ref != 0) in dib7000m_set_agc_config()
711 dib7000m_write_word(state, 102, state->wbd_ref); in dib7000m_set_agc_config()
713 dib7000m_write_word(state, 102, agc->wbd_ref); in dib7000m_set_agc_config()
715 dib7000m_write_word(state, 103, (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8) ); in dib7000m_set_agc_config()
716 dib7000m_write_word(state, 104, agc->agc1_max); in dib7000m_set_agc_config()
717 dib7000m_write_word(state, 105, agc->agc1_min); in dib7000m_set_agc_config()
718 dib7000m_write_word(state, 106, agc->agc2_max); in dib7000m_set_agc_config()
719 dib7000m_write_word(state, 107, agc->agc2_min); in dib7000m_set_agc_config()
720 dib7000m_write_word(state, 108, (agc->agc1_pt1 << 8) | agc->agc1_pt2 ); in dib7000m_set_agc_config()
721 dib7000m_write_word(state, 109, (agc->agc1_slope1 << 8) | agc->agc1_slope2); in dib7000m_set_agc_config()
722 dib7000m_write_word(state, 110, (agc->agc2_pt1 << 8) | agc->agc2_pt2); in dib7000m_set_agc_config()
723 dib7000m_write_word(state, 111, (agc->agc2_slope1 << 8) | agc->agc2_slope2); in dib7000m_set_agc_config()
725 if (state->revision > 0x4000) { // settings for the MC in dib7000m_set_agc_config()
726 dib7000m_write_word(state, 71, agc->agc1_pt3); in dib7000m_set_agc_config()
728 // (dib7000m_read_word(state, 929) & 0xffe3) | (agc->wbd_inv << 4) | (agc->wbd_sel << 2), agc->wb… in dib7000m_set_agc_config()
729 …dib7000m_write_word(state, 929, (dib7000m_read_word(state, 929) & 0xffe3) | (agc->wbd_inv << 4) | … in dib7000m_set_agc_config()
734 dib7000m_write_word(state, 88 + i, b[i]); in dib7000m_set_agc_config()
739 static void dib7000m_update_timf(struct dib7000m_state *state) in dib7000m_update_timf() argument
741 u32 timf = (dib7000m_read_word(state, 436) << 16) | dib7000m_read_word(state, 437); in dib7000m_update_timf()
742 state->timf = timf * 160 / (state->current_bandwidth / 50); in dib7000m_update_timf()
743 dib7000m_write_word(state, 23, (u16) (timf >> 16)); in dib7000m_update_timf()
744 dib7000m_write_word(state, 24, (u16) (timf & 0xffff)); in dib7000m_update_timf()
745 dprintk( "updated timf_frequency: %d (default: %d)",state->timf, state->timf_default); in dib7000m_update_timf()
751 struct dib7000m_state *state = demod->demodulator_priv; in dib7000m_agc_startup() local
752 u16 cfg_72 = dib7000m_read_word(state, 72); in dib7000m_agc_startup()
754 u8 *agc_state = &state->agc_state; in dib7000m_agc_startup()
757 switch (state->agc_state) { in dib7000m_agc_startup()
760 dib7000m_set_power_mode(state, DIB7000M_POWER_INTERF_ANALOG_AGC); in dib7000m_agc_startup()
761 dib7000m_set_adc_state(state, DIBX000_ADC_ON); in dib7000m_agc_startup()
763 if (dib7000m_set_agc_config(state, BAND_OF_FREQUENCY(ch->frequency/1000)) != 0) in dib7000m_agc_startup()
772 if (state->cfg.agc_control) in dib7000m_agc_startup()
773 state->cfg.agc_control(&state->demod, 1); in dib7000m_agc_startup()
775 dib7000m_write_word(state, 75, 32768); in dib7000m_agc_startup()
776 if (!state->current_agc->perform_agc_softsplit) { in dib7000m_agc_startup()
778 dib7000m_write_word(state, 103, 1 << 8); /* force 0 split on WBD and restart AGC */ in dib7000m_agc_startup()
788 dib7000m_restart_agc(state); in dib7000m_agc_startup()
792 dib7000m_write_word(state, 72, cfg_72 | (1 << 4)); /* freeze AGC loop */ in dib7000m_agc_startup()
793 dib7000m_write_word(state, 103, 2 << 9); /* fast split search 0.25kHz */ in dib7000m_agc_startup()
799 agc_split = (u8)dib7000m_read_word(state, 392); /* store the split value for the next time */ in dib7000m_agc_startup()
800 dib7000m_write_word(state, 75, dib7000m_read_word(state, 390)); /* set AGC gain start value */ in dib7000m_agc_startup()
802 dib7000m_write_word(state, 72, cfg_72 & ~(1 << 4)); /* std AGC loop */ in dib7000m_agc_startup()
803 …dib7000m_write_word(state, 103, (state->current_agc->wbd_alpha << 9) | agc_split); /* standard spl… in dib7000m_agc_startup()
805 dib7000m_restart_agc(state); in dib7000m_agc_startup()
817 if (dib7000m_update_lna(state)) in dib7000m_agc_startup()
825 dib7000m_agc_soft_split(state); in dib7000m_agc_startup()
827 if (state->cfg.agc_control) in dib7000m_agc_startup()
828 state->cfg.agc_control(&state->demod, 0); in dib7000m_agc_startup()
839 static void dib7000m_set_channel(struct dib7000m_state *state, struct dtv_frontend_properties *ch, in dib7000m_set_channel() argument
844 dib7000m_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->bandwidth_hz)); in dib7000m_set_channel()
873 dib7000m_write_word(state, 0, value); in dib7000m_set_channel()
874 dib7000m_write_word(state, 5, (seq << 4)); in dib7000m_set_channel()
892 dib7000m_write_word(state, 267 + state->reg_offs, value); in dib7000m_set_channel()
897 dib7000m_write_word(state, 26, (6 << 12) | (6 << 8) | 0x80); in dib7000m_set_channel()
900 dib7000m_write_word(state, 29, (0 << 14) | (4 << 10) | (1 << 9) | (3 << 5) | (1 << 4) | (0x3)); in dib7000m_set_channel()
903 dib7000m_write_word(state, 32, (0 << 4) | 0x3); in dib7000m_set_channel()
906 dib7000m_write_word(state, 33, (0 << 4) | 0x5); in dib7000m_set_channel()
922 …state->div_sync_wait = (value * 3) / 2 + 32; // add 50% SFN margin + compensate for one DVSY-fifo … in dib7000m_set_channel()
926 if (1 == 1 || state->revision > 0x4000) in dib7000m_set_channel()
927 state->div_force_off = 0; in dib7000m_set_channel()
929 state->div_force_off = 1; in dib7000m_set_channel()
930 dib7000m_set_diversity_in(&state->demod, state->div_state); in dib7000m_set_channel()
954 dib7000m_write_word(state, 214 + value + state->reg_offs, est[value]); in dib7000m_set_channel()
957 dib7000m_set_power_mode(state, DIB7000M_POWER_COR4_DINTLV_ICIRM_EQUAL_CFROD); in dib7000m_set_channel()
963 struct dib7000m_state *state = demod->demodulator_priv; in dib7000m_autosearch_start() local
977 dib7000m_set_channel(state, &schan, 7); in dib7000m_autosearch_start()
986 value = 30 * state->internal_clk * factor; in dib7000m_autosearch_start()
987 ret |= dib7000m_write_word(state, 6, (u16) ((value >> 16) & 0xffff)); // lock0 wait time in dib7000m_autosearch_start()
988 ret |= dib7000m_write_word(state, 7, (u16) (value & 0xffff)); // lock0 wait time in dib7000m_autosearch_start()
989 value = 100 * state->internal_clk * factor; in dib7000m_autosearch_start()
990 ret |= dib7000m_write_word(state, 8, (u16) ((value >> 16) & 0xffff)); // lock1 wait time in dib7000m_autosearch_start()
991 ret |= dib7000m_write_word(state, 9, (u16) (value & 0xffff)); // lock1 wait time in dib7000m_autosearch_start()
992 value = 500 * state->internal_clk * factor; in dib7000m_autosearch_start()
993 ret |= dib7000m_write_word(state, 10, (u16) ((value >> 16) & 0xffff)); // lock2 wait time in dib7000m_autosearch_start()
994 ret |= dib7000m_write_word(state, 11, (u16) (value & 0xffff)); // lock2 wait time in dib7000m_autosearch_start()
997 value = dib7000m_read_word(state, 0); in dib7000m_autosearch_start()
998 ret |= dib7000m_write_word(state, 0, (u16) (value | (1 << 9))); in dib7000m_autosearch_start()
1001 if (state->revision == 0x4000) in dib7000m_autosearch_start()
1002 dib7000m_write_word(state, 1793, 0); in dib7000m_autosearch_start()
1004 dib7000m_read_word(state, 537); in dib7000m_autosearch_start()
1006 ret |= dib7000m_write_word(state, 0, (u16) value); in dib7000m_autosearch_start()
1011 static int dib7000m_autosearch_irq(struct dib7000m_state *state, u16 reg) in dib7000m_autosearch_irq() argument
1013 u16 irq_pending = dib7000m_read_word(state, reg); in dib7000m_autosearch_irq()
1029 struct dib7000m_state *state = demod->demodulator_priv; in dib7000m_autosearch_is_irq() local
1030 if (state->revision == 0x4000) in dib7000m_autosearch_is_irq()
1031 return dib7000m_autosearch_irq(state, 1793); in dib7000m_autosearch_is_irq()
1033 return dib7000m_autosearch_irq(state, 537); in dib7000m_autosearch_is_irq()
1039 struct dib7000m_state *state = demod->demodulator_priv; in dib7000m_tune() local
1045 dib7000m_set_channel(state, ch, 0); in dib7000m_tune()
1050 ret |= dib7000m_write_word(state, 898, 0x4000); in dib7000m_tune()
1051 ret |= dib7000m_write_word(state, 898, 0x0000); in dib7000m_tune()
1054 dib7000m_set_power_mode(state, DIB7000M_POWER_COR4_CRY_ESRAM_MOUT_NUD); in dib7000m_tune()
1056 …ret |= dib7000m_write_word(state, 29, (0 << 14) | (4 << 10) | (0 << 9) | (3 << 5) | (1 << 4) | (0x… in dib7000m_tune()
1059 if (state->timf == 0) in dib7000m_tune()
1062 //dump_reg(state); in dib7000m_tune()
1071 ret |= dib7000m_write_word(state, 26, value); in dib7000m_tune()
1081 ret |= dib7000m_write_word(state, 32, value); in dib7000m_tune()
1091 ret |= dib7000m_write_word(state, 33, value); in dib7000m_tune()
1094 if ((dib7000m_read_word(state, 535) >> 6) & 0x1) in dib7000m_tune()
1095 dib7000m_update_timf(state); in dib7000m_tune()
1097 dib7000m_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->bandwidth_hz)); in dib7000m_tune()
1103 struct dib7000m_state *state = demod->demodulator_priv; in dib7000m_wakeup() local
1105 dib7000m_set_power_mode(state, DIB7000M_POWER_ALL); in dib7000m_wakeup()
1107 if (dib7000m_set_adc_state(state, DIBX000_SLOW_ADC_ON) != 0) in dib7000m_wakeup()
1122 static int dib7000m_identify(struct dib7000m_state *state) in dib7000m_identify() argument
1126 if ((value = dib7000m_read_word(state, 896)) != 0x01b3) { in dib7000m_identify()
1131 state->revision = dib7000m_read_word(state, 897); in dib7000m_identify()
1132 if (state->revision != 0x4000 && in dib7000m_identify()
1133 state->revision != 0x4001 && in dib7000m_identify()
1134 state->revision != 0x4002 && in dib7000m_identify()
1135 state->revision != 0x4003) { in dib7000m_identify()
1141 if (state->revision == 0x4000 && dib7000m_read_word(state, 769) == 0x4000) { in dib7000m_identify()
1146 switch (state->revision) { in dib7000m_identify()
1148 case 0x4001: state->reg_offs = 1; dprintk( "found DiB7000HC"); break; in dib7000m_identify()
1149 case 0x4002: state->reg_offs = 1; dprintk( "found DiB7000MC"); break; in dib7000m_identify()
1150 case 0x4003: state->reg_offs = 1; dprintk( "found DiB9000"); break; in dib7000m_identify()
1160 struct dib7000m_state *state = fe->demodulator_priv; in dib7000m_get_frontend() local
1161 u16 tps = dib7000m_read_word(state,480); in dib7000m_get_frontend()
1165 fep->bandwidth_hz = BANDWIDTH_TO_HZ(state->current_bandwidth); in dib7000m_get_frontend()
1210 /* native interleaver: (dib7000m_read_word(state, 481) >> 5) & 0x1 */ in dib7000m_get_frontend()
1218 struct dib7000m_state *state = fe->demodulator_priv; in dib7000m_set_frontend() local
1221 dib7000m_set_output_mode(state, OUTMODE_HIGH_Z); in dib7000m_set_frontend()
1223 dib7000m_set_bandwidth(state, BANDWIDTH_TO_KHZ(fep->bandwidth_hz)); in dib7000m_set_frontend()
1229 state->agc_state = 0; in dib7000m_set_frontend()
1258 dib7000m_set_output_mode(state, OUTMODE_MPEG2_FIFO); in dib7000m_set_frontend()
1264 struct dib7000m_state *state = fe->demodulator_priv; in dib7000m_read_status() local
1265 u16 lock = dib7000m_read_word(state, 535); in dib7000m_read_status()
1285 struct dib7000m_state *state = fe->demodulator_priv; in dib7000m_read_ber() local
1286 *ber = (dib7000m_read_word(state, 526) << 16) | dib7000m_read_word(state, 527); in dib7000m_read_ber()
1292 struct dib7000m_state *state = fe->demodulator_priv; in dib7000m_read_unc_blocks() local
1293 *unc = dib7000m_read_word(state, 534); in dib7000m_read_unc_blocks()
1299 struct dib7000m_state *state = fe->demodulator_priv; in dib7000m_read_signal_strength() local
1300 u16 val = dib7000m_read_word(state, 390); in dib7000m_read_signal_strength()
1333 struct dib7000m_state *state = fe->demodulator_priv; in dib7000m_pid_filter_ctrl() local
1334 u16 val = dib7000m_read_word(state, 294 + state->reg_offs) & 0xffef; in dib7000m_pid_filter_ctrl()
1337 return dib7000m_write_word(state, 294 + state->reg_offs, val); in dib7000m_pid_filter_ctrl()
1343 struct dib7000m_state *state = fe->demodulator_priv; in dib7000m_pid_filter() local
1345 return dib7000m_write_word(state, 300 + state->reg_offs + id, in dib7000m_pid_filter()