Lines Matching full:state
216 static u16 dib0090_read_reg(struct dib0090_state *state, u8 reg) in dib0090_read_reg() argument
220 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { in dib0090_read_reg()
225 state->i2c_write_buffer[0] = reg; in dib0090_read_reg()
227 memset(state->msg, 0, 2 * sizeof(struct i2c_msg)); in dib0090_read_reg()
228 state->msg[0].addr = state->config->i2c_address; in dib0090_read_reg()
229 state->msg[0].flags = 0; in dib0090_read_reg()
230 state->msg[0].buf = state->i2c_write_buffer; in dib0090_read_reg()
231 state->msg[0].len = 1; in dib0090_read_reg()
232 state->msg[1].addr = state->config->i2c_address; in dib0090_read_reg()
233 state->msg[1].flags = I2C_M_RD; in dib0090_read_reg()
234 state->msg[1].buf = state->i2c_read_buffer; in dib0090_read_reg()
235 state->msg[1].len = 2; in dib0090_read_reg()
237 if (i2c_transfer(state->i2c, state->msg, 2) != 2) { in dib0090_read_reg()
241 ret = (state->i2c_read_buffer[0] << 8) in dib0090_read_reg()
242 | state->i2c_read_buffer[1]; in dib0090_read_reg()
244 mutex_unlock(&state->i2c_buffer_lock); in dib0090_read_reg()
248 static int dib0090_write_reg(struct dib0090_state *state, u32 reg, u16 val) in dib0090_write_reg() argument
252 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { in dib0090_write_reg()
257 state->i2c_write_buffer[0] = reg & 0xff; in dib0090_write_reg()
258 state->i2c_write_buffer[1] = val >> 8; in dib0090_write_reg()
259 state->i2c_write_buffer[2] = val & 0xff; in dib0090_write_reg()
261 memset(state->msg, 0, sizeof(struct i2c_msg)); in dib0090_write_reg()
262 state->msg[0].addr = state->config->i2c_address; in dib0090_write_reg()
263 state->msg[0].flags = 0; in dib0090_write_reg()
264 state->msg[0].buf = state->i2c_write_buffer; in dib0090_write_reg()
265 state->msg[0].len = 3; in dib0090_write_reg()
267 if (i2c_transfer(state->i2c, state->msg, 1) != 1) { in dib0090_write_reg()
273 mutex_unlock(&state->i2c_buffer_lock); in dib0090_write_reg()
277 static u16 dib0090_fw_read_reg(struct dib0090_fw_state *state, u8 reg) in dib0090_fw_read_reg() argument
281 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { in dib0090_fw_read_reg()
286 state->i2c_write_buffer[0] = reg; in dib0090_fw_read_reg()
288 memset(&state->msg, 0, sizeof(struct i2c_msg)); in dib0090_fw_read_reg()
289 state->msg.addr = reg; in dib0090_fw_read_reg()
290 state->msg.flags = I2C_M_RD; in dib0090_fw_read_reg()
291 state->msg.buf = state->i2c_read_buffer; in dib0090_fw_read_reg()
292 state->msg.len = 2; in dib0090_fw_read_reg()
293 if (i2c_transfer(state->i2c, &state->msg, 1) != 1) { in dib0090_fw_read_reg()
297 ret = (state->i2c_read_buffer[0] << 8) in dib0090_fw_read_reg()
298 | state->i2c_read_buffer[1]; in dib0090_fw_read_reg()
300 mutex_unlock(&state->i2c_buffer_lock); in dib0090_fw_read_reg()
304 static int dib0090_fw_write_reg(struct dib0090_fw_state *state, u8 reg, u16 val) in dib0090_fw_write_reg() argument
308 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { in dib0090_fw_write_reg()
313 state->i2c_write_buffer[0] = val >> 8; in dib0090_fw_write_reg()
314 state->i2c_write_buffer[1] = val & 0xff; in dib0090_fw_write_reg()
316 memset(&state->msg, 0, sizeof(struct i2c_msg)); in dib0090_fw_write_reg()
317 state->msg.addr = reg; in dib0090_fw_write_reg()
318 state->msg.flags = 0; in dib0090_fw_write_reg()
319 state->msg.buf = state->i2c_write_buffer; in dib0090_fw_write_reg()
320 state->msg.len = 2; in dib0090_fw_write_reg()
321 if (i2c_transfer(state->i2c, &state->msg, 1) != 1) { in dib0090_fw_write_reg()
327 mutex_unlock(&state->i2c_buffer_lock); in dib0090_fw_write_reg()
331 #define HARD_RESET(state) do { if (cfg->reset) { if (cfg->sleep) cfg->sleep(fe, 0); msleep(10); … argument
336 static void dib0090_write_regs(struct dib0090_state *state, u8 r, const u16 * b, u8 c) in dib0090_write_regs() argument
339 dib0090_write_reg(state, r++, *b++); in dib0090_write_regs()
345 struct dib0090_state *state = fe->tuner_priv; in dib0090_identify() local
347 struct dib0090_identity *identity = &state->identity; in dib0090_identify()
349 v = dib0090_read_reg(state, 0x1a); in dib0090_identify()
437 struct dib0090_fw_state *state = fe->tuner_priv; in dib0090_fw_identify() local
438 struct dib0090_identity *identity = &state->identity; in dib0090_fw_identify()
440 u16 v = dib0090_fw_read_reg(state, 0x1a); in dib0090_fw_identify()
527 struct dib0090_state *state = fe->tuner_priv; in dib0090_reset_digital() local
530 HARD_RESET(state); in dib0090_reset_digital()
532 dib0090_write_reg(state, 0x24, EN_PLL | EN_CRYSTAL); in dib0090_reset_digital()
533 …dib0090_write_reg(state, 0x1b, EN_DIGCLK | EN_PLL | EN_CRYSTAL); /* PLL, DIG_CLK and CRYSTAL remai… in dib0090_reset_digital()
537 …dib0090_write_reg(state, 0x20, ((cfg->io.adc_clock_ratio - 1) << 11) | (0 << 10) | (1 << 9) | (1 <… in dib0090_reset_digital()
539 …dib0090_write_reg(state, 0x23, (0 << 15) | ((!cfg->analog_output) << 14) | (2 << 10) | (1 << 9) | … in dib0090_reset_digital()
542 …dib0090_write_reg(state, 0x23, (0 << 15) | ((!cfg->analog_output) << 14) | (2 << 10) | (1 << 9) | … in dib0090_reset_digital()
547 PllCfg = dib0090_read_reg(state, 0x21); in dib0090_reset_digital()
555 dib0090_write_reg(state, 0x21, PllCfg); in dib0090_reset_digital()
559 dib0090_write_reg(state, 0x21, PllCfg); in dib0090_reset_digital()
561 /*** Set new Pll configuration in bypass and reset state ***/ in dib0090_reset_digital()
563 dib0090_write_reg(state, 0x21, PllCfg); in dib0090_reset_digital()
567 dib0090_write_reg(state, 0x21, PllCfg); in dib0090_reset_digital()
572 v = !!(dib0090_read_reg(state, 0x1a) & 0x800); in dib0090_reset_digital()
584 dib0090_write_reg(state, 0x21, PllCfg); in dib0090_reset_digital()
589 dib0090_write_reg(state, 0x21, PllCfg); in dib0090_reset_digital()
595 struct dib0090_fw_state *state = fe->tuner_priv; in dib0090_fw_reset_digital() local
601 HARD_RESET(state); in dib0090_fw_reset_digital()
603 dib0090_fw_write_reg(state, 0x24, EN_PLL | EN_CRYSTAL); in dib0090_fw_reset_digital()
604 …dib0090_fw_write_reg(state, 0x1b, EN_DIGCLK | EN_PLL | EN_CRYSTAL); /* PLL, DIG_CLK and CRYSTAL re… in dib0090_fw_reset_digital()
606 dib0090_fw_write_reg(state, 0x20, in dib0090_fw_reset_digital()
616 dib0090_fw_write_reg(state, 0x23, v); in dib0090_fw_reset_digital()
619 PllCfg = dib0090_fw_read_reg(state, 0x21); in dib0090_fw_reset_digital()
626 dib0090_fw_write_reg(state, 0x21, PllCfg); in dib0090_fw_reset_digital()
630 dib0090_fw_write_reg(state, 0x21, PllCfg); in dib0090_fw_reset_digital()
632 /*** Set new Pll configuration in bypass and reset state ***/ in dib0090_fw_reset_digital()
634 dib0090_fw_write_reg(state, 0x21, PllCfg); in dib0090_fw_reset_digital()
638 dib0090_fw_write_reg(state, 0x21, PllCfg); in dib0090_fw_reset_digital()
643 v = !!(dib0090_fw_read_reg(state, 0x1a) & 0x800); in dib0090_fw_reset_digital()
655 dib0090_fw_write_reg(state, 0x21, PllCfg); in dib0090_fw_reset_digital()
660 dib0090_fw_write_reg(state, 0x21, PllCfg); in dib0090_fw_reset_digital()
668 struct dib0090_state *state = fe->tuner_priv; in dib0090_wakeup() local
669 if (state->config->sleep) in dib0090_wakeup()
670 state->config->sleep(fe, 0); in dib0090_wakeup()
673 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14)); in dib0090_wakeup()
679 struct dib0090_state *state = fe->tuner_priv; in dib0090_sleep() local
680 if (state->config->sleep) in dib0090_sleep()
681 state->config->sleep(fe, 1); in dib0090_sleep()
687 struct dib0090_state *state = fe->tuner_priv; in dib0090_dcc_freq() local
689 dib0090_write_reg(state, 0x04, 0); in dib0090_dcc_freq()
691 dib0090_write_reg(state, 0x04, 1); in dib0090_dcc_freq()
911 static s16 dib0090_wbd_to_db(struct dib0090_state *state, u16 wbd) in dib0090_wbd_to_db() argument
914 if (wbd < state->wbd_offset) in dib0090_wbd_to_db()
917 wbd -= state->wbd_offset; in dib0090_wbd_to_db()
922 static void dib0090_wbd_target(struct dib0090_state *state, u32 rf) in dib0090_wbd_target() argument
928 if (state->current_band == BAND_VHF) in dib0090_wbd_target()
931 if (state->current_band == BAND_VHF) in dib0090_wbd_target()
932 offset = state->config->wbd_vhf_offset; in dib0090_wbd_target()
933 if (state->current_band == BAND_CBAND) in dib0090_wbd_target()
934 offset = state->config->wbd_cband_offset; in dib0090_wbd_target()
937 state->wbd_target = dib0090_wbd_to_db(state, state->wbd_offset + offset); in dib0090_wbd_target()
938 dprintk("wbd-target: %d dB", (u32) state->wbd_target); in dib0090_wbd_target()
945 static void dib0090_gain_apply(struct dib0090_state *state, s16 gain_delta, s16 top_delta, u8 force) in dib0090_gain_apply() argument
961 if (top_delta >= ((s16) (state->rf_ramp[0] << WBD_ALPHA) - state->rf_gain_limit)) /* overflow */ in dib0090_gain_apply()
962 state->rf_gain_limit = state->rf_ramp[0] << WBD_ALPHA; in dib0090_gain_apply()
964 state->rf_gain_limit += top_delta; in dib0090_gain_apply()
966 if (state->rf_gain_limit < 0) /*underflow */ in dib0090_gain_apply()
967 state->rf_gain_limit = 0; in dib0090_gain_apply()
970 gain = ((state->rf_gain_limit >> WBD_ALPHA) + state->bb_ramp[0]) << GAIN_ALPHA; in dib0090_gain_apply()
971 if (gain_delta >= ((s16) gain - state->current_gain)) /* overflow */ in dib0090_gain_apply()
972 state->current_gain = gain; in dib0090_gain_apply()
974 state->current_gain += gain_delta; in dib0090_gain_apply()
976 if (state->current_gain < 0) in dib0090_gain_apply()
977 state->current_gain = 0; in dib0090_gain_apply()
980 gain = state->current_gain >> GAIN_ALPHA; in dib0090_gain_apply()
983 if (gain > (state->rf_gain_limit >> WBD_ALPHA)) { in dib0090_gain_apply()
984 rf = state->rf_gain_limit >> WBD_ALPHA; in dib0090_gain_apply()
986 if (bb > state->bb_ramp[0]) in dib0090_gain_apply()
987 bb = state->bb_ramp[0]; in dib0090_gain_apply()
993 state->gain[0] = rf; in dib0090_gain_apply()
994 state->gain[1] = bb; in dib0090_gain_apply()
998 g = state->rf_ramp + 1; /* point on RF LNA1 max gain */ in dib0090_gain_apply()
1017 gain_reg[2] = v | state->rf_lt_def; in dib0090_gain_apply()
1027 g = state->bb_ramp + 1; /* point on BB gain 1 max gain */ in dib0090_gain_apply()
1031 gain_reg[3] |= state->bb_1_def; in dib0090_gain_apply()
1042 if (force || state->gain_reg[i] != v) { in dib0090_gain_apply()
1043 state->gain_reg[i] = v; in dib0090_gain_apply()
1044 dib0090_write_reg(state, gain_reg_addr[i], v); in dib0090_gain_apply()
1049 static void dib0090_set_boost(struct dib0090_state *state, int onoff) in dib0090_set_boost() argument
1051 state->bb_1_def &= 0xdfff; in dib0090_set_boost()
1052 state->bb_1_def |= onoff << 13; in dib0090_set_boost()
1055 static void dib0090_set_rframp(struct dib0090_state *state, const u16 * cfg) in dib0090_set_rframp() argument
1057 state->rf_ramp = cfg; in dib0090_set_rframp()
1060 static void dib0090_set_rframp_pwm(struct dib0090_state *state, const u16 * cfg) in dib0090_set_rframp_pwm() argument
1062 state->rf_ramp = cfg; in dib0090_set_rframp_pwm()
1064 dib0090_write_reg(state, 0x2a, 0xffff); in dib0090_set_rframp_pwm()
1066 dprintk("total RF gain: %ddB, step: %d", (u32) cfg[0], dib0090_read_reg(state, 0x2a)); in dib0090_set_rframp_pwm()
1068 dib0090_write_regs(state, 0x2c, cfg + 3, 6); in dib0090_set_rframp_pwm()
1069 dib0090_write_regs(state, 0x3e, cfg + 9, 2); in dib0090_set_rframp_pwm()
1072 static void dib0090_set_bbramp(struct dib0090_state *state, const u16 * cfg) in dib0090_set_bbramp() argument
1074 state->bb_ramp = cfg; in dib0090_set_bbramp()
1075 dib0090_set_boost(state, cfg[0] > 500); /* we want the boost if the gain is higher that 50dB */ in dib0090_set_bbramp()
1078 static void dib0090_set_bbramp_pwm(struct dib0090_state *state, const u16 * cfg) in dib0090_set_bbramp_pwm() argument
1080 state->bb_ramp = cfg; in dib0090_set_bbramp_pwm()
1082 dib0090_set_boost(state, cfg[0] > 500); /* we want the boost if the gain is higher that 50dB */ in dib0090_set_bbramp_pwm()
1084 dib0090_write_reg(state, 0x33, 0xffff); in dib0090_set_bbramp_pwm()
1085 dprintk("total BB gain: %ddB, step: %d", (u32) cfg[0], dib0090_read_reg(state, 0x33)); in dib0090_set_bbramp_pwm()
1086 dib0090_write_regs(state, 0x35, cfg + 3, 4); in dib0090_set_bbramp_pwm()
1091 struct dib0090_state *state = fe->tuner_priv; in dib0090_pwm_gain_reset() local
1094 if (state->config->use_pwm_agc) { in dib0090_pwm_gain_reset()
1096 if (state->current_band == BAND_SBAND) { in dib0090_pwm_gain_reset()
1097 dib0090_set_rframp_pwm(state, rf_ramp_pwm_sband); in dib0090_pwm_gain_reset()
1098 dib0090_set_bbramp_pwm(state, bb_ramp_pwm_boost); in dib0090_pwm_gain_reset()
1102 if (state->current_band == BAND_CBAND) { in dib0090_pwm_gain_reset()
1103 if (state->identity.in_soc) { in dib0090_pwm_gain_reset()
1104 dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal_socs); in dib0090_pwm_gain_reset()
1105 … if (state->identity.version == SOC_8090_P1G_11R1 || state->identity.version == SOC_8090_P1G_21R1) in dib0090_pwm_gain_reset()
1106 dib0090_set_rframp_pwm(state, rf_ramp_pwm_cband_8090); in dib0090_pwm_gain_reset()
1107 else if (state->identity.version == SOC_7090_P1G_11R1 in dib0090_pwm_gain_reset()
1108 || state->identity.version == SOC_7090_P1G_21R1) { in dib0090_pwm_gain_reset()
1109 if (state->config->is_dib7090e) { in dib0090_pwm_gain_reset()
1110 if (state->rf_ramp == NULL) in dib0090_pwm_gain_reset()
1111 dib0090_set_rframp_pwm(state, rf_ramp_pwm_cband_7090e_sensitivity); in dib0090_pwm_gain_reset()
1113 dib0090_set_rframp_pwm(state, state->rf_ramp); in dib0090_pwm_gain_reset()
1115 dib0090_set_rframp_pwm(state, rf_ramp_pwm_cband_7090); in dib0090_pwm_gain_reset()
1118 dib0090_set_rframp_pwm(state, rf_ramp_pwm_cband); in dib0090_pwm_gain_reset()
1119 dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal); in dib0090_pwm_gain_reset()
1124 if (state->current_band == BAND_VHF) { in dib0090_pwm_gain_reset()
1125 if (state->identity.in_soc) { in dib0090_pwm_gain_reset()
1126 dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal_socs); in dib0090_pwm_gain_reset()
1128 dib0090_set_rframp_pwm(state, rf_ramp_pwm_vhf); in dib0090_pwm_gain_reset()
1129 dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal); in dib0090_pwm_gain_reset()
1134 if (state->identity.in_soc) { in dib0090_pwm_gain_reset()
1135 … if (state->identity.version == SOC_8090_P1G_11R1 || state->identity.version == SOC_8090_P1G_21R1) in dib0090_pwm_gain_reset()
1136 dib0090_set_rframp_pwm(state, rf_ramp_pwm_uhf_8090); in dib0090_pwm_gain_reset()
1137 …else if (state->identity.version == SOC_7090_P1G_11R1 || state->identity.version == SOC_7090_P1G_2… in dib0090_pwm_gain_reset()
1138 dib0090_set_rframp_pwm(state, rf_ramp_pwm_uhf_7090); in dib0090_pwm_gain_reset()
1139 dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal_socs); in dib0090_pwm_gain_reset()
1141 dib0090_set_rframp_pwm(state, rf_ramp_pwm_uhf); in dib0090_pwm_gain_reset()
1142 dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal); in dib0090_pwm_gain_reset()
1146 if (state->rf_ramp[0] != 0) in dib0090_pwm_gain_reset()
1147 dib0090_write_reg(state, 0x32, (3 << 11)); in dib0090_pwm_gain_reset()
1149 dib0090_write_reg(state, 0x32, (0 << 11)); in dib0090_pwm_gain_reset()
1151 dib0090_write_reg(state, 0x04, 0x03); in dib0090_pwm_gain_reset()
1152 dib0090_write_reg(state, 0x39, (1 << 10)); in dib0090_pwm_gain_reset()
1160 struct dib0090_state *state = fe->tuner_priv; in dib0090_set_dc_servo() local
1162 dib0090_write_reg(state, 0x04, DC_servo_cutoff); in dib0090_set_dc_servo()
1166 static u32 dib0090_get_slow_adc_val(struct dib0090_state *state) in dib0090_get_slow_adc_val() argument
1168 u16 adc_val = dib0090_read_reg(state, 0x1d); in dib0090_get_slow_adc_val()
1169 if (state->identity.in_soc) in dib0090_get_slow_adc_val()
1176 struct dib0090_state *state = fe->tuner_priv; in dib0090_gain_control() local
1177 enum frontend_tune_state *tune_state = &state->tune_state; in dib0090_gain_control()
1185 state->agc_freeze = 0; in dib0090_gain_control()
1186 dib0090_write_reg(state, 0x04, 0x0); in dib0090_gain_control()
1189 if (state->current_band == BAND_SBAND) { in dib0090_gain_control()
1190 dib0090_set_rframp(state, rf_ramp_sband); in dib0090_gain_control()
1191 dib0090_set_bbramp(state, bb_ramp_boost); in dib0090_gain_control()
1195 if (state->current_band == BAND_VHF && !state->identity.p1g) { in dib0090_gain_control()
1196 dib0090_set_rframp(state, rf_ramp_vhf); in dib0090_gain_control()
1197 dib0090_set_bbramp(state, bb_ramp_boost); in dib0090_gain_control()
1201 if (state->current_band == BAND_CBAND && !state->identity.p1g) { in dib0090_gain_control()
1202 dib0090_set_rframp(state, rf_ramp_cband); in dib0090_gain_control()
1203 dib0090_set_bbramp(state, bb_ramp_boost); in dib0090_gain_control()
1206 …if ((state->current_band == BAND_CBAND || state->current_band == BAND_VHF) && state->identity.p1g)… in dib0090_gain_control()
1207 dib0090_set_rframp(state, rf_ramp_cband_broadmatching); in dib0090_gain_control()
1208 dib0090_set_bbramp(state, bb_ramp_boost); in dib0090_gain_control()
1210 dib0090_set_rframp(state, rf_ramp_uhf); in dib0090_gain_control()
1211 dib0090_set_bbramp(state, bb_ramp_boost); in dib0090_gain_control()
1214 dib0090_write_reg(state, 0x32, 0); in dib0090_gain_control()
1215 dib0090_write_reg(state, 0x39, 0); in dib0090_gain_control()
1217 dib0090_wbd_target(state, state->current_rf); in dib0090_gain_control()
1219 state->rf_gain_limit = state->rf_ramp[0] << WBD_ALPHA; in dib0090_gain_control()
1220 state->current_gain = ((state->rf_ramp[0] + state->bb_ramp[0]) / 2) << GAIN_ALPHA; in dib0090_gain_control()
1223 } else if (!state->agc_freeze) { in dib0090_gain_control()
1227 wbd_val = dib0090_get_slow_adc_val(state); in dib0090_gain_control()
1235 wbd_val = dib0090_get_slow_adc_val(state); in dib0090_gain_control()
1236 wbd += dib0090_wbd_to_db(state, wbd_val); in dib0090_gain_control()
1239 wbd_error = state->wbd_target - wbd; in dib0090_gain_control()
1242 if (wbd_error < 0 && state->rf_gain_limit > 0 && !state->identity.p1g) { in dib0090_gain_control()
1245 u8 ltg2 = (state->rf_lt_def >> 10) & 0x7; in dib0090_gain_control()
1246 if (state->current_band == BAND_CBAND && ltg2) { in dib0090_gain_control()
1248 state->rf_lt_def &= ltg2 << 10; /* reduce in 3 steps from 7 to 0 */ in dib0090_gain_control()
1252 state->agc_step = 0; in dib0090_gain_control()
1257 adc = state->config->get_adc_power(fe); in dib0090_gain_control()
1262 if (state->fe->dtv_property_cache.delivery_system == STANDARD_DAB) in dib0090_gain_control()
1266 if (state->fe->dtv_property_cache.delivery_system == STANDARD_DVBT && in dib0090_gain_control()
1267 …(state->fe->dtv_property_cache.modulation == QAM_64 || state->fe->dtv_property_cache.modulation ==… in dib0090_gain_control()
1271 …if ((state->fe->dtv_property_cache.delivery_system == SYS_ISDBT) && (((state->fe->dtv_property_cac… in dib0090_gain_control()
1274 ((state->fe->dtv_property_cache.layer[0].modulation == in dib0090_gain_control()
1276 || (state->fe->dtv_property_cache. in dib0090_gain_control()
1279 ((state->fe->dtv_property_cache.layer[1].segment_count > in dib0090_gain_control()
1282 ((state->fe->dtv_property_cache.layer[1].modulation == in dib0090_gain_control()
1284 || (state->fe->dtv_property_cache. in dib0090_gain_control()
1287 ((state->fe->dtv_property_cache.layer[2].segment_count > in dib0090_gain_control()
1290 ((state->fe->dtv_property_cache.layer[2].modulation == in dib0090_gain_control()
1292 || (state->fe->dtv_property_cache. in dib0090_gain_control()
1300 if (ABS(adc_error) < 50 || state->agc_step++ > 5) { in dib0090_gain_control()
1303 if (state->fe->dtv_property_cache.delivery_system == STANDARD_DAB) { in dib0090_gain_control()
1304 …dib0090_write_reg(state, 0x02, (1 << 15) | (15 << 11) | (31 << 6) | (63)); /* cap value = 63 : nar… in dib0090_gain_control()
1305 dib0090_write_reg(state, 0x04, 0x0); in dib0090_gain_control()
1309 dib0090_write_reg(state, 0x02, (1 << 15) | (3 << 11) | (6 << 6) | (32)); in dib0090_gain_control()
1310 …dib0090_write_reg(state, 0x04, 0x01); /*0 = 1KHz ; 1 = 150Hz ; 2 = 50Hz ; 3 = 50KHz ; 4 = servo fa… in dib0090_gain_control()
1323 …("tune state %d, ADC = %3ddB (ADC err %3d) WBD %3ddB (WBD err %3d, WBD val SADC: %4d), RFGainLimit… in dib0090_gain_control()
1325 (u32) state->rf_gain_limit >> WBD_ALPHA, (s32) 200 + adc - (state->current_gain >> GAIN_ALPHA)); in dib0090_gain_control()
1330 if (!state->agc_freeze) in dib0090_gain_control()
1331 dib0090_gain_apply(state, adc_error, wbd_error, apply_gain_immediatly); in dib0090_gain_control()
1339 struct dib0090_state *state = fe->tuner_priv; in dib0090_get_current_gain() local
1341 *rf = state->gain[0]; in dib0090_get_current_gain()
1343 *bb = state->gain[1]; in dib0090_get_current_gain()
1345 *rf_gain_limit = state->rf_gain_limit; in dib0090_get_current_gain()
1347 *rflt = (state->rf_lt_def >> 10) & 0x7; in dib0090_get_current_gain()
1354 struct dib0090_state *state = fe->tuner_priv; in dib0090_get_wbd_target() local
1355 u32 f_MHz = state->fe->dtv_property_cache.frequency / 1000000; in dib0090_get_wbd_target()
1356 s32 current_temp = state->temperature; in dib0090_get_wbd_target()
1358 const struct dib0090_wbd_slope *wbd = state->current_wbd_table; in dib0090_get_wbd_target()
1370 state->wbdmux &= ~(7 << 13); in dib0090_get_wbd_target()
1372 state->wbdmux |= (wbd->wbd_gain << 13); in dib0090_get_wbd_target()
1374 state->wbdmux |= (4 << 13); in dib0090_get_wbd_target()
1376 dib0090_write_reg(state, 0x10, state->wbdmux); in dib0090_get_wbd_target()
1383 state->wbd_target = dib0090_wbd_to_db(state, state->wbd_offset + wbd_tcold); in dib0090_get_wbd_target()
1384 dprintk("wbd-target: %d dB", (u32) state->wbd_target); in dib0090_get_wbd_target()
1387 return state->wbd_offset + wbd_tcold; in dib0090_get_wbd_target()
1393 struct dib0090_state *state = fe->tuner_priv; in dib0090_get_wbd_offset() local
1394 return state->wbd_offset; in dib0090_get_wbd_offset()
1400 struct dib0090_state *state = fe->tuner_priv; in dib0090_set_switch() local
1402 dib0090_write_reg(state, 0x0b, (dib0090_read_reg(state, 0x0b) & 0xfff8) in dib0090_set_switch()
1411 struct dib0090_state *state = fe->tuner_priv; in dib0090_set_vga() local
1413 dib0090_write_reg(state, 0x09, (dib0090_read_reg(state, 0x09) & 0x7fff) in dib0090_set_vga()
1421 struct dib0090_state *state = fe->tuner_priv; in dib0090_update_rframp_7090() local
1423 if ((!state->identity.p1g) || (!state->identity.in_soc) in dib0090_update_rframp_7090()
1424 || ((state->identity.version != SOC_7090_P1G_21R1) in dib0090_update_rframp_7090()
1425 && (state->identity.version != SOC_7090_P1G_11R1))) { in dib0090_update_rframp_7090()
1431 state->rf_ramp = (const u16 *)&rf_ramp_pwm_cband_7090e_sensitivity; in dib0090_update_rframp_7090()
1433 state->rf_ramp = (const u16 *)&rf_ramp_pwm_cband_7090e_aci; in dib0090_update_rframp_7090()
1503 static void dib0090_set_default_config(struct dib0090_state *state, const u16 * n) in dib0090_set_default_config() argument
1511 dib0090_write_reg(state, r, pgm_read_word(n++)); in dib0090_set_default_config()
1525 static void dib0090_set_EFUSE(struct dib0090_state *state) in dib0090_set_EFUSE() argument
1531 e2 = dib0090_read_reg(state, 0x26); in dib0090_set_EFUSE()
1532 e4 = dib0090_read_reg(state, 0x28); in dib0090_set_EFUSE()
1534 if ((state->identity.version == P1D_E_F) || in dib0090_set_EFUSE()
1535 (state->identity.version == P1G) || (e2 == 0xffff)) { in dib0090_set_EFUSE()
1537 dib0090_write_reg(state, 0x22, 0x10); in dib0090_set_EFUSE()
1538 cal = (dib0090_read_reg(state, 0x22) >> 6) & 0x3ff; in dib0090_set_EFUSE()
1561 dib0090_write_reg(state, 0x13, (h << 10)) ; in dib0090_set_EFUSE()
1563 dib0090_write_reg(state, 0x2, e2) ; /* Load the BB_2 */ in dib0090_set_EFUSE()
1569 struct dib0090_state *state = fe->tuner_priv; in dib0090_reset() local
1571 dib0090_reset_digital(fe, state->config); in dib0090_reset()
1576 if (!(state->identity.version & 0x1)) /* it is P1B - reset is already done */ in dib0090_reset()
1580 if (!state->identity.in_soc) { in dib0090_reset()
1581 if ((dib0090_read_reg(state, 0x1a) >> 5) & 0x2) in dib0090_reset()
1582 dib0090_write_reg(state, 0x1b, (EN_IQADC | EN_BB | EN_BIAS | EN_DIGCLK | EN_PLL | EN_CRYSTAL)); in dib0090_reset()
1584 dib0090_write_reg(state, 0x1b, (EN_DIGCLK | EN_PLL | EN_CRYSTAL)); in dib0090_reset()
1587 dib0090_set_default_config(state, dib0090_defaults); in dib0090_reset()
1589 if (state->identity.in_soc) in dib0090_reset()
1590 dib0090_write_reg(state, 0x18, 0x2910); /* charge pump current = 0 */ in dib0090_reset()
1592 if (state->identity.p1g) in dib0090_reset()
1593 dib0090_set_default_config(state, dib0090_p1g_additionnal_defaults); in dib0090_reset()
1596 if (((state->identity.version & 0x1f) >= P1D_E_F) || (state->identity.in_soc)) in dib0090_reset()
1597 dib0090_set_EFUSE(state); in dib0090_reset()
1600 if (state->config->force_crystal_mode != 0) in dib0090_reset()
1601 dib0090_write_reg(state, 0x14, in dib0090_reset()
1602 state->config->force_crystal_mode & 3); in dib0090_reset()
1603 else if (state->config->io.clock_khz >= 24000) in dib0090_reset()
1604 dib0090_write_reg(state, 0x14, 1); in dib0090_reset()
1606 dib0090_write_reg(state, 0x14, 2); in dib0090_reset()
1607 dprintk("Pll lock : %d", (dib0090_read_reg(state, 0x1a) >> 11) & 0x1); in dib0090_reset()
1609 …state->calibrate = DC_CAL | WBD_CAL | TEMP_CAL; /* enable iq-offset-calibration and wbd-calibratio… in dib0090_reset()
1616 static int dib0090_get_offset(struct dib0090_state *state, enum frontend_tune_state *tune_state) in dib0090_get_offset() argument
1623 dib0090_write_reg(state, 0x1f, 0x7); in dib0090_get_offset()
1628 state->adc_diff = dib0090_read_reg(state, 0x1d); in dib0090_get_offset()
1631 dib0090_write_reg(state, 0x1f, 0x4); in dib0090_get_offset()
1636 state->adc_diff -= dib0090_read_reg(state, 0x1d); in dib0090_get_offset()
1677 static void dib0090_set_trim(struct dib0090_state *state) in dib0090_set_trim() argument
1681 if (state->dc->addr == 0x07) in dib0090_set_trim()
1682 val = &state->bb7; in dib0090_set_trim()
1684 val = &state->bb6; in dib0090_set_trim()
1686 *val &= ~(0x1f << state->dc->offset); in dib0090_set_trim()
1687 *val |= state->step << state->dc->offset; in dib0090_set_trim()
1689 dib0090_write_reg(state, state->dc->addr, *val); in dib0090_set_trim()
1692 static int dib0090_dc_offset_calibration(struct dib0090_state *state, enum frontend_tune_state *tun… in dib0090_dc_offset_calibration() argument
1702 state->bb6 = 0; in dib0090_dc_offset_calibration()
1703 state->bb7 = 0x040d; in dib0090_dc_offset_calibration()
1706 reg = dib0090_read_reg(state, 0x24) & 0x0ffb; /* shutdown lna and lo */ in dib0090_dc_offset_calibration()
1707 dib0090_write_reg(state, 0x24, reg); in dib0090_dc_offset_calibration()
1709 state->wbdmux = dib0090_read_reg(state, 0x10); in dib0090_dc_offset_calibration()
1710 dib0090_write_reg(state, 0x10, (state->wbdmux & ~(0xff << 3)) | (0x7 << 3) | 0x3); in dib0090_dc_offset_calibration()
1711 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) & ~(1 << 14)); in dib0090_dc_offset_calibration()
1713 state->dc = dc_table; in dib0090_dc_offset_calibration()
1715 if (state->identity.p1g) in dib0090_dc_offset_calibration()
1716 state->dc = dc_p1g_table; in dib0090_dc_offset_calibration()
1722 dprintk("Sart/continue DC calibration for %s path", (state->dc->i == 1) ? "I" : "Q"); in dib0090_dc_offset_calibration()
1723 dib0090_write_reg(state, 0x01, state->dc->bb1); in dib0090_dc_offset_calibration()
1724 dib0090_write_reg(state, 0x07, state->bb7 | (state->dc->i << 7)); in dib0090_dc_offset_calibration()
1726 state->step = 0; in dib0090_dc_offset_calibration()
1727 state->min_adc_diff = 1023; in dib0090_dc_offset_calibration()
1733 dib0090_set_trim(state); in dib0090_dc_offset_calibration()
1740 ret = dib0090_get_offset(state, tune_state); in dib0090_dc_offset_calibration()
1744 dprintk("adc_diff = %d, current step= %d", (u32) state->adc_diff, state->step); in dib0090_dc_offset_calibration()
1745 if (state->step == 0 && state->adc_diff < 0) { in dib0090_dc_offset_calibration()
1746 state->min_adc_diff = -1023; in dib0090_dc_offset_calibration()
1750 …("adc_diff = %d, min_adc_diff = %d current_step = %d", state->adc_diff, state->min_adc_diff, state… in dib0090_dc_offset_calibration()
1753 if (state->step == 0) { in dib0090_dc_offset_calibration()
1754 if (state->dc->pga && state->adc_diff < 0) in dib0090_dc_offset_calibration()
1755 state->step = 0x10; in dib0090_dc_offset_calibration()
1756 if (state->dc->pga == 0 && state->adc_diff > 0) in dib0090_dc_offset_calibration()
1757 state->step = 0x10; in dib0090_dc_offset_calibration()
1761 if ((state->adc_diff & 0x8000) == (state->min_adc_diff & 0x8000) && steps(state->step) < 15) { in dib0090_dc_offset_calibration()
1763 state->step++; in dib0090_dc_offset_calibration()
1764 state->min_adc_diff = state->adc_diff; in dib0090_dc_offset_calibration()
1768 if (ABS(state->adc_diff) > ABS(state->min_adc_diff)) { in dib0090_dc_offset_calibration()
1769 … adc_diff N = %d > adc_diff step N-1 = %d, Come back one step", state->adc_diff, state->min_adc_d… in dib0090_dc_offset_calibration()
1770 state->step--; in dib0090_dc_offset_calibration()
1773 dib0090_set_trim(state); in dib0090_dc_offset_calibration()
1774 …ntk("BB Offset Cal, BBreg=%hd,Offset=%hd,Value Set=%hd", state->dc->addr, state->adc_diff, state->… in dib0090_dc_offset_calibration()
1776 state->dc++; in dib0090_dc_offset_calibration()
1777 if (state->dc->addr == 0) /* done */ in dib0090_dc_offset_calibration()
1786 dib0090_write_reg(state, 0x07, state->bb7 & ~0x0008); in dib0090_dc_offset_calibration()
1787 dib0090_write_reg(state, 0x1f, 0x7); in dib0090_dc_offset_calibration()
1789 state->calibrate &= ~DC_CAL; in dib0090_dc_offset_calibration()
1796 static int dib0090_wbd_calibration(struct dib0090_state *state, enum frontend_tune_state *tune_stat… in dib0090_wbd_calibration() argument
1799 const struct dib0090_wbd_slope *wbd = state->current_wbd_table; in dib0090_wbd_calibration()
1803 while (state->current_rf / 1000 > wbd->max_freq) in dib0090_wbd_calibration()
1810 if ((state->current_band == BAND_LBAND) || (state->current_band == BAND_SBAND)) in dib0090_wbd_calibration()
1815 if (wbd_gain == state->wbd_calibration_gain) { /* the WBD calibration has already been done */ in dib0090_wbd_calibration()
1817 state->calibrate &= ~WBD_CAL; in dib0090_wbd_calibration()
1821 dib0090_write_reg(state, 0x10, 0x1b81 | (1 << 10) | (wbd_gain << 13) | (1 << 3)); in dib0090_wbd_calibration()
1823 dib0090_write_reg(state, 0x24, ((EN_UHF & 0x0fff) | (1 << 1))); in dib0090_wbd_calibration()
1825 state->wbd_calibration_gain = wbd_gain; in dib0090_wbd_calibration()
1829 state->wbd_offset = dib0090_get_slow_adc_val(state); in dib0090_wbd_calibration()
1830 dprintk("WBD calibration offset = %d", state->wbd_offset); in dib0090_wbd_calibration()
1832 state->calibrate &= ~WBD_CAL; in dib0090_wbd_calibration()
1841 static void dib0090_set_bandwidth(struct dib0090_state *state) in dib0090_set_bandwidth() argument
1845 if (state->fe->dtv_property_cache.bandwidth_hz / 1000 <= 5000) in dib0090_set_bandwidth()
1847 else if (state->fe->dtv_property_cache.bandwidth_hz / 1000 <= 6000) in dib0090_set_bandwidth()
1849 else if (state->fe->dtv_property_cache.bandwidth_hz / 1000 <= 7000) in dib0090_set_bandwidth()
1854 state->bb_1_def &= 0x3fff; in dib0090_set_bandwidth()
1855 state->bb_1_def |= tmp; in dib0090_set_bandwidth()
1857 dib0090_write_reg(state, 0x01, state->bb_1_def); /* be sure that we have the right bb-filter */ in dib0090_set_bandwidth()
1859 …dib0090_write_reg(state, 0x03, 0x6008); /* = 0x6008 : vcm3_trim = 1 ; filter2_gm1_trim = 8 ; filte… in dib0090_set_bandwidth()
1860 …dib0090_write_reg(state, 0x04, 0x1); /* 0 = 1KHz ; 1 = 50Hz ; 2 = 150Hz ; 3 = 50KHz ; 4 = servo fa… in dib0090_set_bandwidth()
1861 if (state->identity.in_soc) { in dib0090_set_bandwidth()
1862 …dib0090_write_reg(state, 0x05, 0x9bcf); /* attenuator_ibias_tri = 2 ; input_stage_ibias_tr = 1 ; n… in dib0090_set_bandwidth()
1864 dib0090_write_reg(state, 0x02, (5 << 11) | (8 << 6) | (22 & 0x3f)); /* 22 = cap_value */ in dib0090_set_bandwidth()
1865 …dib0090_write_reg(state, 0x05, 0xabcd); /* = 0xabcd : attenuator_ibias_tri = 2 ; input_stage_ibias… in dib0090_set_bandwidth()
2063 struct dib0090_state *state = fe->tuner_priv; in dib0090_update_tuning_table_7090() local
2072 if ((!state->identity.p1g) || (!state->identity.in_soc) in dib0090_update_tuning_table_7090()
2073 || ((state->identity.version != SOC_7090_P1G_21R1) in dib0090_update_tuning_table_7090()
2074 && (state->identity.version != SOC_7090_P1G_11R1))) { in dib0090_update_tuning_table_7090()
2084 while (state->rf_request > tune->max_freq) in dib0090_update_tuning_table_7090()
2087 dib0090_write_reg(state, 0x09, (dib0090_read_reg(state, 0x09) & 0x8000) in dib0090_update_tuning_table_7090()
2089 dib0090_write_reg(state, 0x0b, (dib0090_read_reg(state, 0x0b) & 0xf83f) in dib0090_update_tuning_table_7090()
2095 static int dib0090_captrim_search(struct dib0090_state *state, enum frontend_tune_state *tune_state) in dib0090_captrim_search() argument
2105 if (state->identity.version == SOC_8090_P1G_11R1 || state->identity.version == SOC_8090_P1G_21R1) in dib0090_captrim_search()
2110 dib0090_write_reg(state, 0x10, 0x2B1); in dib0090_captrim_search()
2111 dib0090_write_reg(state, 0x1e, 0x0032); in dib0090_captrim_search()
2113 if (!state->tuner_is_tuned) { in dib0090_captrim_search()
2115 if (!state->identity.p1g || force_soft_search) in dib0090_captrim_search()
2116 state->step = state->captrim = state->fcaptrim = 64; in dib0090_captrim_search()
2118 state->current_rf = state->rf_request; in dib0090_captrim_search()
2120 if (!state->identity.p1g || force_soft_search) { in dib0090_captrim_search()
2122 state->step = 4; in dib0090_captrim_search()
2123 state->captrim = state->fcaptrim = dib0090_read_reg(state, 0x18) & 0x7f; in dib0090_captrim_search()
2126 state->adc_diff = 3000; in dib0090_captrim_search()
2130 if (state->identity.p1g && !force_soft_search) { in dib0090_captrim_search()
2133 dib0090_write_reg(state, 0x40, (3 << 7) | (ratio << 2) | (1 << 1) | 1); in dib0090_captrim_search()
2134 dib0090_read_reg(state, 0x40); in dib0090_captrim_search()
2137 state->step /= 2; in dib0090_captrim_search()
2138 dib0090_write_reg(state, 0x18, lo4 | state->captrim); in dib0090_captrim_search()
2140 if (state->identity.in_soc) in dib0090_captrim_search()
2146 if (state->identity.p1g && !force_soft_search) { in dib0090_captrim_search()
2147 dib0090_write_reg(state, 0x40, 0x18c | (0 << 1) | 0); in dib0090_captrim_search()
2148 dib0090_read_reg(state, 0x40); in dib0090_captrim_search()
2150 state->fcaptrim = dib0090_read_reg(state, 0x18) & 0x7F; in dib0090_captrim_search()
2151 dprintk("***Final Captrim= 0x%x", state->fcaptrim); in dib0090_captrim_search()
2156 adc = dib0090_get_slow_adc_val(state); in dib0090_captrim_search()
2157 …dprintk("CAPTRIM=%d; ADC = %d (ADC) & %dmV", (u32) state->captrim, (u32) adc, (u32) (adc) * (u32) … in dib0090_captrim_search()
2159 …if (state->rest == 0 || state->identity.in_soc) { /* Just for 8090P SOCS where auto captrim HW bug… in dib0090_captrim_search()
2172 if (adc < state->adc_diff) { in dib0090_captrim_search()
2173 …dprintk("CAPTRIM=%d is closer to target (%d/%d)", (u32) state->captrim, (u32) adc, (u32) state->ad… in dib0090_captrim_search()
2174 state->adc_diff = adc; in dib0090_captrim_search()
2175 state->fcaptrim = state->captrim; in dib0090_captrim_search()
2178 state->captrim += step_sign * state->step; in dib0090_captrim_search()
2179 if (state->step >= 1) in dib0090_captrim_search()
2188 dib0090_write_reg(state, 0x18, lo4 | state->fcaptrim); in dib0090_captrim_search()
2193 state->calibrate &= ~CAPTRIM_CAL; in dib0090_captrim_search()
2200 static int dib0090_get_temperature(struct dib0090_state *state, enum frontend_tune_state *tune_stat… in dib0090_get_temperature() argument
2207 state->wbdmux = dib0090_read_reg(state, 0x10); in dib0090_get_temperature()
2208 dib0090_write_reg(state, 0x10, (state->wbdmux & ~(0xff << 3)) | (0x8 << 3)); in dib0090_get_temperature()
2210 state->bias = dib0090_read_reg(state, 0x13); in dib0090_get_temperature()
2211 dib0090_write_reg(state, 0x13, state->bias | (0x3 << 8)); in dib0090_get_temperature()
2218 state->adc_diff = dib0090_get_slow_adc_val(state); in dib0090_get_temperature()
2219 dib0090_write_reg(state, 0x13, (state->bias & ~(0x3 << 8)) | (0x2 << 8)); in dib0090_get_temperature()
2224 val = dib0090_get_slow_adc_val(state); in dib0090_get_temperature()
2225 state->temperature = ((s16) ((val - state->adc_diff) * 180) >> 8) + 55; in dib0090_get_temperature()
2227 dprintk("temperature: %d C", state->temperature - 30); in dib0090_get_temperature()
2233 dib0090_write_reg(state, 0x13, state->bias); in dib0090_get_temperature()
2234 dib0090_write_reg(state, 0x10, state->wbdmux); /* write back original WBDMUX */ in dib0090_get_temperature()
2237 state->calibrate &= ~TEMP_CAL; in dib0090_get_temperature()
2238 if (state->config->analog_output == 0) in dib0090_get_temperature()
2239 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14)); in dib0090_get_temperature()
2253 struct dib0090_state *state = fe->tuner_priv; in dib0090_tune() local
2254 const struct dib0090_tuning *tune = state->current_tune_table_index; in dib0090_tune()
2255 const struct dib0090_pll *pll = state->current_pll_table_index; in dib0090_tune()
2256 enum frontend_tune_state *tune_state = &state->tune_state; in dib0090_tune()
2271 if (state->calibrate & (DC_CAL | TEMP_CAL | WBD_CAL)) in dib0090_tune()
2272 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) & ~(1 << 14)); in dib0090_tune()
2275 if (state->config->analog_output == 0) in dib0090_tune()
2276 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14)); in dib0090_tune()
2279 if (state->calibrate & DC_CAL) in dib0090_tune()
2280 return dib0090_dc_offset_calibration(state, tune_state); in dib0090_tune()
2281 else if (state->calibrate & WBD_CAL) { in dib0090_tune()
2282 if (state->current_rf == 0) in dib0090_tune()
2283 state->current_rf = state->fe->dtv_property_cache.frequency / 1000; in dib0090_tune()
2284 return dib0090_wbd_calibration(state, tune_state); in dib0090_tune()
2285 } else if (state->calibrate & TEMP_CAL) in dib0090_tune()
2286 return dib0090_get_temperature(state, tune_state); in dib0090_tune()
2287 else if (state->calibrate & CAPTRIM_CAL) in dib0090_tune()
2288 return dib0090_captrim_search(state, tune_state); in dib0090_tune()
2292 if (state->config->use_pwm_agc && state->identity.in_soc) { in dib0090_tune()
2293 tmp = dib0090_read_reg(state, 0x39); in dib0090_tune()
2295 dib0090_write_reg(state, 0x39, tmp & ~(1 << 10)); in dib0090_tune()
2298 state->current_band = (u8) BAND_OF_FREQUENCY(state->fe->dtv_property_cache.frequency / 1000); in dib0090_tune()
2299 state->rf_request = in dib0090_tune()
2300 state->fe->dtv_property_cache.frequency / 1000 + (state->current_band == in dib0090_tune()
2301 BAND_UHF ? state->config->freq_offset_khz_uhf : state->config-> in dib0090_tune()
2305 …if ((state->fe->dtv_property_cache.delivery_system == SYS_ISDBT && state->fe->dtv_property_cache.i… in dib0090_tune()
2306 && state->fe->dtv_property_cache.isdbt_partial_reception == 0)) { in dib0090_tune()
2307 const struct dib0090_low_if_offset_table *LUT_offset = state->config->low_if; in dib0090_tune()
2313 if (((state->rf_request > (LUT_offset->RF_freq - margin_khz)) in dib0090_tune()
2314 && (state->rf_request < (LUT_offset->RF_freq + margin_khz))) in dib0090_tune()
2315 && LUT_offset->std == state->fe->dtv_property_cache.delivery_system) { in dib0090_tune()
2316 state->rf_request += LUT_offset->offset_khz; in dib0090_tune()
2325 state->rf_request += 400; in dib0090_tune()
2327 …if (state->current_rf != state->rf_request || (state->current_standard != state->fe->dtv_property_… in dib0090_tune()
2328 state->tuner_is_tuned = 0; in dib0090_tune()
2329 state->current_rf = 0; in dib0090_tune()
2330 state->current_standard = 0; in dib0090_tune()
2333 if (state->identity.p1g) in dib0090_tune()
2336 tmp = (state->identity.version >> 5) & 0x7; in dib0090_tune()
2338 if (state->identity.in_soc) { in dib0090_tune()
2339 if (state->config->force_cband_input) { /* Use the CBAND input for all band */ in dib0090_tune()
2340 …if (state->current_band & BAND_CBAND || state->current_band & BAND_FM || state->current_band & BAN… in dib0090_tune()
2341 || state->current_band & BAND_UHF) { in dib0090_tune()
2342 state->current_band = BAND_CBAND; in dib0090_tune()
2343 if (state->config->is_dib7090e) in dib0090_tune()
2349 …if (state->current_band & BAND_CBAND || state->current_band & BAND_FM || state->current_band & BAN… in dib0090_tune()
2350 state->current_band = BAND_CBAND; in dib0090_tune()
2351 if (state->config->is_dib7090e) in dib0090_tune()
2360 …if (state->current_band == BAND_FM || state->current_band == BAND_CBAND || state->current_band == … in dib0090_tune()
2361 state->current_band = BAND_CBAND; /* Force CBAND */ in dib0090_tune()
2364 if (state->identity.p1g) in dib0090_tune()
2370 if (state->identity.p1g) in dib0090_tune()
2374 while (state->rf_request > tune->max_freq) in dib0090_tune()
2376 while (state->rf_request > pll->max_freq) in dib0090_tune()
2379 state->current_tune_table_index = tune; in dib0090_tune()
2380 state->current_pll_table_index = pll; in dib0090_tune()
2382 dib0090_write_reg(state, 0x0b, 0xb800 | (tune->switch_trim)); in dib0090_tune()
2384 VCOF_kHz = (pll->hfdiv * state->rf_request) * 2; in dib0090_tune()
2386 FREF = state->config->io.clock_khz; in dib0090_tune()
2387 if (state->config->fref_clock_ratio != 0) in dib0090_tune()
2388 FREF /= state->config->fref_clock_ratio; in dib0090_tune()
2403 state->rest = Rest; in dib0090_tune()
2417 else if (state->config->analog_output) in dib0090_tune()
2423 if (state->identity.p1g) { /* Bias is done automatically in P1G */ in dib0090_tune()
2424 if (state->identity.in_soc) { in dib0090_tune()
2425 if (state->identity.version == SOC_8090_P1G_11R1) in dib0090_tune()
2435 if (!state->config->io.pll_int_loop_filt) { in dib0090_tune()
2436 if (state->identity.in_soc) in dib0090_tune()
2438 else if (state->identity.p1g || (Rest == 0)) in dib0090_tune()
2443 lo6 = (state->config->io.pll_int_loop_filt << 3); in dib0090_tune()
2448 if (state->config->analog_output) in dib0090_tune()
2451 if (state->identity.in_soc) in dib0090_tune()
2458 dib0090_write_reg(state, 0x15, (u16) FBDiv); in dib0090_tune()
2459 if (state->config->fref_clock_ratio != 0) in dib0090_tune()
2460 dib0090_write_reg(state, 0x16, (Den << 8) | state->config->fref_clock_ratio); in dib0090_tune()
2462 dib0090_write_reg(state, 0x16, (Den << 8) | 1); in dib0090_tune()
2463 dib0090_write_reg(state, 0x17, (u16) Rest); in dib0090_tune()
2464 dib0090_write_reg(state, 0x19, lo5); in dib0090_tune()
2465 dib0090_write_reg(state, 0x1c, lo6); in dib0090_tune()
2468 if (state->config->analog_output) in dib0090_tune()
2471 dib0090_write_reg(state, 0x24, lo6 | EN_LO | state->config->use_pwm_agc * EN_CRYSTAL); in dib0090_tune()
2475 state->current_rf = state->rf_request; in dib0090_tune()
2476 state->current_standard = state->fe->dtv_property_cache.delivery_system; in dib0090_tune()
2479 state->calibrate = CAPTRIM_CAL; /* captrim serach now */ in dib0090_tune()
2482 …s step, change it also in _cal.c file because it is the step following captrim cal state machine */ in dib0090_tune()
2483 const struct dib0090_wbd_slope *wbd = state->current_wbd_table; in dib0090_tune()
2485 while (state->current_rf / 1000 > wbd->max_freq) in dib0090_tune()
2488 dib0090_write_reg(state, 0x1e, 0x07ff); in dib0090_tune()
2489 dprintk("Final Captrim: %d", (u32) state->fcaptrim); in dib0090_tune()
2492 …n kHz: %d ((%d*%d) << 1))", (u32) ((pll->hfdiv * state->rf_request) * 2), (u32) pll->hfdiv, (u32) … in dib0090_tune()
2493 dprintk("REFDIV: %d, FREF: %d", (u32) 1, (u32) state->config->io.clock_khz); in dib0090_tune()
2494 …dprintk("FBDIV: %d, Rest: %d", (u32) dib0090_read_reg(state, 0x15), (u32) dib0090_read_reg(state, … in dib0090_tune()
2495 …ntk("Num: %d, Den: %d, SD: %d", (u32) dib0090_read_reg(state, 0x17), (u32) (dib0090_read_reg(state… in dib0090_tune()
2496 (u32) dib0090_read_reg(state, 0x1c) & 0x3); in dib0090_tune()
2505 state->wbdmux = (c << 13) | (i << 11) | (WBD | (state->config->use_pwm_agc << 1)); in dib0090_tune()
2506 dib0090_write_reg(state, 0x10, state->wbdmux); in dib0090_tune()
2508 if ((tune->tuner_enable == EN_CAB) && state->identity.p1g) { in dib0090_tune()
2510 dib0090_write_reg(state, 0x09, tune->lna_bias); in dib0090_tune()
2511 dib0090_write_reg(state, 0x0b, 0xb800 | (tune->lna_tune << 6) | (tune->switch_trim)); in dib0090_tune()
2513 dib0090_write_reg(state, 0x09, (tune->lna_tune << 5) | tune->lna_bias); in dib0090_tune()
2515 dib0090_write_reg(state, 0x0c, tune->v2i); in dib0090_tune()
2516 dib0090_write_reg(state, 0x0d, tune->mix); in dib0090_tune()
2517 dib0090_write_reg(state, 0x0e, tune->load); in dib0090_tune()
2522 state->rf_lt_def = 0x7c00; in dib0090_tune()
2524 dib0090_set_bandwidth(state); in dib0090_tune()
2525 state->tuner_is_tuned = 1; in dib0090_tune()
2527 state->calibrate |= WBD_CAL; in dib0090_tune()
2528 state->calibrate |= TEMP_CAL; in dib0090_tune()
2544 struct dib0090_state *state = fe->tuner_priv; in dib0090_get_tune_state() local
2546 return state->tune_state; in dib0090_get_tune_state()
2553 struct dib0090_state *state = fe->tuner_priv; in dib0090_set_tune_state() local
2555 state->tune_state = tune_state; in dib0090_set_tune_state()
2563 struct dib0090_state *state = fe->tuner_priv; in dib0090_get_frequency() local
2565 *frequency = 1000 * state->current_rf; in dib0090_get_frequency()
2571 struct dib0090_state *state = fe->tuner_priv; in dib0090_set_params() local
2574 state->tune_state = CT_TUNER_START; in dib0090_set_params()
2582 } while (state->tune_state != CT_TUNER_STOP); in dib0090_set_params()