Lines Matching +full:0 +full:x2000
37 } while (0)
43 #define MT2063_SPUR_PRESENT_ERR (0x00800000)
46 #define MT2063_SPUR_CNT_MASK (0x001f0000)
50 #define MT2063_UPC_RANGE (0x04000000)
53 #define MT2063_DNC_RANGE (0x08000000)
65 #define MT2063_DECT_AVOID_US_FREQS 0x00000001
67 #define MT2063_DECT_AVOID_EURO_FREQS 0x00000002
69 #define MT2063_EXCLUDE_US_DECT_FREQUENCIES(s) (((s) & MT2063_DECT_AVOID_US_FREQS) != 0)
71 #define MT2063_EXCLUDE_EURO_DECT_FREQUENCIES(s) (((s) & MT2063_DECT_AVOID_EURO_FREQS) != 0)
74 MT2063_NO_DECT_AVOIDANCE = 0, /* Do not create DECT exclusion zones. */
124 MT2063_REG_SD = 0x0040, /* Shutdown regulator */
125 MT2063_SRO_SD = 0x0020, /* Shutdown SRO */
126 MT2063_AFC_SD = 0x0010, /* Shutdown AFC A/D */
127 MT2063_PD_SD = 0x0002, /* Enable power detector shutdown */
128 MT2063_PDADC_SD = 0x0001, /* Enable power detector A/D shutdown */
129 MT2063_VCO_SD = 0x8000, /* Enable VCO shutdown */
130 MT2063_LTX_SD = 0x4000, /* Enable LTX shutdown */
131 MT2063_LT1_SD = 0x2000, /* Enable LT1 shutdown */
132 MT2063_LNA_SD = 0x1000, /* Enable LNA shutdown */
133 MT2063_UPC_SD = 0x0800, /* Enable upconverter shutdown */
134 MT2063_DNC_SD = 0x0400, /* Enable downconverter shutdown */
135 MT2063_VGA_SD = 0x0200, /* Enable VGA shutdown */
136 MT2063_AMP_SD = 0x0100, /* Enable AMP shutdown */
137 MT2063_ALL_SD = 0xFF73, /* All shutdown bits for this tuner */
138 MT2063_NONE_SD = 0x0000 /* No shutdown bits */
145 MT2063_DNC_NONE = 0,
156 MT2063_REG_PART_REV = 0, /* 0x00: Part/Rev Code */
157 MT2063_REG_LO1CQ_1, /* 0x01: LO1C Queued Byte 1 */
158 MT2063_REG_LO1CQ_2, /* 0x02: LO1C Queued Byte 2 */
159 MT2063_REG_LO2CQ_1, /* 0x03: LO2C Queued Byte 1 */
160 MT2063_REG_LO2CQ_2, /* 0x04: LO2C Queued Byte 2 */
161 MT2063_REG_LO2CQ_3, /* 0x05: LO2C Queued Byte 3 */
162 MT2063_REG_RSVD_06, /* 0x06: Reserved */
163 MT2063_REG_LO_STATUS, /* 0x07: LO Status */
164 MT2063_REG_FIFFC, /* 0x08: FIFF Center */
165 MT2063_REG_CLEARTUNE, /* 0x09: ClearTune Filter */
166 MT2063_REG_ADC_OUT, /* 0x0A: ADC_OUT */
167 MT2063_REG_LO1C_1, /* 0x0B: LO1C Byte 1 */
168 MT2063_REG_LO1C_2, /* 0x0C: LO1C Byte 2 */
169 MT2063_REG_LO2C_1, /* 0x0D: LO2C Byte 1 */
170 MT2063_REG_LO2C_2, /* 0x0E: LO2C Byte 2 */
171 MT2063_REG_LO2C_3, /* 0x0F: LO2C Byte 3 */
172 MT2063_REG_RSVD_10, /* 0x10: Reserved */
173 MT2063_REG_PWR_1, /* 0x11: PWR Byte 1 */
174 MT2063_REG_PWR_2, /* 0x12: PWR Byte 2 */
175 MT2063_REG_TEMP_STATUS, /* 0x13: Temp Status */
176 MT2063_REG_XO_STATUS, /* 0x14: Crystal Status */
177 MT2063_REG_RF_STATUS, /* 0x15: RF Attn Status */
178 MT2063_REG_FIF_STATUS, /* 0x16: FIF Attn Status */
179 MT2063_REG_LNA_OV, /* 0x17: LNA Attn Override */
180 MT2063_REG_RF_OV, /* 0x18: RF Attn Override */
181 MT2063_REG_FIF_OV, /* 0x19: FIF Attn Override */
182 MT2063_REG_LNA_TGT, /* 0x1A: Reserved */
183 MT2063_REG_PD1_TGT, /* 0x1B: Pwr Det 1 Target */
184 MT2063_REG_PD2_TGT, /* 0x1C: Pwr Det 2 Target */
185 MT2063_REG_RSVD_1D, /* 0x1D: Reserved */
186 MT2063_REG_RSVD_1E, /* 0x1E: Reserved */
187 MT2063_REG_RSVD_1F, /* 0x1F: Reserved */
188 MT2063_REG_RSVD_20, /* 0x20: Reserved */
189 MT2063_REG_BYP_CTRL, /* 0x21: Bypass Control */
190 MT2063_REG_RSVD_22, /* 0x22: Reserved */
191 MT2063_REG_RSVD_23, /* 0x23: Reserved */
192 MT2063_REG_RSVD_24, /* 0x24: Reserved */
193 MT2063_REG_RSVD_25, /* 0x25: Reserved */
194 MT2063_REG_RSVD_26, /* 0x26: Reserved */
195 MT2063_REG_RSVD_27, /* 0x27: Reserved */
196 MT2063_REG_FIFF_CTRL, /* 0x28: FIFF Control */
197 MT2063_REG_FIFF_OFFSET, /* 0x29: FIFF Offset */
198 MT2063_REG_CTUNE_CTRL, /* 0x2A: Reserved */
199 MT2063_REG_CTUNE_OV, /* 0x2B: Reserved */
200 MT2063_REG_CTRL_2C, /* 0x2C: Reserved */
201 MT2063_REG_FIFF_CTRL2, /* 0x2D: Fiff Control */
202 MT2063_REG_RSVD_2E, /* 0x2E: Reserved */
203 MT2063_REG_DNC_GAIN, /* 0x2F: DNC Control */
204 MT2063_REG_VGA_GAIN, /* 0x30: VGA Gain Ctrl */
205 MT2063_REG_RSVD_31, /* 0x31: Reserved */
206 MT2063_REG_TEMP_SEL, /* 0x32: Temperature Selection */
207 MT2063_REG_RSVD_33, /* 0x33: Reserved */
208 MT2063_REG_RSVD_34, /* 0x34: Reserved */
209 MT2063_REG_RSVD_35, /* 0x35: Reserved */
210 MT2063_REG_RSVD_36, /* 0x36: Reserved */
211 MT2063_REG_RSVD_37, /* 0x37: Reserved */
212 MT2063_REG_RSVD_38, /* 0x38: Reserved */
213 MT2063_REG_RSVD_39, /* 0x39: Reserved */
214 MT2063_REG_RSVD_3A, /* 0x3A: Reserved */
215 MT2063_REG_RSVD_3B, /* 0x3B: Reserved */
216 MT2063_REG_RSVD_3C, /* 0x3C: Reserved */
255 .flags = 0, in mt2063_write()
262 msg.buf[0] = reg; in mt2063_write()
269 fe->ops.i2c_gate_ctrl(fe, 0); in mt2063_write()
271 if (ret < 0) in mt2063_write()
290 if (status < 0) in mt2063_setreg()
295 return 0; in mt2063_setreg()
304 u32 status = 0; /* Status to be returned */ in mt2063_read()
306 u32 i = 0; in mt2063_read()
308 dprintk(2, "addr 0x%02x, cnt %d\n", subAddress, cnt); in mt2063_read()
313 for (i = 0; i < cnt; i++) { in mt2063_read()
318 .flags = 0, in mt2063_read()
330 dprintk(2, "addr 0x%02x, ret = %d, val = 0x%02x\n", in mt2063_read()
332 if (status < 0) in mt2063_read()
336 fe->ops.i2c_gate_ctrl(fe, 0); in mt2063_read()
338 if (status < 0) in mt2063_read()
339 printk(KERN_ERR "Can't read from address 0x%02x,\n", in mt2063_read()
355 return 0; in MT2063_Sleep()
363 #define ceil(n, d) (((n) < 0) ? (-((-(n))/(d))) : (n)/(d) + ((n)%(d) != 0))
364 #define floor(n, d) (((n) < 0) ? (-((-(n))/(d))) - ((n)%(d) != 0) : (n)/(d))
494 pAS_Info->nZones = 0; /* this clears the used list */ in MT2063_ResetExclZones()
580 s32 j = 0; in MT2063_ChooseFirstIF()
581 u32 bDesiredExcluded = 0; in MT2063_ChooseFirstIF()
582 u32 bZeroExcluded = 0; in MT2063_ChooseFirstIF()
590 if (pAS_Info->nZones == 0) in MT2063_ChooseFirstIF()
626 if ((tmpMin < 0) && (tmpMax > 0)) in MT2063_ChooseFirstIF()
630 if ((j > 0) && (tmpMin < zones[j - 1].max_)) in MT2063_ChooseFirstIF()
644 if (bDesiredExcluded == 0) in MT2063_ChooseFirstIF()
650 if (bZeroExcluded == 0) in MT2063_ChooseFirstIF()
653 /* Find the value closest to 0 (f_Center) */ in MT2063_ChooseFirstIF()
654 bestDiff = zones[0].min_; in MT2063_ChooseFirstIF()
655 for (i = 0; i < j; i++) { in MT2063_ChooseFirstIF()
662 if (bestDiff < 0) in MT2063_ChooseFirstIF()
673 * Returns THE greatest common divisor of u and v, if either value is 0,
680 while (v != 0) { in MT2063_gcd()
695 * | ^ 0 ^ |
706 * Returns 1 if an LO spur would be present, otherwise 0.
728 *fm = 0; in IsSpurInBand()
808 return 0; in IsSpurInBand()
819 u32 status = 0; in MT2063_AvoidSpurs()
821 pAS_Info->bSpurAvoided = 0; in MT2063_AvoidSpurs()
822 pAS_Info->nSpursFound = 0; in MT2063_AvoidSpurs()
826 if (pAS_Info->maxH1 == 0) in MT2063_AvoidSpurs()
827 return 0; in MT2063_AvoidSpurs()
912 #define MT2063_LO1_FRACN_AVOID (0UL) /* LO1 FracN numerator avoid region (in Hz) */
926 #define MT2063_B0 (0x9B)
927 #define MT2063_B1 (0x9C)
928 #define MT2063_B2 (0x9D)
929 #define MT2063_B3 (0x9E)
936 * This function returns 0, if no lock, 1 if locked and a value < 1 if error
943 const u8 LO1LK = 0x80; in mt2063_lockStatus()
944 u8 LO2LK = 0x08; in mt2063_lockStatus()
946 u32 nDelays = 0; in mt2063_lockStatus()
952 LO2LK = 0x40; in mt2063_lockStatus()
958 if (status < 0) in mt2063_lockStatus()
971 return 0; in mt2063_lockStatus()
982 * Mode 0 : | MT2063_CABLE_QAM
991 * Reg Field | 0 | 1 | 2 | 3 | 4 | 5 |
994 * LNARin | 0 | 0 | 3 | 3 | 3 | 3
996 * FIFFq | 0 | 0 | 0 | 0 | 0 | 0
997 * DNC1gc | 0 | 0 | 0 | 0 | 0 | 0
998 * DNC2gc | 0 | 0 | 0 | 0 | 0 | 0
1002 * ign RF Ovl | 0 | 0 | 0 | 0 | 0 | 0
1005 * ign FIF Ovl | 0 | 0 | 0 | 0 | 0 | 0
1011 MT2063_CABLE_QAM = 0,
1029 static const u8 RFAGCEN[] = { 0, 0, 0, 0, 0, 0 };
1030 static const u8 LNARIN[] = { 0, 0, 3, 3, 3, 3 };
1032 static const u8 FIFFQ[] = { 0, 0, 0, 0, 0, 0 };
1033 static const u8 DNC1GC[] = { 0, 0, 0, 0, 0, 0 };
1034 static const u8 DNC2GC[] = { 0, 0, 0, 0, 0, 0 };
1037 static const u8 RFOVDIS[] = { 0, 0, 0, 0, 0, 0 };
1040 static const u8 FIFOVDIS[] = { 0, 0, 0, 0, 0, 0 };
1052 if ((state->reg[MT2063_REG_DNC_GAIN] & 0x03) == 0x03) { /* if DNC1 is off */ in mt2063_get_dnc_output_enable()
1053 if ((state->reg[MT2063_REG_VGA_GAIN] & 0x03) == 0x03) /* if DNC2 is off */ in mt2063_get_dnc_output_enable()
1058 if ((state->reg[MT2063_REG_VGA_GAIN] & 0x03) == 0x03) /* if DNC2 is off */ in mt2063_get_dnc_output_enable()
1063 return 0; in mt2063_get_dnc_output_enable()
1072 u32 status = 0; /* Status to be returned */ in mt2063_set_dnc_output_enable()
1073 u8 val = 0; in mt2063_set_dnc_output_enable()
1080 val = (state->reg[MT2063_REG_DNC_GAIN] & 0xFC) | 0x03; /* Set DNC1GC=3 */ in mt2063_set_dnc_output_enable()
1088 val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | 0x03; /* Set DNC2GC=3 */ in mt2063_set_dnc_output_enable()
1096 val = (state->reg[MT2063_REG_RSVD_20] & ~0x40); /* Set PD2MUX=0 */ in mt2063_set_dnc_output_enable()
1106 …val = (state->reg[MT2063_REG_DNC_GAIN] & 0xFC) | (DNC1GC[state->rcvr_mode] & 0x03); /* Set DNC1GC=… in mt2063_set_dnc_output_enable()
1114 val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | 0x03; /* Set DNC2GC=3 */ in mt2063_set_dnc_output_enable()
1122 val = (state->reg[MT2063_REG_RSVD_20] & ~0x40); /* Set PD2MUX=0 */ in mt2063_set_dnc_output_enable()
1132 val = (state->reg[MT2063_REG_DNC_GAIN] & 0xFC) | 0x03; /* Set DNC1GC=3 */ in mt2063_set_dnc_output_enable()
1140 …val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | (DNC2GC[state->rcvr_mode] & 0x03); /* Set DNC2GC=… in mt2063_set_dnc_output_enable()
1148 val = (state->reg[MT2063_REG_RSVD_20] | 0x40); /* Set PD2MUX=1 */ in mt2063_set_dnc_output_enable()
1158 …val = (state->reg[MT2063_REG_DNC_GAIN] & 0xFC) | (DNC1GC[state->rcvr_mode] & 0x03); /* Set DNC1GC=… in mt2063_set_dnc_output_enable()
1166 …val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | (DNC2GC[state->rcvr_mode] & 0x03); /* Set DNC2GC=… in mt2063_set_dnc_output_enable()
1174 val = (state->reg[MT2063_REG_RSVD_20] | 0x40); /* Set PD2MUX=1 */ in mt2063_set_dnc_output_enable()
1206 u32 status = 0; /* Status to be returned */ in MT2063_SetReceiverMode()
1216 if (status >= 0) { in MT2063_SetReceiverMode()
1219 reg[MT2063_REG_PD1_TGT] & (u8) ~0x40) | (RFAGCEN[Mode] in MT2063_SetReceiverMode()
1220 ? 0x40 : in MT2063_SetReceiverMode()
1221 0x00); in MT2063_SetReceiverMode()
1227 if (status >= 0) { in MT2063_SetReceiverMode()
1228 u8 val = (state->reg[MT2063_REG_CTRL_2C] & (u8) ~0x03) | in MT2063_SetReceiverMode()
1229 (LNARIN[Mode] & 0x03); in MT2063_SetReceiverMode()
1235 if (status >= 0) { in MT2063_SetReceiverMode()
1238 reg[MT2063_REG_FIFF_CTRL2] & (u8) ~0xF0) | in MT2063_SetReceiverMode()
1245 (state->reg[MT2063_REG_FIFF_CTRL] | (u8) 0x01); in MT2063_SetReceiverMode()
1250 reg[MT2063_REG_FIFF_CTRL] & (u8) ~0x01); in MT2063_SetReceiverMode()
1261 if (status >= 0) { in MT2063_SetReceiverMode()
1262 u8 val = (state->reg[MT2063_REG_LNA_OV] & (u8) ~0x1F) | in MT2063_SetReceiverMode()
1263 (ACLNAMAX[Mode] & 0x1F); in MT2063_SetReceiverMode()
1269 if (status >= 0) { in MT2063_SetReceiverMode()
1270 u8 val = (state->reg[MT2063_REG_LNA_TGT] & (u8) ~0x3F) | in MT2063_SetReceiverMode()
1271 (LNATGT[Mode] & 0x3F); in MT2063_SetReceiverMode()
1277 if (status >= 0) { in MT2063_SetReceiverMode()
1278 u8 val = (state->reg[MT2063_REG_RF_OV] & (u8) ~0x1F) | in MT2063_SetReceiverMode()
1279 (ACRFMAX[Mode] & 0x1F); in MT2063_SetReceiverMode()
1285 if (status >= 0) { in MT2063_SetReceiverMode()
1286 u8 val = (state->reg[MT2063_REG_PD1_TGT] & (u8) ~0x3F) | in MT2063_SetReceiverMode()
1287 (PD1TGT[Mode] & 0x3F); in MT2063_SetReceiverMode()
1293 if (status >= 0) { in MT2063_SetReceiverMode()
1297 val = (state->reg[MT2063_REG_FIF_OV] & (u8) ~0x1F) | in MT2063_SetReceiverMode()
1298 (val & 0x1F); in MT2063_SetReceiverMode()
1304 if (status >= 0) { in MT2063_SetReceiverMode()
1305 u8 val = (state->reg[MT2063_REG_PD2_TGT] & (u8) ~0x3F) | in MT2063_SetReceiverMode()
1306 (PD2TGT[Mode] & 0x3F); in MT2063_SetReceiverMode()
1312 if (status >= 0) { in MT2063_SetReceiverMode()
1313 val = (state->reg[MT2063_REG_LNA_TGT] & (u8) ~0x80) | in MT2063_SetReceiverMode()
1314 (RFOVDIS[Mode] ? 0x80 : 0x00); in MT2063_SetReceiverMode()
1320 if (status >= 0) { in MT2063_SetReceiverMode()
1321 val = (state->reg[MT2063_REG_PD1_TGT] & (u8) ~0x80) | in MT2063_SetReceiverMode()
1322 (FIFOVDIS[Mode] ? 0x80 : 0x00); in MT2063_SetReceiverMode()
1327 if (status >= 0) { in MT2063_SetReceiverMode()
1348 u32 status = 0; in MT2063_ClearPowerMaskBits()
1352 if ((Bits & 0xFF00) != 0) { in MT2063_ClearPowerMaskBits()
1359 if ((Bits & 0xFF) != 0) { in MT2063_ClearPowerMaskBits()
1360 state->reg[MT2063_REG_PWR_1] &= ~(u8) (Bits & 0xFF); in MT2063_ClearPowerMaskBits()
1381 state->reg[MT2063_REG_PWR_1] |= 0x04; in MT2063_SoftwareShutdown()
1383 state->reg[MT2063_REG_PWR_1] &= ~0x04; in MT2063_SoftwareShutdown()
1391 (state->reg[MT2063_REG_BYP_CTRL] & 0x9F) | 0x40; in MT2063_SoftwareShutdown()
1398 (state->reg[MT2063_REG_BYP_CTRL] & 0x9F); in MT2063_SoftwareShutdown()
1428 * 0x03FFF.
1439 (((f_ref & 0x00003FFF) * num + (loss << 14)) + (denom / 2)) / denom; in MT2063_fLO_FractionalTerm()
1517 * Returns: ClearTune filter number (0-31)
1528 for (idx = 0; idx < 31; ++idx) { in FindClearTuneFilter()
1543 u32 status = 0; in MT2063_Tune()
1550 u8 fiffc = 0x80; /* FIFF center freq from tuner */ in MT2063_Tune()
1552 const u8 LO1LK = 0x80; /* Mask for LO1 Lock bit */ in MT2063_Tune()
1553 u8 LO2LK = 0x08; /* Mask for LO2 Lock bit */ in MT2063_Tune()
1576 val = (state->reg[MT2063_REG_CTUNE_CTRL] | 0x08); in MT2063_Tune()
1584 (u8) ((state->reg[MT2063_REG_CTUNE_OV] & ~0x1F) in MT2063_Tune()
1595 if (status >= 0) { in MT2063_Tune()
1659 LO2LK = 0x40; in MT2063_Tune()
1680 if (fiffof > 0xFF) in MT2063_Tune()
1681 fiffof = 0xFF; in MT2063_Tune()
1687 if (status >= 0) { in MT2063_Tune()
1688 state->reg[MT2063_REG_LO1CQ_1] = (u8) (LO1 & 0xFF); /* DIV1q */ in MT2063_Tune()
1689 state->reg[MT2063_REG_LO1CQ_2] = (u8) (Num1 & 0x3F); /* NUM1q */ in MT2063_Tune()
1690 state->reg[MT2063_REG_LO2CQ_1] = (u8) (((LO2 & 0x7F) << 1) /* DIV2q */ in MT2063_Tune()
1692 state->reg[MT2063_REG_LO2CQ_2] = (u8) ((Num2 & 0x0FF0) >> 4); /* NUM2q (mid) */ in MT2063_Tune()
1693 state->reg[MT2063_REG_LO2CQ_3] = (u8) (0xE0 | (Num2 & 0x000F)); /* NUM2q (lo) */ in MT2063_Tune()
1698 * (0x05 must follow all the others). in MT2063_Tune()
1700 …s |= mt2063_write(state, MT2063_REG_LO1CQ_1, &state->reg[MT2063_REG_LO1CQ_1], 5); /* 0x01 - 0x05 */ in MT2063_Tune()
1703 … status |= mt2063_write(state, MT2063_REG_LO2CQ_3, &state->reg[MT2063_REG_LO2CQ_3], 1); /* 0x05 */ in MT2063_Tune()
1723 if (status < 0) in MT2063_Tune()
1727 if (status < 0) in MT2063_Tune()
1743 0x19, 0x05,
1744 0x1B, 0x1D,
1745 0x1C, 0x1F,
1746 0x1D, 0x0F,
1747 0x1E, 0x3F,
1748 0x1F, 0x0F,
1749 0x20, 0x3F,
1750 0x22, 0x21,
1751 0x23, 0x3F,
1752 0x24, 0x20,
1753 0x25, 0x3F,
1754 0x27, 0xEE,
1755 0x2C, 0x27, /* bit at 0x20 is cleared below */
1756 0x30, 0x03,
1757 0x2C, 0x07, /* bit at 0x20 is cleared here */
1758 0x2D, 0x87,
1759 0x2E, 0xAA,
1760 0x28, 0xE1, /* Set the FIFCrst bit here */
1761 0x28, 0xE0, /* Clear the FIFCrst bit here */
1762 0x00
1765 /* writing 0x05 0xf0 sw-resets all registers, so we write only needed changes */
1768 0x05, 0xF0,
1769 0x11, 0x10, /* New Enable AFCsd */
1770 0x19, 0x05,
1771 0x1A, 0x6C,
1772 0x1B, 0x24,
1773 0x1C, 0x28,
1774 0x1D, 0x8F,
1775 0x1E, 0x14,
1776 0x1F, 0x8F,
1777 0x20, 0x57,
1778 0x22, 0x21, /* New - ver 1.03 */
1779 0x23, 0x3C, /* New - ver 1.10 */
1780 0x24, 0x20, /* New - ver 1.03 */
1781 0x2C, 0x24, /* bit at 0x20 is cleared below */
1782 0x2D, 0x87, /* FIFFQ=0 */
1783 0x2F, 0xF3,
1784 0x30, 0x0C, /* New - ver 1.11 */
1785 0x31, 0x1B, /* New - ver 1.11 */
1786 0x2C, 0x04, /* bit at 0x20 is cleared here */
1787 0x28, 0xE1, /* Set the FIFCrst bit here */
1788 0x28, 0xE0, /* Clear the FIFCrst bit here */
1789 0x00
1792 /* writing 0x05 0xf0 sw-resets all registers, so we write only needed changes */
1795 0x05, 0xF0,
1796 0x19, 0x3D,
1797 0x2C, 0x24, /* bit at 0x20 is cleared below */
1798 0x2C, 0x04, /* bit at 0x20 is cleared here */
1799 0x28, 0xE1, /* Set the FIFCrst bit here */
1800 0x28, 0xE0, /* Clear the FIFCrst bit here */
1801 0x00
1808 u8 all_resets = 0xF0; /* reset/load bits */ in mt2063_init()
1823 if (status < 0) { in mt2063_init()
1843 printk(KERN_ERR "mt2063: Unknown mt2063 device ID (0x%02x)\n", in mt2063_init()
1852 /* b7 != 0 ==> NOT MT2063 */ in mt2063_init()
1853 if (status < 0 || ((state->reg[MT2063_REG_RSVD_3B] & 0x80) != 0x00)) { in mt2063_init()
1854 printk(KERN_ERR "mt2063: Unknown part ID (0x%02x%02x)\n", in mt2063_init()
1864 if (status < 0) in mt2063_init()
1887 while (status >= 0 && *def) { in mt2063_init()
1892 if (status < 0) in mt2063_init()
1898 while (status >= 0 && (FCRUN != 0) && (maxReads-- > 0)) { in mt2063_init()
1904 FCRUN = (state->reg[MT2063_REG_XO_STATUS] & 0x40) >> 6; in mt2063_init()
1907 if (FCRUN != 0 || status < 0) in mt2063_init()
1913 if (status < 0) in mt2063_init()
1920 if (status < 0) in mt2063_init()
1946 state->ctfilt_sw = 0; in mt2063_init()
1948 state->CTFiltMax[0] = 69230000; in mt2063_init()
1985 state->reg[MT2063_REG_CTUNE_CTRL] = 0x0A; in mt2063_init()
1988 if (status < 0) in mt2063_init()
1994 if (status < 0) in mt2063_init()
1999 state->reg[MT2063_REG_CTUNE_CTRL] = 0x00; in mt2063_init()
2002 if (status < 0) in mt2063_init()
2006 for (i = 0; i < 31; i++) in mt2063_init()
2010 if (status < 0) in mt2063_init()
2013 if (status < 0) in mt2063_init()
2018 return 0; in mt2063_init()
2031 *tuner_status = 0; in mt2063_get_status()
2033 if (status < 0) in mt2063_get_status()
2040 return 0; in mt2063_get_status()
2052 return 0; in mt2063_release()
2070 if (status < 0) in mt2063_set_analog_params()
2106 if (status < 0) in mt2063_set_analog_params()
2113 if (status < 0) in mt2063_set_analog_params()
2117 return 0; in mt2063_set_analog_params()
2142 if (status < 0) in mt2063_set_params()
2148 if (c->bandwidth_hz == 0) in mt2063_set_params()
2178 if (status < 0) in mt2063_set_params()
2186 if (status < 0) in mt2063_set_params()
2190 return 0; in mt2063_set_params()
2206 return 0; in mt2063_get_if_frequency()
2222 return 0; in mt2063_get_bandwidth()
2230 .frequency_step = 0,
2278 int err = 0; in tuner_MT2063_SoftwareShutdown()
2283 if (err < 0) in tuner_MT2063_SoftwareShutdown()
2293 int err = 0; in tuner_MT2063_ClearPowerMaskBits()
2298 if (err < 0) in tuner_MT2063_ClearPowerMaskBits()