Lines Matching +full:cs +full:- +full:3
3 * low level stuff for ITK ix1-micro Rev.2 isdn cards
6 * Author Klaus-Peter Nischke
7 * Copyright by Klaus-Peter Nischke, ITK AG
14 * Klaus-Peter Nischke
32 #define SPECIAL_PORT_OFFSET 3
76 ReadISAC(struct IsdnCardState *cs, u_char offset) in ReadISAC() argument
78 return (readreg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, offset)); in ReadISAC()
82 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) in WriteISAC() argument
84 writereg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, offset, value); in WriteISAC()
88 ReadISACfifo(struct IsdnCardState *cs, u_char * data, int size) in ReadISACfifo() argument
90 readfifo(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, 0, data, size); in ReadISACfifo()
94 WriteISACfifo(struct IsdnCardState *cs, u_char * data, int size) in WriteISACfifo() argument
96 writefifo(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, 0, data, size); in WriteISACfifo()
100 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) in ReadHSCX() argument
102 return (readreg(cs->hw.ix1.hscx_ale, in ReadHSCX()
103 cs->hw.ix1.hscx, offset + (hscx ? 0x40 : 0))); in ReadHSCX()
107 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) in WriteHSCX() argument
109 writereg(cs->hw.ix1.hscx_ale, in WriteHSCX()
110 cs->hw.ix1.hscx, offset + (hscx ? 0x40 : 0), value); in WriteHSCX()
113 #define READHSCX(cs, nr, reg) readreg(cs->hw.ix1.hscx_ale, \ argument
114 cs->hw.ix1.hscx, reg + (nr ? 0x40 : 0))
115 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.ix1.hscx_ale, \ argument
116 cs->hw.ix1.hscx, reg + (nr ? 0x40 : 0), data)
118 #define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs->hw.ix1.hscx_ale, \ argument
119 cs->hw.ix1.hscx, (nr ? 0x40 : 0), ptr, cnt)
121 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs->hw.ix1.hscx_ale, \ argument
122 cs->hw.ix1.hscx, (nr ? 0x40 : 0), ptr, cnt)
129 struct IsdnCardState *cs = dev_id; in ix1micro_interrupt() local
133 spin_lock_irqsave(&cs->lock, flags); in ix1micro_interrupt()
134 val = readreg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_ISTA + 0x40); in ix1micro_interrupt()
137 hscx_int_main(cs, val); in ix1micro_interrupt()
138 val = readreg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, ISAC_ISTA); in ix1micro_interrupt()
141 isac_interrupt(cs, val); in ix1micro_interrupt()
142 val = readreg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_ISTA + 0x40); in ix1micro_interrupt()
144 if (cs->debug & L1_DEB_HSCX) in ix1micro_interrupt()
145 debugl1(cs, "HSCX IntStat after IntRoutine"); in ix1micro_interrupt()
148 val = readreg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, ISAC_ISTA); in ix1micro_interrupt()
150 if (cs->debug & L1_DEB_ISAC) in ix1micro_interrupt()
151 debugl1(cs, "ISAC IntStat after IntRoutine"); in ix1micro_interrupt()
154 writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK, 0xFF); in ix1micro_interrupt()
155 writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK + 0x40, 0xFF); in ix1micro_interrupt()
156 writereg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, ISAC_MASK, 0xFF); in ix1micro_interrupt()
157 writereg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, ISAC_MASK, 0); in ix1micro_interrupt()
158 writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK, 0); in ix1micro_interrupt()
159 writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK + 0x40, 0); in ix1micro_interrupt()
160 spin_unlock_irqrestore(&cs->lock, flags); in ix1micro_interrupt()
165 release_io_ix1micro(struct IsdnCardState *cs) in release_io_ix1micro() argument
167 if (cs->hw.ix1.cfg_reg) in release_io_ix1micro()
168 release_region(cs->hw.ix1.cfg_reg, 4); in release_io_ix1micro()
172 ix1_reset(struct IsdnCardState *cs) in ix1_reset() argument
177 cnt = 3 * (HZ / 10) + 1; in ix1_reset()
178 while (cnt--) { in ix1_reset()
179 byteout(cs->hw.ix1.cfg_reg + SPECIAL_PORT_OFFSET, 1); in ix1_reset()
182 byteout(cs->hw.ix1.cfg_reg + SPECIAL_PORT_OFFSET, 0); in ix1_reset()
186 ix1_card_msg(struct IsdnCardState *cs, int mt, void *arg) in ix1_card_msg() argument
192 spin_lock_irqsave(&cs->lock, flags); in ix1_card_msg()
193 ix1_reset(cs); in ix1_card_msg()
194 spin_unlock_irqrestore(&cs->lock, flags); in ix1_card_msg()
197 release_io_ix1micro(cs); in ix1_card_msg()
200 spin_lock_irqsave(&cs->lock, flags); in ix1_card_msg()
201 ix1_reset(cs); in ix1_card_msg()
202 inithscxisac(cs, 3); in ix1_card_msg()
203 spin_unlock_irqrestore(&cs->lock, flags); in ix1_card_msg()
230 struct IsdnCardState *cs = card->cs; in setup_ix1micro() local
235 if (cs->typ != ISDN_CTYPE_IX1MICROR2) in setup_ix1micro()
239 if (!card->para[1] && isapnp_present()) { in setup_ix1micro()
241 while(ipid->card_vendor) { in setup_ix1micro()
242 if ((pnp_c = pnp_find_card(ipid->card_vendor, in setup_ix1micro()
243 ipid->card_device, pnp_c))) { in setup_ix1micro()
246 ipid->vendor, ipid->function, pnp_d))) { in setup_ix1micro()
250 (char *)ipid->driver_data); in setup_ix1micro()
258 card->para[1] = pnp_port_start(pnp_d, 0); in setup_ix1micro()
259 card->para[0] = pnp_irq(pnp_d, 0); in setup_ix1micro()
260 if (!card->para[0] || !card->para[1]) { in setup_ix1micro()
262 card->para[0], card->para[1]); in setup_ix1micro()
274 if (!ipid->card_vendor) { in setup_ix1micro()
280 /* IO-Ports */ in setup_ix1micro()
281 cs->hw.ix1.isac_ale = card->para[1] + ISAC_COMMAND_OFFSET; in setup_ix1micro()
282 cs->hw.ix1.hscx_ale = card->para[1] + HSCX_COMMAND_OFFSET; in setup_ix1micro()
283 cs->hw.ix1.isac = card->para[1] + ISAC_DATA_OFFSET; in setup_ix1micro()
284 cs->hw.ix1.hscx = card->para[1] + HSCX_DATA_OFFSET; in setup_ix1micro()
285 cs->hw.ix1.cfg_reg = card->para[1]; in setup_ix1micro()
286 cs->irq = card->para[0]; in setup_ix1micro()
287 if (cs->hw.ix1.cfg_reg) { in setup_ix1micro()
288 if (!request_region(cs->hw.ix1.cfg_reg, 4, "ix1micro cfg")) { in setup_ix1micro()
290 "HiSax: ITK ix1-micro Rev.2 config port " in setup_ix1micro()
291 "%x-%x already in use\n", in setup_ix1micro()
292 cs->hw.ix1.cfg_reg, in setup_ix1micro()
293 cs->hw.ix1.cfg_reg + 4); in setup_ix1micro()
297 printk(KERN_INFO "HiSax: ITK ix1-micro Rev.2 config irq:%d io:0x%X\n", in setup_ix1micro()
298 cs->irq, cs->hw.ix1.cfg_reg); in setup_ix1micro()
299 setup_isac(cs); in setup_ix1micro()
300 cs->readisac = &ReadISAC; in setup_ix1micro()
301 cs->writeisac = &WriteISAC; in setup_ix1micro()
302 cs->readisacfifo = &ReadISACfifo; in setup_ix1micro()
303 cs->writeisacfifo = &WriteISACfifo; in setup_ix1micro()
304 cs->BC_Read_Reg = &ReadHSCX; in setup_ix1micro()
305 cs->BC_Write_Reg = &WriteHSCX; in setup_ix1micro()
306 cs->BC_Send_Data = &hscx_fill_fifo; in setup_ix1micro()
307 cs->cardmsg = &ix1_card_msg; in setup_ix1micro()
308 cs->irq_func = &ix1micro_interrupt; in setup_ix1micro()
309 ISACVersion(cs, "ix1-Micro:"); in setup_ix1micro()
310 if (HscxVersion(cs, "ix1-Micro:")) { in setup_ix1micro()
312 "ix1-Micro: wrong HSCX versions check IO address\n"); in setup_ix1micro()
313 release_io_ix1micro(cs); in setup_ix1micro()