Lines Matching +full:cs +full:- +full:3
22 {"A1", "?1", "A2", "?3", "A3", "V2.1", "?6", "?7",
26 HscxVersion(struct IsdnCardState *cs, char *s) in HscxVersion() argument
30 verA = cs->BC_Read_Reg(cs, 0, HSCX_VSTR) & 0xf; in HscxVersion()
31 verB = cs->BC_Read_Reg(cs, 1, HSCX_VSTR) & 0xf; in HscxVersion()
43 struct IsdnCardState *cs = bcs->cs; in modehscx() local
44 int hscx = bcs->hw.hscx.hscx; in modehscx()
46 if (cs->debug & L1_DEB_HSCX) in modehscx()
47 debugl1(cs, "hscx %c mode %d ichan %d", in modehscx()
49 bcs->mode = mode; in modehscx()
50 bcs->channel = bc; in modehscx()
51 cs->BC_Write_Reg(cs, hscx, HSCX_XAD1, 0xFF); in modehscx()
52 cs->BC_Write_Reg(cs, hscx, HSCX_XAD2, 0xFF); in modehscx()
53 cs->BC_Write_Reg(cs, hscx, HSCX_RAH2, 0xFF); in modehscx()
54 cs->BC_Write_Reg(cs, hscx, HSCX_XBCH, 0x0); in modehscx()
55 cs->BC_Write_Reg(cs, hscx, HSCX_RLCR, 0x0); in modehscx()
56 cs->BC_Write_Reg(cs, hscx, HSCX_CCR1, in modehscx()
57 test_bit(HW_IPAC, &cs->HW_Flags) ? 0x82 : 0x85); in modehscx()
58 cs->BC_Write_Reg(cs, hscx, HSCX_CCR2, 0x30); in modehscx()
59 cs->BC_Write_Reg(cs, hscx, HSCX_XCCR, 7); in modehscx()
60 cs->BC_Write_Reg(cs, hscx, HSCX_RCCR, 7); in modehscx()
63 if (test_bit(HW_IOM1, &cs->HW_Flags) && (hscx == 0)) in modehscx()
64 bc = 1 - bc; in modehscx()
67 cs->BC_Write_Reg(cs, hscx, HSCX_TSAX, in modehscx()
68 test_bit(HW_IOM1, &cs->HW_Flags) ? 0x7 : bcs->hw.hscx.tsaxr0); in modehscx()
69 cs->BC_Write_Reg(cs, hscx, HSCX_TSAR, in modehscx()
70 test_bit(HW_IOM1, &cs->HW_Flags) ? 0x7 : bcs->hw.hscx.tsaxr0); in modehscx()
72 cs->BC_Write_Reg(cs, hscx, HSCX_TSAX, bcs->hw.hscx.tsaxr1); in modehscx()
73 cs->BC_Write_Reg(cs, hscx, HSCX_TSAR, bcs->hw.hscx.tsaxr1); in modehscx()
77 cs->BC_Write_Reg(cs, hscx, HSCX_TSAX, 0x1f); in modehscx()
78 cs->BC_Write_Reg(cs, hscx, HSCX_TSAR, 0x1f); in modehscx()
79 cs->BC_Write_Reg(cs, hscx, HSCX_MODE, 0x84); in modehscx()
82 cs->BC_Write_Reg(cs, hscx, HSCX_MODE, 0xe4); in modehscx()
85 cs->BC_Write_Reg(cs, hscx, HSCX_CCR1, in modehscx()
86 test_bit(HW_IPAC, &cs->HW_Flags) ? 0x8a : 0x8d); in modehscx()
87 cs->BC_Write_Reg(cs, hscx, HSCX_MODE, 0x8c); in modehscx()
91 cs->BC_Write_Reg(cs, hscx, HSCX_CMDR, 0x41); in modehscx()
92 cs->BC_Write_Reg(cs, hscx, HSCX_ISTA, 0x00); in modehscx()
98 struct BCState *bcs = st->l1.bcs; in hscx_l2l1()
104 spin_lock_irqsave(&bcs->cs->lock, flags); in hscx_l2l1()
105 if (bcs->tx_skb) { in hscx_l2l1()
106 skb_queue_tail(&bcs->squeue, skb); in hscx_l2l1()
108 bcs->tx_skb = skb; in hscx_l2l1()
109 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag); in hscx_l2l1()
110 bcs->hw.hscx.count = 0; in hscx_l2l1()
111 bcs->cs->BC_Send_Data(bcs); in hscx_l2l1()
113 spin_unlock_irqrestore(&bcs->cs->lock, flags); in hscx_l2l1()
116 spin_lock_irqsave(&bcs->cs->lock, flags); in hscx_l2l1()
117 if (bcs->tx_skb) { in hscx_l2l1()
120 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag); in hscx_l2l1()
121 bcs->tx_skb = skb; in hscx_l2l1()
122 bcs->hw.hscx.count = 0; in hscx_l2l1()
123 bcs->cs->BC_Send_Data(bcs); in hscx_l2l1()
125 spin_unlock_irqrestore(&bcs->cs->lock, flags); in hscx_l2l1()
128 if (!bcs->tx_skb) { in hscx_l2l1()
129 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags); in hscx_l2l1()
130 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL); in hscx_l2l1()
132 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags); in hscx_l2l1()
135 spin_lock_irqsave(&bcs->cs->lock, flags); in hscx_l2l1()
136 test_and_set_bit(BC_FLG_ACTIV, &bcs->Flag); in hscx_l2l1()
137 modehscx(bcs, st->l1.mode, st->l1.bc); in hscx_l2l1()
138 spin_unlock_irqrestore(&bcs->cs->lock, flags); in hscx_l2l1()
145 spin_lock_irqsave(&bcs->cs->lock, flags); in hscx_l2l1()
146 test_and_clear_bit(BC_FLG_ACTIV, &bcs->Flag); in hscx_l2l1()
147 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag); in hscx_l2l1()
148 modehscx(bcs, 0, st->l1.bc); in hscx_l2l1()
149 spin_unlock_irqrestore(&bcs->cs->lock, flags); in hscx_l2l1()
150 st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL); in hscx_l2l1()
158 modehscx(bcs, 0, bcs->channel); in close_hscxstate()
159 if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) { in close_hscxstate()
160 kfree(bcs->hw.hscx.rcvbuf); in close_hscxstate()
161 bcs->hw.hscx.rcvbuf = NULL; in close_hscxstate()
162 kfree(bcs->blog); in close_hscxstate()
163 bcs->blog = NULL; in close_hscxstate()
164 skb_queue_purge(&bcs->rqueue); in close_hscxstate()
165 skb_queue_purge(&bcs->squeue); in close_hscxstate()
166 if (bcs->tx_skb) { in close_hscxstate()
167 dev_kfree_skb_any(bcs->tx_skb); in close_hscxstate()
168 bcs->tx_skb = NULL; in close_hscxstate()
169 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag); in close_hscxstate()
175 open_hscxstate(struct IsdnCardState *cs, struct BCState *bcs) in open_hscxstate() argument
177 if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) { in open_hscxstate()
178 if (!(bcs->hw.hscx.rcvbuf = kmalloc(HSCX_BUFMAX, GFP_ATOMIC))) { in open_hscxstate()
181 test_and_clear_bit(BC_FLG_INIT, &bcs->Flag); in open_hscxstate()
184 if (!(bcs->blog = kmalloc(MAX_BLOG_SPACE, GFP_ATOMIC))) { in open_hscxstate()
186 "HiSax: No memory for bcs->blog\n"); in open_hscxstate()
187 test_and_clear_bit(BC_FLG_INIT, &bcs->Flag); in open_hscxstate()
188 kfree(bcs->hw.hscx.rcvbuf); in open_hscxstate()
189 bcs->hw.hscx.rcvbuf = NULL; in open_hscxstate()
192 skb_queue_head_init(&bcs->rqueue); in open_hscxstate()
193 skb_queue_head_init(&bcs->squeue); in open_hscxstate()
195 bcs->tx_skb = NULL; in open_hscxstate()
196 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag); in open_hscxstate()
197 bcs->event = 0; in open_hscxstate()
198 bcs->hw.hscx.rcvidx = 0; in open_hscxstate()
199 bcs->tx_cnt = 0; in open_hscxstate()
206 bcs->channel = st->l1.bc; in setstack_hscx()
207 if (open_hscxstate(st->l1.hardware, bcs)) in setstack_hscx()
208 return (-1); in setstack_hscx()
209 st->l1.bcs = bcs; in setstack_hscx()
210 st->l2.l2l1 = hscx_l2l1; in setstack_hscx()
212 bcs->st = st; in setstack_hscx()
218 clear_pending_hscx_ints(struct IsdnCardState *cs) in clear_pending_hscx_ints() argument
222 val = cs->BC_Read_Reg(cs, 1, HSCX_ISTA); in clear_pending_hscx_ints()
223 debugl1(cs, "HSCX B ISTA %x", val); in clear_pending_hscx_ints()
225 eval = cs->BC_Read_Reg(cs, 1, HSCX_EXIR); in clear_pending_hscx_ints()
226 debugl1(cs, "HSCX B EXIR %x", eval); in clear_pending_hscx_ints()
229 eval = cs->BC_Read_Reg(cs, 0, HSCX_EXIR); in clear_pending_hscx_ints()
230 debugl1(cs, "HSCX A EXIR %x", eval); in clear_pending_hscx_ints()
232 val = cs->BC_Read_Reg(cs, 0, HSCX_ISTA); in clear_pending_hscx_ints()
233 debugl1(cs, "HSCX A ISTA %x", val); in clear_pending_hscx_ints()
234 val = cs->BC_Read_Reg(cs, 1, HSCX_STAR); in clear_pending_hscx_ints()
235 debugl1(cs, "HSCX B STAR %x", val); in clear_pending_hscx_ints()
236 val = cs->BC_Read_Reg(cs, 0, HSCX_STAR); in clear_pending_hscx_ints()
237 debugl1(cs, "HSCX A STAR %x", val); in clear_pending_hscx_ints()
239 cs->BC_Write_Reg(cs, 0, HSCX_MASK, 0xFF); in clear_pending_hscx_ints()
240 cs->BC_Write_Reg(cs, 1, HSCX_MASK, 0xFF); in clear_pending_hscx_ints()
244 inithscx(struct IsdnCardState *cs) in inithscx() argument
246 cs->bcs[0].BC_SetStack = setstack_hscx; in inithscx()
247 cs->bcs[1].BC_SetStack = setstack_hscx; in inithscx()
248 cs->bcs[0].BC_Close = close_hscxstate; in inithscx()
249 cs->bcs[1].BC_Close = close_hscxstate; in inithscx()
250 cs->bcs[0].hw.hscx.hscx = 0; in inithscx()
251 cs->bcs[1].hw.hscx.hscx = 1; in inithscx()
252 cs->bcs[0].hw.hscx.tsaxr0 = 0x2f; in inithscx()
253 cs->bcs[0].hw.hscx.tsaxr1 = 3; in inithscx()
254 cs->bcs[1].hw.hscx.tsaxr0 = 0x2f; in inithscx()
255 cs->bcs[1].hw.hscx.tsaxr1 = 3; in inithscx()
256 modehscx(cs->bcs, 0, 0); in inithscx()
257 modehscx(cs->bcs + 1, 0, 0); in inithscx()
261 inithscxisac(struct IsdnCardState *cs, int part) in inithscxisac() argument
264 clear_pending_isac_ints(cs); in inithscxisac()
265 clear_pending_hscx_ints(cs); in inithscxisac()
266 initisac(cs); in inithscxisac()
267 inithscx(cs); in inithscxisac()
271 cs->writeisac(cs, ISAC_MASK, 0); in inithscxisac()
272 cs->BC_Write_Reg(cs, 0, HSCX_MASK, 0); in inithscxisac()
273 cs->BC_Write_Reg(cs, 1, HSCX_MASK, 0); in inithscxisac()
275 cs->writeisac(cs, ISAC_CMDR, 0x41); in inithscxisac()