64 	u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);  in rs600_page_flip()  local
98 	u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl;  in rs600_pm_misc()  local
192 	u32 tmp;  in rs600_pm_prepare()  local
210 	u32 tmp;  in rs600_pm_finish()  local
226 	u32 tmp;  in rs600_hpd_sense()  local
249 	u32 tmp;  in rs600_hpd_set_polarity()  local
328 	u32 status, tmp;  in rs600_asic_reset()  local
393 	uint32_t tmp;  in rs600_gart_tlb_flush()  local
428 	u32 tmp;  in rs600_gart_enable()  local
493 	u32 tmp;  in rs600_gart_disable()  local
531 	uint32_t tmp = 0;  in rs600_irq_set()  local
574 	u32 tmp;  in rs600_irq_ack()  local