Lines Matching defs:drm_radeon_private
190 typedef struct drm_radeon_private { struct
191 drm_radeon_ring_buffer_t ring;
193 u32 fb_location;
194 u32 fb_size;
195 int new_memmap;
197 int gart_size;
198 u32 gart_vm_start;
199 unsigned long gart_buffers_offset;
201 int cp_mode;
202 int cp_running;
204 drm_radeon_freelist_t *head;
205 drm_radeon_freelist_t *tail;
206 int last_buf;
207 int writeback_works;
209 int usec_timeout;
211 int microcode_version;
213 struct {
222 } stats;
224 int do_boxes;
225 int page_flipping;
227 u32 color_fmt;
228 unsigned int front_offset;
229 unsigned int front_pitch;
230 unsigned int back_offset;
231 unsigned int back_pitch;
233 u32 depth_fmt;
234 unsigned int depth_offset;
235 unsigned int depth_pitch;
237 u32 front_pitch_offset;
238 u32 back_pitch_offset;
239 u32 depth_pitch_offset;
241 drm_radeon_depth_clear_t depth_clear;
243 unsigned long ring_offset;
244 unsigned long ring_rptr_offset;
245 unsigned long buffers_offset;
246 unsigned long gart_textures_offset;
248 drm_local_map_t *sarea;
249 drm_local_map_t *cp_ring;
250 drm_local_map_t *ring_rptr;
251 drm_local_map_t *gart_textures;
253 struct mem_block *gart_heap;
254 struct mem_block *fb_heap;
257 wait_queue_head_t swi_queue;
258 atomic_t swi_emitted;
259 int vblank_crtc;
260 uint32_t irq_enable_reg;
261 uint32_t r500_disp_irq_reg;
263 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
264 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
266 unsigned long pcigart_offset;
267 unsigned int pcigart_offset_set;
268 struct drm_ati_pcigart_info gart_info;
270 u32 scratch_ages[5];
272 int have_z_offset;
275 uint32_t flags; /* see radeon_chip_flags */
276 resource_size_t fb_aper_offset;
278 int num_gb_pipes;
279 int num_z_pipes;
280 int track_flush;
281 drm_local_map_t *mmio;
284 int r600_max_pipes;
285 int r600_max_tile_pipes;
286 int r600_max_simds;
287 int r600_max_backends;
288 int r600_max_gprs;
289 int r600_max_threads;
313 } drm_radeon_private_t; argument