Lines Matching +full:is +full:- +full:decoded +full:- +full:cs
6 * Permission is hereby granted, free of charge, to any person obtaining a
11 * Software is furnished to do so, subject to the following conditions:
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
113 actual_temp -= 256; in rv6xx_get_temp()
122 rdev->pm.dynpm_can_upclock = true; in r600_pm_get_dynpm_state()
123 rdev->pm.dynpm_can_downclock = true; in r600_pm_get_dynpm_state()
125 /* power state array is low to high, default is first */ in r600_pm_get_dynpm_state()
126 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) { in r600_pm_get_dynpm_state()
129 if (rdev->pm.num_power_states > 2) in r600_pm_get_dynpm_state()
132 switch (rdev->pm.dynpm_planned_action) { in r600_pm_get_dynpm_state()
134 rdev->pm.requested_power_state_index = min_power_state_index; in r600_pm_get_dynpm_state()
135 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
136 rdev->pm.dynpm_can_downclock = false; in r600_pm_get_dynpm_state()
139 if (rdev->pm.current_power_state_index == min_power_state_index) { in r600_pm_get_dynpm_state()
140 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; in r600_pm_get_dynpm_state()
141 rdev->pm.dynpm_can_downclock = false; in r600_pm_get_dynpm_state()
143 if (rdev->pm.active_crtc_count > 1) { in r600_pm_get_dynpm_state()
144 for (i = 0; i < rdev->pm.num_power_states; i++) { in r600_pm_get_dynpm_state()
145 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) in r600_pm_get_dynpm_state()
147 else if (i >= rdev->pm.current_power_state_index) { in r600_pm_get_dynpm_state()
148 rdev->pm.requested_power_state_index = in r600_pm_get_dynpm_state()
149 rdev->pm.current_power_state_index; in r600_pm_get_dynpm_state()
152 rdev->pm.requested_power_state_index = i; in r600_pm_get_dynpm_state()
157 if (rdev->pm.current_power_state_index == 0) in r600_pm_get_dynpm_state()
158 rdev->pm.requested_power_state_index = in r600_pm_get_dynpm_state()
159 rdev->pm.num_power_states - 1; in r600_pm_get_dynpm_state()
161 rdev->pm.requested_power_state_index = in r600_pm_get_dynpm_state()
162 rdev->pm.current_power_state_index - 1; in r600_pm_get_dynpm_state()
165 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
166 /* don't use the power state if crtcs are active and no display flag is set */ in r600_pm_get_dynpm_state()
167 if ((rdev->pm.active_crtc_count > 0) && in r600_pm_get_dynpm_state()
168 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r600_pm_get_dynpm_state()
169 clock_info[rdev->pm.requested_clock_mode_index].flags & in r600_pm_get_dynpm_state()
171 rdev->pm.requested_power_state_index++; in r600_pm_get_dynpm_state()
175 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { in r600_pm_get_dynpm_state()
176 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; in r600_pm_get_dynpm_state()
177 rdev->pm.dynpm_can_upclock = false; in r600_pm_get_dynpm_state()
179 if (rdev->pm.active_crtc_count > 1) { in r600_pm_get_dynpm_state()
180 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { in r600_pm_get_dynpm_state()
181 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) in r600_pm_get_dynpm_state()
183 else if (i <= rdev->pm.current_power_state_index) { in r600_pm_get_dynpm_state()
184 rdev->pm.requested_power_state_index = in r600_pm_get_dynpm_state()
185 rdev->pm.current_power_state_index; in r600_pm_get_dynpm_state()
188 rdev->pm.requested_power_state_index = i; in r600_pm_get_dynpm_state()
193 rdev->pm.requested_power_state_index = in r600_pm_get_dynpm_state()
194 rdev->pm.current_power_state_index + 1; in r600_pm_get_dynpm_state()
196 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
199 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; in r600_pm_get_dynpm_state()
200 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
201 rdev->pm.dynpm_can_upclock = false; in r600_pm_get_dynpm_state()
211 /* power state array is low to high, default is first (0) */ in r600_pm_get_dynpm_state()
212 if (rdev->pm.active_crtc_count > 1) { in r600_pm_get_dynpm_state()
213 rdev->pm.requested_power_state_index = -1; in r600_pm_get_dynpm_state()
215 for (i = 1; i < rdev->pm.num_power_states; i++) { in r600_pm_get_dynpm_state()
216 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) in r600_pm_get_dynpm_state()
218 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) || in r600_pm_get_dynpm_state()
219 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) { in r600_pm_get_dynpm_state()
220 rdev->pm.requested_power_state_index = i; in r600_pm_get_dynpm_state()
225 if (rdev->pm.requested_power_state_index == -1) in r600_pm_get_dynpm_state()
226 rdev->pm.requested_power_state_index = 0; in r600_pm_get_dynpm_state()
228 rdev->pm.requested_power_state_index = 1; in r600_pm_get_dynpm_state()
230 switch (rdev->pm.dynpm_planned_action) { in r600_pm_get_dynpm_state()
232 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
233 rdev->pm.dynpm_can_downclock = false; in r600_pm_get_dynpm_state()
236 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { in r600_pm_get_dynpm_state()
237 if (rdev->pm.current_clock_mode_index == 0) { in r600_pm_get_dynpm_state()
238 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
239 rdev->pm.dynpm_can_downclock = false; in r600_pm_get_dynpm_state()
241 rdev->pm.requested_clock_mode_index = in r600_pm_get_dynpm_state()
242 rdev->pm.current_clock_mode_index - 1; in r600_pm_get_dynpm_state()
244 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
245 rdev->pm.dynpm_can_downclock = false; in r600_pm_get_dynpm_state()
247 /* don't use the power state if crtcs are active and no display flag is set */ in r600_pm_get_dynpm_state()
248 if ((rdev->pm.active_crtc_count > 0) && in r600_pm_get_dynpm_state()
249 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r600_pm_get_dynpm_state()
250 clock_info[rdev->pm.requested_clock_mode_index].flags & in r600_pm_get_dynpm_state()
252 rdev->pm.requested_clock_mode_index++; in r600_pm_get_dynpm_state()
256 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { in r600_pm_get_dynpm_state()
257 if (rdev->pm.current_clock_mode_index == in r600_pm_get_dynpm_state()
258 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) { in r600_pm_get_dynpm_state()
259 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index; in r600_pm_get_dynpm_state()
260 rdev->pm.dynpm_can_upclock = false; in r600_pm_get_dynpm_state()
262 rdev->pm.requested_clock_mode_index = in r600_pm_get_dynpm_state()
263 rdev->pm.current_clock_mode_index + 1; in r600_pm_get_dynpm_state()
265 rdev->pm.requested_clock_mode_index = in r600_pm_get_dynpm_state()
266 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1; in r600_pm_get_dynpm_state()
267 rdev->pm.dynpm_can_upclock = false; in r600_pm_get_dynpm_state()
271 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; in r600_pm_get_dynpm_state()
272 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
273 rdev->pm.dynpm_can_upclock = false; in r600_pm_get_dynpm_state()
283 rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r600_pm_get_dynpm_state()
284 clock_info[rdev->pm.requested_clock_mode_index].sclk, in r600_pm_get_dynpm_state()
285 rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r600_pm_get_dynpm_state()
286 clock_info[rdev->pm.requested_clock_mode_index].mclk, in r600_pm_get_dynpm_state()
287 rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r600_pm_get_dynpm_state()
293 if (rdev->pm.num_power_states == 2) { in rs780_pm_init_profile()
295 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in rs780_pm_init_profile()
296 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in rs780_pm_init_profile()
297 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
298 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
300 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; in rs780_pm_init_profile()
301 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; in rs780_pm_init_profile()
302 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
303 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
305 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; in rs780_pm_init_profile()
306 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; in rs780_pm_init_profile()
307 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
308 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
310 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; in rs780_pm_init_profile()
311 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; in rs780_pm_init_profile()
312 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
313 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
315 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; in rs780_pm_init_profile()
316 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; in rs780_pm_init_profile()
317 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
318 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
320 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; in rs780_pm_init_profile()
321 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; in rs780_pm_init_profile()
322 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
323 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
325 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; in rs780_pm_init_profile()
326 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1; in rs780_pm_init_profile()
327 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
328 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
329 } else if (rdev->pm.num_power_states == 3) { in rs780_pm_init_profile()
331 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in rs780_pm_init_profile()
332 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in rs780_pm_init_profile()
333 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
334 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
336 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; in rs780_pm_init_profile()
337 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; in rs780_pm_init_profile()
338 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
339 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
341 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; in rs780_pm_init_profile()
342 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; in rs780_pm_init_profile()
343 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
344 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
346 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; in rs780_pm_init_profile()
347 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2; in rs780_pm_init_profile()
348 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
349 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
351 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1; in rs780_pm_init_profile()
352 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1; in rs780_pm_init_profile()
353 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
354 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
356 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1; in rs780_pm_init_profile()
357 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1; in rs780_pm_init_profile()
358 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
359 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
361 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1; in rs780_pm_init_profile()
362 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; in rs780_pm_init_profile()
363 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
364 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
367 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in rs780_pm_init_profile()
368 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in rs780_pm_init_profile()
369 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
370 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
372 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2; in rs780_pm_init_profile()
373 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2; in rs780_pm_init_profile()
374 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
375 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
377 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2; in rs780_pm_init_profile()
378 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2; in rs780_pm_init_profile()
379 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
380 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
382 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2; in rs780_pm_init_profile()
383 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3; in rs780_pm_init_profile()
384 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
385 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
387 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; in rs780_pm_init_profile()
388 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; in rs780_pm_init_profile()
389 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
390 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
392 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; in rs780_pm_init_profile()
393 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; in rs780_pm_init_profile()
394 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
395 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
397 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; in rs780_pm_init_profile()
398 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3; in rs780_pm_init_profile()
399 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
400 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
408 if (rdev->family == CHIP_R600) { in r600_pm_init_profile()
411 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
412 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
413 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
414 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
416 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
417 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
418 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
419 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
421 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
422 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
423 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
424 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
426 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
427 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
428 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
429 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
431 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
432 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
433 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
434 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
436 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
437 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
438 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
439 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
441 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
442 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
443 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
444 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
446 if (rdev->pm.num_power_states < 4) { in r600_pm_init_profile()
448 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
449 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
450 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
451 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; in r600_pm_init_profile()
453 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; in r600_pm_init_profile()
454 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; in r600_pm_init_profile()
455 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
456 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
458 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; in r600_pm_init_profile()
459 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; in r600_pm_init_profile()
460 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
461 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; in r600_pm_init_profile()
463 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; in r600_pm_init_profile()
464 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; in r600_pm_init_profile()
465 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
466 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; in r600_pm_init_profile()
468 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; in r600_pm_init_profile()
469 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2; in r600_pm_init_profile()
470 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
471 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
473 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; in r600_pm_init_profile()
474 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2; in r600_pm_init_profile()
475 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
476 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; in r600_pm_init_profile()
478 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; in r600_pm_init_profile()
479 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; in r600_pm_init_profile()
480 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
481 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; in r600_pm_init_profile()
484 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
485 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
486 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
487 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; in r600_pm_init_profile()
489 if (rdev->flags & RADEON_IS_MOBILITY) in r600_pm_init_profile()
493 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx; in r600_pm_init_profile()
494 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx; in r600_pm_init_profile()
495 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
496 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
498 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx; in r600_pm_init_profile()
499 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx; in r600_pm_init_profile()
500 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
501 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; in r600_pm_init_profile()
504 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx; in r600_pm_init_profile()
505 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx; in r600_pm_init_profile()
506 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
507 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; in r600_pm_init_profile()
509 if (rdev->flags & RADEON_IS_MOBILITY) in r600_pm_init_profile()
513 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx; in r600_pm_init_profile()
514 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx; in r600_pm_init_profile()
515 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
516 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
518 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx; in r600_pm_init_profile()
519 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx; in r600_pm_init_profile()
520 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
521 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; in r600_pm_init_profile()
524 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx; in r600_pm_init_profile()
525 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx; in r600_pm_init_profile()
526 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
527 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; in r600_pm_init_profile()
534 int req_ps_idx = rdev->pm.requested_power_state_index; in r600_pm_misc()
535 int req_cm_idx = rdev->pm.requested_clock_mode_index; in r600_pm_misc()
536 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; in r600_pm_misc()
537 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; in r600_pm_misc()
539 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { in r600_pm_misc()
540 /* 0xff01 is a flag rather then an actual voltage */ in r600_pm_misc()
541 if (voltage->voltage == 0xff01) in r600_pm_misc()
543 if (voltage->voltage != rdev->pm.current_vddc) { in r600_pm_misc()
544 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); in r600_pm_misc()
545 rdev->pm.current_vddc = voltage->voltage; in r600_pm_misc()
546 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage); in r600_pm_misc()
709 struct drm_device *dev = rdev->ddev; in r600_hpd_init()
712 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { in r600_hpd_init()
720 switch (radeon_connector->hpd.hpd) { in r600_hpd_init()
723 rdev->irq.hpd[0] = true; in r600_hpd_init()
727 rdev->irq.hpd[1] = true; in r600_hpd_init()
731 rdev->irq.hpd[2] = true; in r600_hpd_init()
735 rdev->irq.hpd[3] = true; in r600_hpd_init()
740 rdev->irq.hpd[4] = true; in r600_hpd_init()
744 rdev->irq.hpd[5] = true; in r600_hpd_init()
750 switch (radeon_connector->hpd.hpd) { in r600_hpd_init()
753 rdev->irq.hpd[0] = true; in r600_hpd_init()
757 rdev->irq.hpd[1] = true; in r600_hpd_init()
761 rdev->irq.hpd[2] = true; in r600_hpd_init()
767 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); in r600_hpd_init()
769 if (rdev->irq.installed) in r600_hpd_init()
775 struct drm_device *dev = rdev->ddev; in r600_hpd_fini()
779 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { in r600_hpd_fini()
781 switch (radeon_connector->hpd.hpd) { in r600_hpd_fini()
784 rdev->irq.hpd[0] = false; in r600_hpd_fini()
788 rdev->irq.hpd[1] = false; in r600_hpd_fini()
792 rdev->irq.hpd[2] = false; in r600_hpd_fini()
796 rdev->irq.hpd[3] = false; in r600_hpd_fini()
801 rdev->irq.hpd[4] = false; in r600_hpd_fini()
805 rdev->irq.hpd[5] = false; in r600_hpd_fini()
812 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { in r600_hpd_fini()
814 switch (radeon_connector->hpd.hpd) { in r600_hpd_fini()
817 rdev->irq.hpd[0] = false; in r600_hpd_fini()
821 rdev->irq.hpd[1] = false; in r600_hpd_fini()
825 rdev->irq.hpd[2] = false; in r600_hpd_fini()
843 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && in r600_pcie_gart_tlb_flush()
844 !(rdev->flags & RADEON_IS_AGP)) { in r600_pcie_gart_tlb_flush()
845 void __iomem *ptr = (void *)rdev->gart.ptr; in r600_pcie_gart_tlb_flush()
858 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); in r600_pcie_gart_tlb_flush()
859 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); in r600_pcie_gart_tlb_flush()
861 for (i = 0; i < rdev->usec_timeout; i++) { in r600_pcie_gart_tlb_flush()
880 if (rdev->gart.robj) { in r600_pcie_gart_init()
888 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; in r600_pcie_gart_init()
897 if (rdev->gart.robj == NULL) { in r600_pcie_gart_enable()
898 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); in r600_pcie_gart_enable()
899 return -EINVAL; in r600_pcie_gart_enable()
931 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); in r600_pcie_gart_enable()
932 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); in r600_pcie_gart_enable()
933 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in r600_pcie_gart_enable()
937 (u32)(rdev->dummy_page.addr >> 12)); in r600_pcie_gart_enable()
943 (unsigned)(rdev->mc.gtt_size >> 20), in r600_pcie_gart_enable()
944 (unsigned long long)rdev->gart.table_addr); in r600_pcie_gart_enable()
945 rdev->gart.ready = true; in r600_pcie_gart_enable()
1028 for (i = 0; i < rdev->usec_timeout; i++) { in r600_mc_wait_for_idle()
1035 return -1; in r600_mc_wait_for_idle()
1056 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in r600_mc_program()
1061 if (rdev->flags & RADEON_IS_AGP) { in r600_mc_program()
1062 if (rdev->mc.vram_start < rdev->mc.gtt_start) { in r600_mc_program()
1065 rdev->mc.vram_start >> 12); in r600_mc_program()
1067 rdev->mc.gtt_end >> 12); in r600_mc_program()
1071 rdev->mc.gtt_start >> 12); in r600_mc_program()
1073 rdev->mc.vram_end >> 12); in r600_mc_program()
1076 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); in r600_mc_program()
1077 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12); in r600_mc_program()
1079 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); in r600_mc_program()
1080 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; in r600_mc_program()
1081 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); in r600_mc_program()
1083 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); in r600_mc_program()
1086 if (rdev->flags & RADEON_IS_AGP) { in r600_mc_program()
1087 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22); in r600_mc_program()
1088 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22); in r600_mc_program()
1089 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); in r600_mc_program()
1096 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in r600_mc_program()
1105 * r600_vram_gtt_location - try to find VRAM & GTT location
1113 * If there is not enough space to fit the unvisible VRAM after the
1129 if (mc->mc_vram_size > 0xE0000000) { in r600_vram_gtt_location()
1131 dev_warn(rdev->dev, "limiting VRAM\n"); in r600_vram_gtt_location()
1132 mc->real_vram_size = 0xE0000000; in r600_vram_gtt_location()
1133 mc->mc_vram_size = 0xE0000000; in r600_vram_gtt_location()
1135 if (rdev->flags & RADEON_IS_AGP) { in r600_vram_gtt_location()
1136 size_bf = mc->gtt_start; in r600_vram_gtt_location()
1137 size_af = 0xFFFFFFFF - mc->gtt_end + 1; in r600_vram_gtt_location()
1139 if (mc->mc_vram_size > size_bf) { in r600_vram_gtt_location()
1140 dev_warn(rdev->dev, "limiting VRAM\n"); in r600_vram_gtt_location()
1141 mc->real_vram_size = size_bf; in r600_vram_gtt_location()
1142 mc->mc_vram_size = size_bf; in r600_vram_gtt_location()
1144 mc->vram_start = mc->gtt_start - mc->mc_vram_size; in r600_vram_gtt_location()
1146 if (mc->mc_vram_size > size_af) { in r600_vram_gtt_location()
1147 dev_warn(rdev->dev, "limiting VRAM\n"); in r600_vram_gtt_location()
1148 mc->real_vram_size = size_af; in r600_vram_gtt_location()
1149 mc->mc_vram_size = size_af; in r600_vram_gtt_location()
1151 mc->vram_start = mc->gtt_end; in r600_vram_gtt_location()
1153 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; in r600_vram_gtt_location()
1154 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", in r600_vram_gtt_location()
1155 mc->mc_vram_size >> 20, mc->vram_start, in r600_vram_gtt_location()
1156 mc->vram_end, mc->real_vram_size >> 20); in r600_vram_gtt_location()
1159 if (rdev->flags & RADEON_IS_IGP) { in r600_vram_gtt_location()
1163 radeon_vram_location(rdev, &rdev->mc, base); in r600_vram_gtt_location()
1164 rdev->mc.gtt_base_align = 0; in r600_vram_gtt_location()
1175 rdev->mc.vram_is_ddr = true; in r600_mc_init()
1200 rdev->mc.vram_width = numchan * chansize; in r600_mc_init()
1202 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); in r600_mc_init()
1203 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); in r600_mc_init()
1205 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); in r600_mc_init()
1206 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); in r600_mc_init()
1207 rdev->mc.visible_vram_size = rdev->mc.aper_size; in r600_mc_init()
1208 r600_vram_gtt_location(rdev, &rdev->mc); in r600_mc_init()
1210 if (rdev->flags & RADEON_IS_IGP) { in r600_mc_init()
1212 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); in r600_mc_init()
1222 if (rdev->vram_scratch.robj == NULL) { in r600_vram_scratch_init()
1225 &rdev->vram_scratch.robj); in r600_vram_scratch_init()
1231 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); in r600_vram_scratch_init()
1234 r = radeon_bo_pin(rdev->vram_scratch.robj, in r600_vram_scratch_init()
1235 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr); in r600_vram_scratch_init()
1237 radeon_bo_unreserve(rdev->vram_scratch.robj); in r600_vram_scratch_init()
1240 r = radeon_bo_kmap(rdev->vram_scratch.robj, in r600_vram_scratch_init()
1241 (void **)&rdev->vram_scratch.ptr); in r600_vram_scratch_init()
1243 radeon_bo_unpin(rdev->vram_scratch.robj); in r600_vram_scratch_init()
1244 radeon_bo_unreserve(rdev->vram_scratch.robj); in r600_vram_scratch_init()
1253 if (rdev->vram_scratch.robj == NULL) { in r600_vram_scratch_fini()
1256 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); in r600_vram_scratch_fini()
1258 radeon_bo_kunmap(rdev->vram_scratch.robj); in r600_vram_scratch_fini()
1259 radeon_bo_unpin(rdev->vram_scratch.robj); in r600_vram_scratch_fini()
1260 radeon_bo_unreserve(rdev->vram_scratch.robj); in r600_vram_scratch_fini()
1262 radeon_bo_unref(&rdev->vram_scratch.robj); in r600_vram_scratch_fini()
1293 dev_info(rdev->dev, "GPU softreset \n"); in r600_gpu_soft_reset()
1294 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n", in r600_gpu_soft_reset()
1296 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n", in r600_gpu_soft_reset()
1298 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n", in r600_gpu_soft_reset()
1302 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in r600_gpu_soft_reset()
1306 /* Check if any of the rendering block is busy and reset it */ in r600_gpu_soft_reset()
1322 dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); in r600_gpu_soft_reset()
1330 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); in r600_gpu_soft_reset()
1337 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n", in r600_gpu_soft_reset()
1339 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n", in r600_gpu_soft_reset()
1341 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n", in r600_gpu_soft_reset()
1355 if (rdev->family >= CHIP_RV770) in r600_gpu_is_lockup()
1356 lockup = &rdev->config.rv770.lockup; in r600_gpu_is_lockup()
1358 lockup = &rdev->config.r600.lockup; in r600_gpu_is_lockup()
1375 ring->rptr = RREG32(ring->rptr_reg); in r600_gpu_is_lockup()
1521 switch (rdev->family) { in r600_gpu_init()
1523 rdev->config.r600.max_pipes = 4; in r600_gpu_init()
1524 rdev->config.r600.max_tile_pipes = 8; in r600_gpu_init()
1525 rdev->config.r600.max_simds = 4; in r600_gpu_init()
1526 rdev->config.r600.max_backends = 4; in r600_gpu_init()
1527 rdev->config.r600.max_gprs = 256; in r600_gpu_init()
1528 rdev->config.r600.max_threads = 192; in r600_gpu_init()
1529 rdev->config.r600.max_stack_entries = 256; in r600_gpu_init()
1530 rdev->config.r600.max_hw_contexts = 8; in r600_gpu_init()
1531 rdev->config.r600.max_gs_threads = 16; in r600_gpu_init()
1532 rdev->config.r600.sx_max_export_size = 128; in r600_gpu_init()
1533 rdev->config.r600.sx_max_export_pos_size = 16; in r600_gpu_init()
1534 rdev->config.r600.sx_max_export_smx_size = 128; in r600_gpu_init()
1535 rdev->config.r600.sq_num_cf_insts = 2; in r600_gpu_init()
1539 rdev->config.r600.max_pipes = 2; in r600_gpu_init()
1540 rdev->config.r600.max_tile_pipes = 2; in r600_gpu_init()
1541 rdev->config.r600.max_simds = 3; in r600_gpu_init()
1542 rdev->config.r600.max_backends = 1; in r600_gpu_init()
1543 rdev->config.r600.max_gprs = 128; in r600_gpu_init()
1544 rdev->config.r600.max_threads = 192; in r600_gpu_init()
1545 rdev->config.r600.max_stack_entries = 128; in r600_gpu_init()
1546 rdev->config.r600.max_hw_contexts = 8; in r600_gpu_init()
1547 rdev->config.r600.max_gs_threads = 4; in r600_gpu_init()
1548 rdev->config.r600.sx_max_export_size = 128; in r600_gpu_init()
1549 rdev->config.r600.sx_max_export_pos_size = 16; in r600_gpu_init()
1550 rdev->config.r600.sx_max_export_smx_size = 128; in r600_gpu_init()
1551 rdev->config.r600.sq_num_cf_insts = 2; in r600_gpu_init()
1557 rdev->config.r600.max_pipes = 1; in r600_gpu_init()
1558 rdev->config.r600.max_tile_pipes = 1; in r600_gpu_init()
1559 rdev->config.r600.max_simds = 2; in r600_gpu_init()
1560 rdev->config.r600.max_backends = 1; in r600_gpu_init()
1561 rdev->config.r600.max_gprs = 128; in r600_gpu_init()
1562 rdev->config.r600.max_threads = 192; in r600_gpu_init()
1563 rdev->config.r600.max_stack_entries = 128; in r600_gpu_init()
1564 rdev->config.r600.max_hw_contexts = 4; in r600_gpu_init()
1565 rdev->config.r600.max_gs_threads = 4; in r600_gpu_init()
1566 rdev->config.r600.sx_max_export_size = 128; in r600_gpu_init()
1567 rdev->config.r600.sx_max_export_pos_size = 16; in r600_gpu_init()
1568 rdev->config.r600.sx_max_export_smx_size = 128; in r600_gpu_init()
1569 rdev->config.r600.sq_num_cf_insts = 1; in r600_gpu_init()
1572 rdev->config.r600.max_pipes = 4; in r600_gpu_init()
1573 rdev->config.r600.max_tile_pipes = 4; in r600_gpu_init()
1574 rdev->config.r600.max_simds = 4; in r600_gpu_init()
1575 rdev->config.r600.max_backends = 4; in r600_gpu_init()
1576 rdev->config.r600.max_gprs = 192; in r600_gpu_init()
1577 rdev->config.r600.max_threads = 192; in r600_gpu_init()
1578 rdev->config.r600.max_stack_entries = 256; in r600_gpu_init()
1579 rdev->config.r600.max_hw_contexts = 8; in r600_gpu_init()
1580 rdev->config.r600.max_gs_threads = 16; in r600_gpu_init()
1581 rdev->config.r600.sx_max_export_size = 128; in r600_gpu_init()
1582 rdev->config.r600.sx_max_export_pos_size = 16; in r600_gpu_init()
1583 rdev->config.r600.sx_max_export_smx_size = 128; in r600_gpu_init()
1584 rdev->config.r600.sq_num_cf_insts = 2; in r600_gpu_init()
1604 switch (rdev->config.r600.max_tile_pipes) { in r600_gpu_init()
1620 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes; in r600_gpu_init()
1621 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); in r600_gpu_init()
1625 rdev->config.r600.tiling_group_size = 512; in r600_gpu_init()
1627 rdev->config.r600.tiling_group_size = 256; in r600_gpu_init()
1640 …BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MAS… in r600_gpu_init()
1644 INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK); in r600_gpu_init()
1646 INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK); in r600_gpu_init()
1648 backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes, in r600_gpu_init()
1649 (R6XX_MAX_BACKENDS - in r600_gpu_init()
1653 rdev->config.r600.tile_config = tiling_config; in r600_gpu_init()
1654 rdev->config.r600.backend_map = backend_map; in r600_gpu_init()
1665 …tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >>… in r600_gpu_init()
1667 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK); in r600_gpu_init()
1676 if (rdev->family == CHIP_RV670) in r600_gpu_init()
1681 if ((rdev->family > CHIP_R600)) in r600_gpu_init()
1685 if (((rdev->family) == CHIP_R600) || in r600_gpu_init()
1686 ((rdev->family) == CHIP_RV630) || in r600_gpu_init()
1687 ((rdev->family) == CHIP_RV610) || in r600_gpu_init()
1688 ((rdev->family) == CHIP_RV620) || in r600_gpu_init()
1689 ((rdev->family) == CHIP_RS780) || in r600_gpu_init()
1690 ((rdev->family) == CHIP_RS880)) { in r600_gpu_init()
1705 if (((rdev->family) == CHIP_RV610) || in r600_gpu_init()
1706 ((rdev->family) == CHIP_RV620) || in r600_gpu_init()
1707 ((rdev->family) == CHIP_RS780) || in r600_gpu_init()
1708 ((rdev->family) == CHIP_RS880)) { in r600_gpu_init()
1713 } else if (((rdev->family) == CHIP_R600) || in r600_gpu_init()
1714 ((rdev->family) == CHIP_RV630)) { in r600_gpu_init()
1735 if ((rdev->family) == CHIP_R600) { in r600_gpu_init()
1749 } else if (((rdev->family) == CHIP_RV610) || in r600_gpu_init()
1750 ((rdev->family) == CHIP_RV620) || in r600_gpu_init()
1751 ((rdev->family) == CHIP_RS780) || in r600_gpu_init()
1752 ((rdev->family) == CHIP_RS880)) { in r600_gpu_init()
1769 } else if (((rdev->family) == CHIP_RV630) || in r600_gpu_init()
1770 ((rdev->family) == CHIP_RV635)) { in r600_gpu_init()
1784 } else if ((rdev->family) == CHIP_RV670) { in r600_gpu_init()
1807 if (((rdev->family) == CHIP_RV610) || in r600_gpu_init()
1808 ((rdev->family) == CHIP_RV620) || in r600_gpu_init()
1809 ((rdev->family) == CHIP_RS780) || in r600_gpu_init()
1810 ((rdev->family) == CHIP_RS880)) { in r600_gpu_init()
1833 tmp = rdev->config.r600.max_pipes * 16; in r600_gpu_init()
1834 switch (rdev->family) { in r600_gpu_init()
1877 switch (rdev->family) { in r600_gpu_init()
1937 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); in r600_cp_stop()
1957 return -EINVAL; in r600_init_microcode()
1960 switch (rdev->family) { in r600_init_microcode()
2035 if (rdev->family >= CHIP_CEDAR) { in r600_init_microcode()
2039 } else if (rdev->family >= CHIP_RV770) { in r600_init_microcode()
2052 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev); in r600_init_microcode()
2055 if (rdev->pfp_fw->size != pfp_req_size) { in r600_init_microcode()
2058 rdev->pfp_fw->size, fw_name); in r600_init_microcode()
2059 err = -EINVAL; in r600_init_microcode()
2064 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev); in r600_init_microcode()
2067 if (rdev->me_fw->size != me_req_size) { in r600_init_microcode()
2070 rdev->me_fw->size, fw_name); in r600_init_microcode()
2071 err = -EINVAL; in r600_init_microcode()
2075 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev); in r600_init_microcode()
2078 if (rdev->rlc_fw->size != rlc_req_size) { in r600_init_microcode()
2081 rdev->rlc_fw->size, fw_name); in r600_init_microcode()
2082 err = -EINVAL; in r600_init_microcode()
2089 if (err != -EINVAL) in r600_init_microcode()
2093 release_firmware(rdev->pfp_fw); in r600_init_microcode()
2094 rdev->pfp_fw = NULL; in r600_init_microcode()
2095 release_firmware(rdev->me_fw); in r600_init_microcode()
2096 rdev->me_fw = NULL; in r600_init_microcode()
2097 release_firmware(rdev->rlc_fw); in r600_init_microcode()
2098 rdev->rlc_fw = NULL; in r600_init_microcode()
2108 if (!rdev->me_fw || !rdev->pfp_fw) in r600_cp_load_microcode()
2109 return -EINVAL; in r600_cp_load_microcode()
2127 fw_data = (const __be32 *)rdev->me_fw->data; in r600_cp_load_microcode()
2133 fw_data = (const __be32 *)rdev->pfp_fw->data; in r600_cp_load_microcode()
2147 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r600_cp_start()
2158 if (rdev->family >= CHIP_RV770) { in r600_cp_start()
2160 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1); in r600_cp_start()
2163 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1); in r600_cp_start()
2177 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r600_cp_resume()
2189 rb_bufsz = drm_order(ring->ring_size / 8); in r600_cp_resume()
2203 ring->wptr = 0; in r600_cp_resume()
2204 WREG32(CP_RB_WPTR, ring->wptr); in r600_cp_resume()
2208 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); in r600_cp_resume()
2209 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); in r600_cp_resume()
2210 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); in r600_cp_resume()
2212 if (rdev->wb.enabled) in r600_cp_resume()
2222 WREG32(CP_RB_BASE, ring->gpu_addr >> 8); in r600_cp_resume()
2225 ring->rptr = RREG32(CP_RB_RPTR); in r600_cp_resume()
2228 ring->ready = true; in r600_cp_resume()
2231 ring->ready = false; in r600_cp_resume()
2244 ring->ring_size = ring_size; in r600_ring_init()
2245 ring->align_mask = 16 - 1; in r600_ring_init()
2251 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); in r600_cp_fini()
2262 rdev->scratch.num_reg = 7; in r600_scratch_init()
2263 rdev->scratch.reg_base = SCRATCH_REG0; in r600_scratch_init()
2264 for (i = 0; i < rdev->scratch.num_reg; i++) { in r600_scratch_init()
2265 rdev->scratch.free[i] = true; in r600_scratch_init()
2266 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); in r600_scratch_init()
2290 radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); in r600_ring_test()
2293 for (i = 0; i < rdev->usec_timeout; i++) { in r600_ring_test()
2299 if (i < rdev->usec_timeout) { in r600_ring_test()
2304 r = -EINVAL; in r600_ring_test()
2313 struct radeon_ring *ring = &rdev->ring[fence->ring]; in r600_fence_ring_emit()
2315 if (rdev->wb.use_event) { in r600_fence_ring_emit()
2316 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in r600_fence_ring_emit()
2325 /* EVENT_WRITE_EOP - flush caches, send int */ in r600_fence_ring_emit()
2330 radeon_ring_write(ring, fence->seq); in r600_fence_ring_emit()
2345 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); in r600_fence_ring_emit()
2349 …radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET… in r600_fence_ring_emit()
2350 radeon_ring_write(ring, fence->seq); in r600_fence_ring_emit()
2362 uint64_t addr = semaphore->gpu_addr; in r600_semaphore_ring_emit()
2365 if (rdev->family < CHIP_CAYMAN) in r600_semaphore_ring_emit()
2381 mutex_lock(&rdev->r600_blit.mutex); in r600_copy_blit()
2382 rdev->r600_blit.vb_ib = NULL; in r600_copy_blit()
2385 if (rdev->r600_blit.vb_ib) in r600_copy_blit()
2386 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib); in r600_copy_blit()
2387 mutex_unlock(&rdev->r600_blit.mutex); in r600_copy_blit()
2392 mutex_unlock(&rdev->r600_blit.mutex); in r600_copy_blit()
2401 if (rdev->r600_blit.shader_obj) { in r600_blit_suspend()
2402 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); in r600_blit_suspend()
2404 radeon_bo_unpin(rdev->r600_blit.shader_obj); in r600_blit_suspend()
2405 radeon_bo_unreserve(rdev->r600_blit.shader_obj); in r600_blit_suspend()
2425 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r600_startup()
2431 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { in r600_startup()
2444 if (rdev->flags & RADEON_IS_AGP) { in r600_startup()
2455 rdev->asic->copy = NULL; in r600_startup()
2456 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); in r600_startup()
2466 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in r600_startup()
2479 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, in r600_startup()
2499 rdev->accel_working = false; in r600_startup()
2529 atom_asic_init(rdev->mode_info.atom_context); in r600_resume()
2531 rdev->accel_working = true; in r600_resume()
2535 rdev->accel_working = false; in r600_resume()
2555 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in r600_suspend()
2563 /* Plan is to move initialization in that function and use
2583 return -EINVAL; in r600_init()
2586 if (!rdev->is_atom_bios) { in r600_init()
2587 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); in r600_init()
2588 return -EINVAL; in r600_init()
2595 if (!rdev->bios) { in r600_init()
2596 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); in r600_init()
2597 return -EINVAL; in r600_init()
2600 atom_asic_init(rdev->mode_info.atom_context); in r600_init()
2607 radeon_get_clock_info(rdev->ddev); in r600_init()
2612 if (rdev->flags & RADEON_IS_AGP) { in r600_init()
2629 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; in r600_init()
2630 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); in r600_init()
2632 rdev->ih.ring_obj = NULL; in r600_init()
2640 rdev->accel_working = true; in r600_init()
2642 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); in r600_init()
2643 rdev->accel_working = false; in r600_init()
2648 dev_err(rdev->dev, "disabling GPU acceleration\n"); in r600_init()
2655 rdev->accel_working = false; in r600_init()
2681 kfree(rdev->bios); in r600_fini()
2682 rdev->bios = NULL; in r600_fini()
2687 * CS stuff
2691 struct radeon_ring *ring = &rdev->ring[ib->fence->ring]; in r600_ring_ib_execute()
2699 (ib->gpu_addr & 0xFFFFFFFC)); in r600_ring_ib_execute()
2700 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); in r600_ring_ib_execute()
2701 radeon_ring_write(ring, ib->length_dw); in r600_ring_ib_execute()
2723 ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); in r600_ib_test()
2724 ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); in r600_ib_test()
2725 ib->ptr[2] = 0xDEADBEEF; in r600_ib_test()
2726 ib->ptr[3] = PACKET2(0); in r600_ib_test()
2727 ib->ptr[4] = PACKET2(0); in r600_ib_test()
2728 ib->ptr[5] = PACKET2(0); in r600_ib_test()
2729 ib->ptr[6] = PACKET2(0); in r600_ib_test()
2730 ib->ptr[7] = PACKET2(0); in r600_ib_test()
2731 ib->ptr[8] = PACKET2(0); in r600_ib_test()
2732 ib->ptr[9] = PACKET2(0); in r600_ib_test()
2733 ib->ptr[10] = PACKET2(0); in r600_ib_test()
2734 ib->ptr[11] = PACKET2(0); in r600_ib_test()
2735 ib->ptr[12] = PACKET2(0); in r600_ib_test()
2736 ib->ptr[13] = PACKET2(0); in r600_ib_test()
2737 ib->ptr[14] = PACKET2(0); in r600_ib_test()
2738 ib->ptr[15] = PACKET2(0); in r600_ib_test()
2739 ib->length_dw = 16; in r600_ib_test()
2747 r = radeon_fence_wait(ib->fence, false); in r600_ib_test()
2752 for (i = 0; i < rdev->usec_timeout; i++) { in r600_ib_test()
2758 if (i < rdev->usec_timeout) { in r600_ib_test()
2759 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib->fence->ring, i); in r600_ib_test()
2763 r = -EINVAL; in r600_ib_test()
2788 rdev->ih.ring_size = ring_size; in r600_ih_ring_init()
2789 rdev->ih.ptr_mask = rdev->ih.ring_size - 1; in r600_ih_ring_init()
2790 rdev->ih.rptr = 0; in r600_ih_ring_init()
2798 if (rdev->ih.ring_obj == NULL) { in r600_ih_ring_alloc()
2799 r = radeon_bo_create(rdev, rdev->ih.ring_size, in r600_ih_ring_alloc()
2802 &rdev->ih.ring_obj); in r600_ih_ring_alloc()
2807 r = radeon_bo_reserve(rdev->ih.ring_obj, false); in r600_ih_ring_alloc()
2810 r = radeon_bo_pin(rdev->ih.ring_obj, in r600_ih_ring_alloc()
2812 &rdev->ih.gpu_addr); in r600_ih_ring_alloc()
2814 radeon_bo_unreserve(rdev->ih.ring_obj); in r600_ih_ring_alloc()
2818 r = radeon_bo_kmap(rdev->ih.ring_obj, in r600_ih_ring_alloc()
2819 (void **)&rdev->ih.ring); in r600_ih_ring_alloc()
2820 radeon_bo_unreserve(rdev->ih.ring_obj); in r600_ih_ring_alloc()
2832 if (rdev->ih.ring_obj) { in r600_ih_ring_fini()
2833 r = radeon_bo_reserve(rdev->ih.ring_obj, false); in r600_ih_ring_fini()
2835 radeon_bo_kunmap(rdev->ih.ring_obj); in r600_ih_ring_fini()
2836 radeon_bo_unpin(rdev->ih.ring_obj); in r600_ih_ring_fini()
2837 radeon_bo_unreserve(rdev->ih.ring_obj); in r600_ih_ring_fini()
2839 radeon_bo_unref(&rdev->ih.ring_obj); in r600_ih_ring_fini()
2840 rdev->ih.ring = NULL; in r600_ih_ring_fini()
2841 rdev->ih.ring_obj = NULL; in r600_ih_ring_fini()
2848 if ((rdev->family >= CHIP_RV770) && in r600_rlc_stop()
2849 (rdev->family <= CHIP_RV740)) { in r600_rlc_stop()
2871 if (!rdev->rlc_fw) in r600_rlc_init()
2872 return -EINVAL; in r600_rlc_init()
2880 if (rdev->family <= CHIP_CAICOS) { in r600_rlc_init()
2887 fw_data = (const __be32 *)rdev->rlc_fw->data; in r600_rlc_init()
2888 if (rdev->family >= CHIP_CAYMAN) { in r600_rlc_init()
2893 } else if (rdev->family >= CHIP_CEDAR) { in r600_rlc_init()
2898 } else if (rdev->family >= CHIP_RV770) { in r600_rlc_init()
2925 rdev->ih.enabled = true; in r600_enable_interrupts()
2940 rdev->ih.enabled = false; in r600_disable_interrupts()
2941 rdev->ih.wptr = 0; in r600_disable_interrupts()
2942 rdev->ih.rptr = 0; in r600_disable_interrupts()
3006 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8); in r600_irq_init()
3008 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi in r600_irq_init()
3009 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN in r600_irq_init()
3012 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */ in r600_irq_init()
3016 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); in r600_irq_init()
3017 rb_bufsz = drm_order(rdev->ih.ring_size / 4); in r600_irq_init()
3023 if (rdev->wb.enabled) in r600_irq_init()
3027 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); in r600_irq_init()
3028 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); in r600_irq_init()
3039 if (rdev->msi_enabled) in r600_irq_init()
3044 if (rdev->family >= CHIP_CEDAR) in r600_irq_init()
3076 if (!rdev->irq.installed) { in r600_irq_set()
3077 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); in r600_irq_set()
3078 return -EINVAL; in r600_irq_set()
3080 /* don't enable anything if the ih is disabled */ in r600_irq_set()
3081 if (!rdev->ih.enabled) { in r600_irq_set()
3106 if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) { in r600_irq_set()
3111 if (rdev->irq.crtc_vblank_int[0] || in r600_irq_set()
3112 rdev->irq.pflip[0]) { in r600_irq_set()
3116 if (rdev->irq.crtc_vblank_int[1] || in r600_irq_set()
3117 rdev->irq.pflip[1]) { in r600_irq_set()
3121 if (rdev->irq.hpd[0]) { in r600_irq_set()
3125 if (rdev->irq.hpd[1]) { in r600_irq_set()
3129 if (rdev->irq.hpd[2]) { in r600_irq_set()
3133 if (rdev->irq.hpd[3]) { in r600_irq_set()
3137 if (rdev->irq.hpd[4]) { in r600_irq_set()
3141 if (rdev->irq.hpd[5]) { in r600_irq_set()
3145 if (rdev->irq.hdmi[0]) { in r600_irq_set()
3149 if (rdev->irq.hdmi[1]) { in r600_irq_set()
3153 if (rdev->irq.gui_idle) { in r600_irq_set()
3189 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); in r600_irq_ack()
3190 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE); in r600_irq_ack()
3191 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2); in r600_irq_ack()
3193 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS); in r600_irq_ack()
3194 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); in r600_irq_ack()
3195 rdev->irq.stat_regs.r600.disp_int_cont2 = 0; in r600_irq_ack()
3197 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS); in r600_irq_ack()
3198 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS); in r600_irq_ack()
3200 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED) in r600_irq_ack()
3202 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED) in r600_irq_ack()
3204 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) in r600_irq_ack()
3206 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) in r600_irq_ack()
3208 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) in r600_irq_ack()
3210 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) in r600_irq_ack()
3212 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { in r600_irq_ack()
3223 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { in r600_irq_ack()
3234 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { in r600_irq_ack()
3245 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { in r600_irq_ack()
3251 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { in r600_irq_ack()
3256 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { in r600_irq_ack()
3289 if (rdev->wb.enabled) in r600_get_ih_wptr()
3290 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); in r600_get_ih_wptr()
3299 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n", in r600_get_ih_wptr()
3300 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask); in r600_get_ih_wptr()
3301 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; in r600_get_ih_wptr()
3306 return (wptr & rdev->ih.ptr_mask); in r600_get_ih_wptr()
3310 * Each IV ring entry is 128 bits:
3311 * [7:0] - interrupt source id
3312 * [31:8] - reserved
3313 * [59:32] - interrupt source data
3314 * [127:60] - reserved
3317 * are decoded as follows:
3325 * 19 2 DAC A auto-detection
3326 * 19 3 DAC B auto-detection
3329 * 176 - CP_INT RB
3330 * 177 - CP_INT IB1
3331 * 178 - CP_INT IB2
3332 * 181 - EOP Interrupt
3333 * 233 - GUI Idle
3348 if (!rdev->ih.enabled || rdev->shutdown) in r600_irq_process()
3352 if (!rdev->msi_enabled) in r600_irq_process()
3356 rptr = rdev->ih.rptr; in r600_irq_process()
3359 spin_lock_irqsave(&rdev->ih.lock, flags); in r600_irq_process()
3362 spin_unlock_irqrestore(&rdev->ih.lock, flags); in r600_irq_process()
3373 rdev->ih.wptr = wptr; in r600_irq_process()
3377 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; in r600_irq_process()
3378 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; in r600_irq_process()
3384 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) { in r600_irq_process()
3385 if (rdev->irq.crtc_vblank_int[0]) { in r600_irq_process()
3386 drm_handle_vblank(rdev->ddev, 0); in r600_irq_process()
3387 rdev->pm.vblank_sync = true; in r600_irq_process()
3388 wake_up(&rdev->irq.vblank_queue); in r600_irq_process()
3390 if (rdev->irq.pflip[0]) in r600_irq_process()
3392 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT; in r600_irq_process()
3397 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) { in r600_irq_process()
3398 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT; in r600_irq_process()
3410 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) { in r600_irq_process()
3411 if (rdev->irq.crtc_vblank_int[1]) { in r600_irq_process()
3412 drm_handle_vblank(rdev->ddev, 1); in r600_irq_process()
3413 rdev->pm.vblank_sync = true; in r600_irq_process()
3414 wake_up(&rdev->irq.vblank_queue); in r600_irq_process()
3416 if (rdev->irq.pflip[1]) in r600_irq_process()
3418 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT; in r600_irq_process()
3423 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) { in r600_irq_process()
3424 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT; in r600_irq_process()
3436 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { in r600_irq_process()
3437 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT; in r600_irq_process()
3443 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { in r600_irq_process()
3444 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT; in r600_irq_process()
3450 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { in r600_irq_process()
3451 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT; in r600_irq_process()
3457 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { in r600_irq_process()
3458 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT; in r600_irq_process()
3464 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { in r600_irq_process()
3465 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT; in r600_irq_process()
3471 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { in r600_irq_process()
3472 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT; in r600_irq_process()
3498 rdev->pm.gui_idle = true; in r600_irq_process()
3499 wake_up(&rdev->irq.idle_queue); in r600_irq_process()
3508 rptr &= rdev->ih.ptr_mask; in r600_irq_process()
3512 if (wptr != rdev->ih.wptr) in r600_irq_process()
3515 schedule_work(&rdev->hotplug_work); in r600_irq_process()
3516 rdev->ih.rptr = rptr; in r600_irq_process()
3517 WREG32(IH_RB_RPTR, rdev->ih.rptr); in r600_irq_process()
3518 spin_unlock_irqrestore(&rdev->ih.lock, flags); in r600_irq_process()
3529 struct drm_info_node *node = (struct drm_info_node *) m->private; in r600_debugfs_mc_info()
3530 struct drm_device *dev = node->minor->dev; in r600_debugfs_mc_info()
3531 struct radeon_device *rdev = dev->dev_private; in r600_debugfs_mc_info()
3553 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
3555 * bo: buffer object struct which userspace is waiting for idle
3569 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && in r600_ioctl_wait_idle()
3570 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) { in r600_ioctl_wait_idle()
3571 void __iomem *ptr = (void *)rdev->vram_scratch.ptr; in r600_ioctl_wait_idle()
3584 if (rdev->flags & RADEON_IS_IGP) in r600_set_pcie_lanes()
3587 if (!(rdev->flags & RADEON_IS_PCIE)) in r600_set_pcie_lanes()
3639 …* a complete re-config. … in r600_set_pcie_lanes()
3650 if (rdev->family >= CHIP_RV770) in r600_set_pcie_lanes()
3666 if (rdev->flags & RADEON_IS_IGP) in r600_get_pcie_lanes()
3669 if (!(rdev->flags & RADEON_IS_PCIE)) in r600_get_pcie_lanes()
3705 if (rdev->flags & RADEON_IS_IGP) in r600_pcie_gen2_enable()
3708 if (!(rdev->flags & RADEON_IS_PCIE)) in r600_pcie_gen2_enable()
3716 if (rdev->family <= CHIP_R600) in r600_pcie_gen2_enable()
3720 if ((rdev->family == CHIP_RV670) || in r600_pcie_gen2_enable()
3721 (rdev->family == CHIP_RV620) || in r600_pcie_gen2_enable()
3722 (rdev->family == CHIP_RV635)) { in r600_pcie_gen2_enable()
3745 if ((rdev->family == CHIP_RV670) || in r600_pcie_gen2_enable()
3746 (rdev->family == CHIP_RV620) || in r600_pcie_gen2_enable()
3747 (rdev->family == CHIP_RV635)) { in r600_pcie_gen2_enable()
3772 if ((rdev->family == CHIP_RV670) || in r600_pcie_gen2_enable()
3773 (rdev->family == CHIP_RV620) || in r600_pcie_gen2_enable()
3774 (rdev->family == CHIP_RV635)) { in r600_pcie_gen2_enable()