Lines Matching +full:hb +full:- +full:pll +full:- +full:clock
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
32 #include "atom-bits.h"
38 struct drm_device *dev = crtc->dev; in atombios_overscan_setup()
39 struct radeon_device *rdev = dev->dev_private; in atombios_overscan_setup()
47 args.ucCRTC = radeon_crtc->crtc_id; in atombios_overscan_setup()
49 switch (radeon_crtc->rmx_type) { in atombios_overscan_setup()
51 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); in atombios_overscan_setup()
52 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); in atombios_overscan_setup()
53 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); in atombios_overscan_setup()
54 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); in atombios_overscan_setup()
57 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; in atombios_overscan_setup()
58 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay; in atombios_overscan_setup()
61 …args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); in atombios_overscan_setup()
62 …args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2… in atombios_overscan_setup()
64 … args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); in atombios_overscan_setup()
65 …args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / … in atombios_overscan_setup()
70 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border); in atombios_overscan_setup()
71 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border); in atombios_overscan_setup()
72 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border); in atombios_overscan_setup()
73 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border); in atombios_overscan_setup()
76 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); in atombios_overscan_setup()
81 struct drm_device *dev = crtc->dev; in atombios_scaler_setup()
82 struct radeon_device *rdev = dev->dev_private; in atombios_scaler_setup()
87 /* fixme - fill in enc_priv for atom dac */ in atombios_scaler_setup()
92 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) in atombios_scaler_setup()
95 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { in atombios_scaler_setup()
97 if (encoder->crtc == crtc) { in atombios_scaler_setup()
99 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { in atombios_scaler_setup()
100 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; in atombios_scaler_setup()
101 tv_std = tv_dac->tv_std; in atombios_scaler_setup()
109 args.ucScaler = radeon_crtc->crtc_id; in atombios_scaler_setup()
144 switch (radeon_crtc->rmx_type) { in atombios_scaler_setup()
162 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); in atombios_scaler_setup()
164 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) { in atombios_scaler_setup()
172 struct drm_device *dev = crtc->dev; in atombios_lock_crtc()
173 struct radeon_device *rdev = dev->dev_private; in atombios_lock_crtc()
180 args.ucCRTC = radeon_crtc->crtc_id; in atombios_lock_crtc()
183 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); in atombios_lock_crtc()
189 struct drm_device *dev = crtc->dev; in atombios_enable_crtc()
190 struct radeon_device *rdev = dev->dev_private; in atombios_enable_crtc()
196 args.ucCRTC = radeon_crtc->crtc_id; in atombios_enable_crtc()
199 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); in atombios_enable_crtc()
205 struct drm_device *dev = crtc->dev; in atombios_enable_crtc_memreq()
206 struct radeon_device *rdev = dev->dev_private; in atombios_enable_crtc_memreq()
212 args.ucCRTC = radeon_crtc->crtc_id; in atombios_enable_crtc_memreq()
215 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); in atombios_enable_crtc_memreq()
221 struct drm_device *dev = crtc->dev; in atombios_blank_crtc()
222 struct radeon_device *rdev = dev->dev_private; in atombios_blank_crtc()
228 args.ucCRTC = radeon_crtc->crtc_id; in atombios_blank_crtc()
231 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); in atombios_blank_crtc()
236 struct drm_device *dev = crtc->dev; in atombios_crtc_dpms()
237 struct radeon_device *rdev = dev->dev_private; in atombios_crtc_dpms()
242 radeon_crtc->enabled = true; in atombios_crtc_dpms()
249 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); in atombios_crtc_dpms()
255 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); in atombios_crtc_dpms()
256 if (radeon_crtc->enabled) in atombios_crtc_dpms()
261 radeon_crtc->enabled = false; in atombios_crtc_dpms()
273 struct drm_device *dev = crtc->dev; in atombios_set_crtc_dtd_timing()
274 struct radeon_device *rdev = dev->dev_private; in atombios_set_crtc_dtd_timing()
280 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2)); in atombios_set_crtc_dtd_timing()
282 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2)); in atombios_set_crtc_dtd_timing()
283 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2)); in atombios_set_crtc_dtd_timing()
285 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2)); in atombios_set_crtc_dtd_timing()
287 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border); in atombios_set_crtc_dtd_timing()
289 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); in atombios_set_crtc_dtd_timing()
291 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border); in atombios_set_crtc_dtd_timing()
293 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); in atombios_set_crtc_dtd_timing()
294 args.ucH_Border = radeon_crtc->h_border; in atombios_set_crtc_dtd_timing()
295 args.ucV_Border = radeon_crtc->v_border; in atombios_set_crtc_dtd_timing()
297 if (mode->flags & DRM_MODE_FLAG_NVSYNC) in atombios_set_crtc_dtd_timing()
299 if (mode->flags & DRM_MODE_FLAG_NHSYNC) in atombios_set_crtc_dtd_timing()
301 if (mode->flags & DRM_MODE_FLAG_CSYNC) in atombios_set_crtc_dtd_timing()
303 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in atombios_set_crtc_dtd_timing()
305 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) in atombios_set_crtc_dtd_timing()
309 args.ucCRTC = radeon_crtc->crtc_id; in atombios_set_crtc_dtd_timing()
311 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); in atombios_set_crtc_dtd_timing()
318 struct drm_device *dev = crtc->dev; in atombios_crtc_set_timing()
319 struct radeon_device *rdev = dev->dev_private; in atombios_crtc_set_timing()
325 args.usH_Total = cpu_to_le16(mode->crtc_htotal); in atombios_crtc_set_timing()
326 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay); in atombios_crtc_set_timing()
327 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start); in atombios_crtc_set_timing()
329 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); in atombios_crtc_set_timing()
330 args.usV_Total = cpu_to_le16(mode->crtc_vtotal); in atombios_crtc_set_timing()
331 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay); in atombios_crtc_set_timing()
332 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start); in atombios_crtc_set_timing()
334 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); in atombios_crtc_set_timing()
336 args.ucOverscanRight = radeon_crtc->h_border; in atombios_crtc_set_timing()
337 args.ucOverscanLeft = radeon_crtc->h_border; in atombios_crtc_set_timing()
338 args.ucOverscanBottom = radeon_crtc->v_border; in atombios_crtc_set_timing()
339 args.ucOverscanTop = radeon_crtc->v_border; in atombios_crtc_set_timing()
341 if (mode->flags & DRM_MODE_FLAG_NVSYNC) in atombios_crtc_set_timing()
343 if (mode->flags & DRM_MODE_FLAG_NHSYNC) in atombios_crtc_set_timing()
345 if (mode->flags & DRM_MODE_FLAG_CSYNC) in atombios_crtc_set_timing()
347 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in atombios_crtc_set_timing()
349 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) in atombios_crtc_set_timing()
353 args.ucCRTC = radeon_crtc->crtc_id; in atombios_crtc_set_timing()
355 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); in atombios_crtc_set_timing()
418 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; in atombios_crtc_program_ss()
422 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); in atombios_crtc_program_ss()
423 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); in atombios_crtc_program_ss()
427 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); in atombios_crtc_program_ss()
428 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); in atombios_crtc_program_ss()
439 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK)) in atombios_crtc_program_ss()
442 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); in atombios_crtc_program_ss()
443 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; in atombios_crtc_program_ss()
447 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); in atombios_crtc_program_ss()
448 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step); in atombios_crtc_program_ss()
452 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); in atombios_crtc_program_ss()
453 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step); in atombios_crtc_program_ss()
464 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE41(rdev)) in atombios_crtc_program_ss()
467 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); in atombios_crtc_program_ss()
468 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; in atombios_crtc_program_ss()
469 args.v1.ucSpreadSpectrumStep = ss->step; in atombios_crtc_program_ss()
470 args.v1.ucSpreadSpectrumDelay = ss->delay; in atombios_crtc_program_ss()
471 args.v1.ucSpreadSpectrumRange = ss->range; in atombios_crtc_program_ss()
475 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) || in atombios_crtc_program_ss()
476 (ss->type & ATOM_EXTERNAL_SS_MASK)) { in atombios_crtc_program_ss()
480 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); in atombios_crtc_program_ss()
481 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; in atombios_crtc_program_ss()
482 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step; in atombios_crtc_program_ss()
483 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay; in atombios_crtc_program_ss()
484 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range; in atombios_crtc_program_ss()
487 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) || in atombios_crtc_program_ss()
488 (ss->type & ATOM_EXTERNAL_SS_MASK)) { in atombios_crtc_program_ss()
492 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); in atombios_crtc_program_ss()
493 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; in atombios_crtc_program_ss()
494 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2; in atombios_crtc_program_ss()
495 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4; in atombios_crtc_program_ss()
498 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); in atombios_crtc_program_ss()
508 struct radeon_pll *pll, in atombios_adjust_pll() argument
512 struct drm_device *dev = crtc->dev; in atombios_adjust_pll()
513 struct radeon_device *rdev = dev->dev_private; in atombios_adjust_pll()
517 u32 adjusted_clock = mode->clock; in atombios_adjust_pll()
519 u32 dp_clock = mode->clock; in atombios_adjust_pll()
523 /* reset the pll flags */ in atombios_adjust_pll()
524 pll->flags = 0; in atombios_adjust_pll()
527 if ((rdev->family == CHIP_RS600) || in atombios_adjust_pll()
528 (rdev->family == CHIP_RS690) || in atombios_adjust_pll()
529 (rdev->family == CHIP_RS740)) in atombios_adjust_pll()
530 pll->flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/ in atombios_adjust_pll()
533 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */ in atombios_adjust_pll()
534 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; in atombios_adjust_pll()
536 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; in atombios_adjust_pll()
538 if (rdev->family < CHIP_RV770) in atombios_adjust_pll()
539 pll->flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP; in atombios_adjust_pll()
541 pll->flags |= RADEON_PLL_LEGACY; in atombios_adjust_pll()
543 if (mode->clock > 200000) /* range limits??? */ in atombios_adjust_pll()
544 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; in atombios_adjust_pll()
546 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; in atombios_adjust_pll()
549 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { in atombios_adjust_pll()
550 if (encoder->crtc == crtc) { in atombios_adjust_pll()
553 if (connector && connector->display_info.bpc) in atombios_adjust_pll()
554 bpc = connector->display_info.bpc; in atombios_adjust_pll()
556 is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock); in atombios_adjust_pll()
557 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || in atombios_adjust_pll()
562 radeon_connector->con_priv; in atombios_adjust_pll()
564 dp_clock = dig_connector->dp_clock; in atombios_adjust_pll()
569 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { in atombios_adjust_pll()
571 if (ss->refdiv) { in atombios_adjust_pll()
572 pll->flags |= RADEON_PLL_USE_REF_DIV; in atombios_adjust_pll()
573 pll->reference_div = ss->refdiv; in atombios_adjust_pll()
575 pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV; in atombios_adjust_pll()
581 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ in atombios_adjust_pll()
582 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) in atombios_adjust_pll()
583 adjusted_clock = mode->clock * 2; in atombios_adjust_pll()
584 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) in atombios_adjust_pll()
585 pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER; in atombios_adjust_pll()
586 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) in atombios_adjust_pll()
587 pll->flags |= RADEON_PLL_IS_LCD; in atombios_adjust_pll()
589 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) in atombios_adjust_pll()
590 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV; in atombios_adjust_pll()
591 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) in atombios_adjust_pll()
592 pll->flags |= RADEON_PLL_USE_REF_DIV; in atombios_adjust_pll()
598 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock in atombios_adjust_pll()
608 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, in atombios_adjust_pll()
619 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10); in atombios_adjust_pll()
620 args.v1.ucTransmitterID = radeon_encoder->encoder_id; in atombios_adjust_pll()
622 if (ss_enabled && ss->percentage) in atombios_adjust_pll()
626 atom_execute_table(rdev->mode_info.atom_context, in atombios_adjust_pll()
631 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10); in atombios_adjust_pll()
632 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id; in atombios_adjust_pll()
635 if (ss_enabled && ss->percentage) in atombios_adjust_pll()
643 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { in atombios_adjust_pll()
644 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; in atombios_adjust_pll()
648 cpu_to_le16((mode->clock * bpc / 8) / 10); in atombios_adjust_pll()
649 if (dig->coherent_mode) in atombios_adjust_pll()
663 atom_execute_table(rdev->mode_info.atom_context, in atombios_adjust_pll()
667 pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV; in atombios_adjust_pll()
668 pll->flags |= RADEON_PLL_USE_REF_DIV; in atombios_adjust_pll()
669 pll->reference_div = args.v3.sOutput.ucRefDiv; in atombios_adjust_pll()
672 pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV; in atombios_adjust_pll()
673 pll->flags |= RADEON_PLL_USE_POST_DIV; in atombios_adjust_pll()
674 pll->post_div = args.v3.sOutput.ucPostDiv; in atombios_adjust_pll()
712 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, in atombios_crtc_set_dcpll()
720 /* if the default dcpll clock is specified, in atombios_crtc_set_dcpll()
728 /* if the default dcpll clock is specified, in atombios_crtc_set_dcpll()
743 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); in atombios_crtc_set_dcpll()
751 u32 clock, in atombios_crtc_program_pll() argument
760 struct drm_device *dev = crtc->dev; in atombios_crtc_program_pll()
761 struct radeon_device *rdev = dev->dev_private; in atombios_crtc_program_pll()
768 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, in atombios_crtc_program_pll()
776 if (clock == ATOM_DISABLE) in atombios_crtc_program_pll()
778 args.v1.usPixelClock = cpu_to_le16(clock / 10); in atombios_crtc_program_pll()
788 args.v2.usPixelClock = cpu_to_le16(clock / 10); in atombios_crtc_program_pll()
798 args.v3.usPixelClock = cpu_to_le16(clock / 10); in atombios_crtc_program_pll()
805 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) in atombios_crtc_program_pll()
812 args.v5.usPixelClock = cpu_to_le16(clock / 10); in atombios_crtc_program_pll()
818 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) in atombios_crtc_program_pll()
834 args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10); in atombios_crtc_program_pll()
840 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) in atombios_crtc_program_pll()
871 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); in atombios_crtc_program_pll()
877 struct drm_device *dev = crtc->dev; in atombios_crtc_set_pll()
878 struct radeon_device *rdev = dev->dev_private; in atombios_crtc_set_pll()
881 u32 pll_clock = mode->clock; in atombios_crtc_set_pll()
883 struct radeon_pll *pll; in atombios_crtc_set_pll() local
890 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { in atombios_crtc_set_pll()
891 if (encoder->crtc == crtc) { in atombios_crtc_set_pll()
901 switch (radeon_crtc->pll_id) { in atombios_crtc_set_pll()
903 pll = &rdev->clock.p1pll; in atombios_crtc_set_pll()
906 pll = &rdev->clock.p2pll; in atombios_crtc_set_pll()
911 pll = &rdev->clock.dcpll; in atombios_crtc_set_pll()
915 if (radeon_encoder->active_device & in atombios_crtc_set_pll()
917 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; in atombios_crtc_set_pll()
923 radeon_connector->con_priv; in atombios_crtc_set_pll()
925 bpc = connector->display_info.bpc; in atombios_crtc_set_pll()
931 dp_clock = dig_connector->dp_clock / 10; in atombios_crtc_set_pll()
955 dig->lcd_ss_id, in atombios_crtc_set_pll()
956 mode->clock / 10); in atombios_crtc_set_pll()
959 dig->lcd_ss_id); in atombios_crtc_set_pll()
966 mode->clock / 10); in atombios_crtc_set_pll()
973 mode->clock / 10); in atombios_crtc_set_pll()
980 /* adjust pixel clock as needed */ in atombios_crtc_set_pll()
981 adjusted_clock = atombios_adjust_pll(crtc, mode, pll, ss_enabled, &ss); in atombios_crtc_set_pll()
983 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) in atombios_crtc_set_pll()
985 radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div, in atombios_crtc_set_pll()
988 radeon_compute_pll_avivo(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div, in atombios_crtc_set_pll()
991 radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div, in atombios_crtc_set_pll()
994 atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id, &ss); in atombios_crtc_set_pll()
996 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, in atombios_crtc_set_pll()
997 encoder_mode, radeon_encoder->encoder_id, mode->clock, in atombios_crtc_set_pll()
1006 ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) & in atombios_crtc_set_pll()
1010 (125 * 25 * pll->reference_freq / 100); in atombios_crtc_set_pll()
1013 (125 * 25 * pll->reference_freq / 100); in atombios_crtc_set_pll()
1017 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id, &ss); in atombios_crtc_set_pll()
1026 struct drm_device *dev = crtc->dev; in dce4_crtc_do_set_base()
1027 struct radeon_device *rdev = dev->dev_private; in dce4_crtc_do_set_base()
1039 if (!atomic && !crtc->fb) { in dce4_crtc_do_set_base()
1049 radeon_fb = to_radeon_framebuffer(crtc->fb); in dce4_crtc_do_set_base()
1050 target_fb = crtc->fb; in dce4_crtc_do_set_base()
1056 obj = radeon_fb->obj; in dce4_crtc_do_set_base()
1068 return -EINVAL; in dce4_crtc_do_set_base()
1075 switch (target_fb->bits_per_pixel) { in dce4_crtc_do_set_base()
1101 target_fb->bits_per_pixel); in dce4_crtc_do_set_base()
1102 return -EINVAL; in dce4_crtc_do_set_base()
1106 if (rdev->family >= CHIP_CAYMAN) in dce4_crtc_do_set_base()
1107 tmp = rdev->config.cayman.tile_config; in dce4_crtc_do_set_base()
1109 tmp = rdev->config.evergreen.tile_config; in dce4_crtc_do_set_base()
1141 switch (radeon_crtc->crtc_id) { in dce4_crtc_do_set_base()
1164 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1166 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1168 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1170 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1172 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); in dce4_crtc_do_set_base()
1173 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); in dce4_crtc_do_set_base()
1175 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); in dce4_crtc_do_set_base()
1176 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); in dce4_crtc_do_set_base()
1177 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0); in dce4_crtc_do_set_base()
1178 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0); in dce4_crtc_do_set_base()
1179 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); in dce4_crtc_do_set_base()
1180 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); in dce4_crtc_do_set_base()
1182 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); in dce4_crtc_do_set_base()
1183 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); in dce4_crtc_do_set_base()
1184 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1); in dce4_crtc_do_set_base()
1186 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1187 target_fb->height); in dce4_crtc_do_set_base()
1190 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1192 viewport_w = crtc->mode.hdisplay; in dce4_crtc_do_set_base()
1193 viewport_h = (crtc->mode.vdisplay + 1) & ~1; in dce4_crtc_do_set_base()
1194 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1198 /* make sure flip is at vb rather than hb */ in dce4_crtc_do_set_base()
1199 tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset); in dce4_crtc_do_set_base()
1201 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp); in dce4_crtc_do_set_base()
1204 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0); in dce4_crtc_do_set_base()
1206 if (!atomic && fb && fb != crtc->fb) { in dce4_crtc_do_set_base()
1208 rbo = gem_to_radeon_bo(radeon_fb->obj); in dce4_crtc_do_set_base()
1227 struct drm_device *dev = crtc->dev; in avivo_crtc_do_set_base()
1228 struct radeon_device *rdev = dev->dev_private; in avivo_crtc_do_set_base()
1240 if (!atomic && !crtc->fb) { in avivo_crtc_do_set_base()
1250 radeon_fb = to_radeon_framebuffer(crtc->fb); in avivo_crtc_do_set_base()
1251 target_fb = crtc->fb; in avivo_crtc_do_set_base()
1254 obj = radeon_fb->obj; in avivo_crtc_do_set_base()
1269 return -EINVAL; in avivo_crtc_do_set_base()
1275 switch (target_fb->bits_per_pixel) { in avivo_crtc_do_set_base()
1305 target_fb->bits_per_pixel); in avivo_crtc_do_set_base()
1306 return -EINVAL; in avivo_crtc_do_set_base()
1309 if (rdev->family >= CHIP_R600) { in avivo_crtc_do_set_base()
1322 if (radeon_crtc->crtc_id == 0) in avivo_crtc_do_set_base()
1327 if (rdev->family >= CHIP_RV770) { in avivo_crtc_do_set_base()
1328 if (radeon_crtc->crtc_id) { in avivo_crtc_do_set_base()
1336 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in avivo_crtc_do_set_base()
1339 radeon_crtc->crtc_offset, (u32) fb_location); in avivo_crtc_do_set_base()
1340 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); in avivo_crtc_do_set_base()
1341 if (rdev->family >= CHIP_R600) in avivo_crtc_do_set_base()
1342 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); in avivo_crtc_do_set_base()
1344 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); in avivo_crtc_do_set_base()
1345 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); in avivo_crtc_do_set_base()
1346 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); in avivo_crtc_do_set_base()
1347 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); in avivo_crtc_do_set_base()
1348 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); in avivo_crtc_do_set_base()
1349 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); in avivo_crtc_do_set_base()
1351 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); in avivo_crtc_do_set_base()
1352 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); in avivo_crtc_do_set_base()
1353 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); in avivo_crtc_do_set_base()
1355 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, in avivo_crtc_do_set_base()
1356 target_fb->height); in avivo_crtc_do_set_base()
1359 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, in avivo_crtc_do_set_base()
1361 viewport_w = crtc->mode.hdisplay; in avivo_crtc_do_set_base()
1362 viewport_h = (crtc->mode.vdisplay + 1) & ~1; in avivo_crtc_do_set_base()
1363 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, in avivo_crtc_do_set_base()
1367 /* make sure flip is at vb rather than hb */ in avivo_crtc_do_set_base()
1368 tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset); in avivo_crtc_do_set_base()
1370 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp); in avivo_crtc_do_set_base()
1373 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0); in avivo_crtc_do_set_base()
1375 if (!atomic && fb && fb != crtc->fb) { in avivo_crtc_do_set_base()
1377 rbo = gem_to_radeon_bo(radeon_fb->obj); in avivo_crtc_do_set_base()
1394 struct drm_device *dev = crtc->dev; in atombios_crtc_set_base()
1395 struct radeon_device *rdev = dev->dev_private; in atombios_crtc_set_base()
1409 struct drm_device *dev = crtc->dev; in atombios_crtc_set_base_atomic()
1410 struct radeon_device *rdev = dev->dev_private; in atombios_crtc_set_base_atomic()
1423 struct drm_device *dev = crtc->dev; in radeon_legacy_atom_fixup()
1424 struct radeon_device *rdev = dev->dev_private; in radeon_legacy_atom_fixup()
1428 switch (radeon_crtc->crtc_id) { in radeon_legacy_atom_fixup()
1447 struct drm_device *dev = crtc->dev; in radeon_atom_pick_pll()
1448 struct radeon_device *rdev = dev->dev_private; in radeon_atom_pick_pll()
1454 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { in radeon_atom_pick_pll()
1455 if (test_encoder->crtc && (test_encoder->crtc == crtc)) { in radeon_atom_pick_pll()
1456 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, in radeon_atom_pick_pll()
1458 * DCE4: PPLL or ext clock in radeon_atom_pick_pll()
1459 * DCE5: DCPLL or ext clock in radeon_atom_pick_pll()
1463 * crtc virtual pixel clock. in radeon_atom_pick_pll()
1466 if (ASIC_IS_DCE5(rdev) || rdev->clock.dp_extclk) in radeon_atom_pick_pll()
1473 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { in radeon_atom_pick_pll()
1480 if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) && in radeon_atom_pick_pll()
1481 (radeon_test_crtc->pll_id <= ATOM_PPLL2)) in radeon_atom_pick_pll()
1482 pll_in_use |= (1 << radeon_test_crtc->pll_id); in radeon_atom_pick_pll()
1488 return radeon_crtc->crtc_id; in radeon_atom_pick_pll()
1499 rdev->clock.default_dispclk); in radeon_atom_dcpll_init()
1503 atombios_crtc_set_dcpll(rdev, rdev->clock.default_dispclk); in radeon_atom_dcpll_init()
1516 struct drm_device *dev = crtc->dev; in atombios_crtc_mode_set()
1517 struct radeon_device *rdev = dev->dev_private; in atombios_crtc_mode_set()
1521 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { in atombios_crtc_mode_set()
1523 if (encoder->crtc == crtc) { in atombios_crtc_mode_set()
1525 if (radeon_encoder->active_device & in atombios_crtc_mode_set()
1542 if (radeon_crtc->crtc_id == 0) in atombios_crtc_mode_set()
1565 /* pick pll */ in atombios_crtc_prepare()
1566 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc); in atombios_crtc_prepare()
1585 switch (radeon_crtc->pll_id) { in atombios_crtc_disable()
1589 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, in atombios_crtc_disable()
1595 radeon_crtc->pll_id = -1; in atombios_crtc_disable()
1613 struct radeon_device *rdev = dev->dev_private; in radeon_atombios_init_crtc()
1616 switch (radeon_crtc->crtc_id) { in radeon_atombios_init_crtc()
1619 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET; in radeon_atombios_init_crtc()
1622 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET; in radeon_atombios_init_crtc()
1625 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET; in radeon_atombios_init_crtc()
1628 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET; in radeon_atombios_init_crtc()
1631 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET; in radeon_atombios_init_crtc()
1634 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET; in radeon_atombios_init_crtc()
1638 if (radeon_crtc->crtc_id == 1) in radeon_atombios_init_crtc()
1639 radeon_crtc->crtc_offset = in radeon_atombios_init_crtc()
1640 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; in radeon_atombios_init_crtc()
1642 radeon_crtc->crtc_offset = 0; in radeon_atombios_init_crtc()
1644 radeon_crtc->pll_id = -1; in radeon_atombios_init_crtc()
1645 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); in radeon_atombios_init_crtc()