Lines Matching +full:tras +full:- +full:max +full:- +full:ns
2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
211 UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios,
385 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
391 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
398 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
490 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
496 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode
737 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disab…
790 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disab…
841 …UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to prev…
1094 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1098 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1446 …// bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the sour…
1474 // =1: other external clock source, which is pre-defined
1522 …// =1: other external clock source, which is pre-defined …
1600 …UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other …
1601 …UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other …
1647 //Read operaion successeful when the paramter space is non-zero, otherwise read operation failed
1755 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
1756 // Bit[1]: 1-Ext. 0-Int.
1780 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
1781 // Bit[1]: 1-Ext. 0-Int.
1954 // bit1=0: non-coherent mode
2008 #define SET_VOLTAGE_GET_MAX_VOLTAGE 6 //Gets the Max. voltage for the soldered Asic
2094 …SIC_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600
2237 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2273 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2276 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
2310 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2313 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
2348 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2351 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
2387 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2390 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
2424 … usReserved11; //Was usMaxPixelClock; //In 10Khz unit, Max. Pclk used only fo…
2483 … For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock
2484 ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mod…
2497 ucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max …
2503 … Voltage regulator dependent PWM value. High 8 bits of the value for the max voltage.Set this on…
2508 …ndent PWM value. The value makes the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this…
2559 … // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us.
2564 ulBootUpEngineClock: Boot-up Engine Clock in 10Khz;
2565 ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present
2566 ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not …
2569 Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode;
2570 … or user customized mode. In this case, driver will just stick to this boot-up mode. No other Pow…
2577 Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT…
2578 …CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max H…
2588 …ord is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEV…
2590 ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion;
2591 …[7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are suppor…
2594 …[3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lan…
2595 …[7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station…
2598 …one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connect…
2600 [15:8] - Lane configuration attribute;
2601 [23:16]- Connector type, possible value:
2607 [31:24]- Reserved
2615 ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offs…
2623 usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode.
2629 usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value.
2657 // ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo - CPU type definition
2664 …X_CODE INTEGRATED_SYSTEM_INFO__AMD_CPU__PHARAOH // this deff reflects max defined CPU code
2853 // Bits0 = 0 - no CRT1 support= 1- CRT1 is supported
2854 // Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported
2855 // Bit 2 = 0 - no TV1 support= 1- TV1 is supported
2856 // Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported
2857 // Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported
2858 // Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported
2859 // Bit 6 = 0 - no DFP6 support= 1- DFP6 is supported
2860 // Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported
2861 // Bit 8 = 0 - no CV support= 1- CV is supported
2862 // Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported
2863 // Bit 10 = 0 - no DFP4 support= 1- DFP4 is supported
2864 // Bit 11 = 0 - no DFP5 support= 1- DFP5 is supported
2872 // [7:0] - I2C LINE Associate ID
2873 // = 0 - no I2C
2874 // [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection)
2876 // [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use
2878 // = 3-7 Reserved for future I2C engines
2879 // [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C
2984 // usModeMiscInfo-
2996 //usRefreshRate-
3178 // 0 0 0 - Color bit depth is undefined
3179 // 0 0 1 - 6 Bits per Primary Color
3180 // 0 1 0 - 8 Bits per Primary Color
3181 // 0 1 1 - 10 Bits per Primary Color
3182 // 1 0 0 - 12 Bits per Primary Color
3183 // 1 0 1 - 14 Bits per Primary Color
3184 // 1 1 0 - 16 Bits per Primary Color
3185 // 1 1 1 - Reserved
3223 // Bit7-3: Reserved
3253 // 0 0 0 - Color bit depth is undefined
3254 // 0 0 1 - 6 Bits per Primary Color
3255 // 0 1 0 - 8 Bits per Primary Color
3256 // 0 1 1 - 10 Bits per Primary Color
3257 // 1 0 0 - 12 Bits per Primary Color
3258 // 1 0 1 - 14 Bits per Primary Color
3259 // 1 1 0 - 16 Bits per Primary Color
3260 // 1 1 1 - Reserved
3427 // To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX
3430 #define VESA_MEMORY_IN_64K_BLOCK 0x100 //256*64K=16Mb (Max. VESA memory is 16Mb!)
3440 …(ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20)
3498 #define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)…
3521 FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB;
3525 FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB;
3527 FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB
3644 …UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC t…
3661 …UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC t…
3957 UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin
4006 …USHORT usReserved:15; // Bit1-15 may be defined for other capability in fu…
4010 …USHORT usReserved:15; // Bit1-15 may be defined for other capability in fu…
4116 UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage
4118 …UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /Vo…
4131 UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage
4202 …USHORT usFuseIndex[8]; //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse i…
4322 … Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine…
4347 …When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways …
4348 …1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determin…
4350 … Changing BL using VBIOS function is functional in both driver and non-driver present environment;
4353 …2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only ind…
4356 …Changing BL using VBIOS function could be functional in both driver and non-driver present environ…
4367 Bit[1]=0: DDR-DLL shut-down feature disabled.
4368 1: DDR-DLL shut-down feature enabled.
4369 Bit[2]=0: DDR-PLL Power down feature disabled.
4370 … 1: DDR-PLL Power down feature enabled.
4388 … GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns.
4389 ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconne…
4390 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
4391 ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns.
4392 ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns.
4941 …char*>(&(static_cast<ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*>(0))->FieldName)-static_cast<cha…
4943 …ADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableFormatRevisio…
4944 …DER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableContentRevisi…
4946 …ieldName) (((char*)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*)0)->FieldName)-(char*)0)/sizeo…
4948 …SION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevisio…
4949 …ION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevisi…
5252 #define UCODE_SIGNATURE 0x4375434d // 'MCuC' - MC uCode
5290 …fault MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
5291 …fault MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
5308 … ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for…
5317 …fault MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
5318 …fault MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
5337 UCHAR uctRAS; // tRAS
5367 UCHAR uctRAS; // tRAS
5400 UCHAR uctRAS; // tRAS
5440 … ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for…
5465 UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv
5486 … // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
5488 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
5491 …HAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlengt…
5496 … // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
5528 … // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
5530 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
5533 …HAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlengt…
5538 … // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
5547 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
5559 … // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
5561 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
5564 …HAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlengt…
5569 … // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
5578 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
5597 … // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2.
5599 …Size; // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
5607 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
5822 ULONG Reserved_1; // dd 0 ; reserved - always set to 0
5823 USHORT Reserved_2; // dw 0 ; reserved - always set to 0
6150 // [7:4] - connector type
6151 // = 1 - VGA connector
6152 // = 2 - DVI-I
6153 // = 3 - DVI-D
6154 // = 4 - DVI-A
6155 // = 5 - SVIDEO
6156 // = 6 - COMPOSITE
6157 // = 7 - LVDS
6158 // = 8 - DIGITAL LINK
6159 // = 9 - SCART
6160 // = 0xA - HDMI_type A
6161 // = 0xB - HDMI_type B
6162 // = 0xE - Special case1 (DVI+DIN)
6164 // [3:0] - DAC Associated
6165 // = 0 - no DAC
6166 // = 1 - DACA
6167 // = 2 - DACB
6168 // = 3 - External DAC
6233 UCHAR ucPLL_ChargePump; // PLL charge-pump gain control
6343 …SCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-…
6353 …ETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-Hi…
6363 …O2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver …
6476 UCHAR ucFanMinRPM; // Fan Minimum RPM (hundreds) -- for display purposes only.
6477 UCHAR ucFanMaxRPM; // Fan Maximum RPM (hundreds) -- for display purposes only.
6478 UCHAR ucReserved; // ----
6512 UCHAR ucClockStateIndices[1]; // variable-sized
6549 …GOTO_BOOT_ON_ALERT 0x2000 // Go to boot state on alerts, e.g. on an AC->DC transition.
6550 …IT_FOR_VBLANK_ON_ALERT 0x4000 // Do NOT wait for VBLANK during an alert (e.g. AC->DC transition).
6569 // offset from start of this table to array of ASIC-specific structures,
6662 // lanes - 1: 1, 2, 4, 8, 12, 16 permitted by PCIE spec
6666 // lookup into reduced refresh-rate table
6672 // 2-15 TBD as needed.
6768 UCHAR ucMaxHTLinkWidth; // From SBIOS - {2, 4, 8, 16}
6769 …UCHAR ucMinHTLinkWidth; // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled.…
6790 UCHAR vddcIndex; //2-bit vddc index;
6791 UCHAR leakage; //please use 8-bit absolute value, not the 6-bit % value
6805 //size of the state: sizeof(ATOM_PPLIB_STATE_V2) + (ucNumDPMLevels - 1) * sizeof(UCHAR)
6837 //how many non-clock levels we have. normally should be same as number of states