Lines Matching +full:simple +full:- +full:framebuffer
45 void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo); in nv50_crtc_lut_load()
48 NV_DEBUG_KMS(crtc->dev, "\n"); in nv50_crtc_lut_load()
51 writew(nv_crtc->lut.r[i] >> 2, lut + 8*i + 0); in nv50_crtc_lut_load()
52 writew(nv_crtc->lut.g[i] >> 2, lut + 8*i + 2); in nv50_crtc_lut_load()
53 writew(nv_crtc->lut.b[i] >> 2, lut + 8*i + 4); in nv50_crtc_lut_load()
56 if (nv_crtc->lut.depth == 30) { in nv50_crtc_lut_load()
57 writew(nv_crtc->lut.r[i - 1] >> 2, lut + 8*i + 0); in nv50_crtc_lut_load()
58 writew(nv_crtc->lut.g[i - 1] >> 2, lut + 8*i + 2); in nv50_crtc_lut_load()
59 writew(nv_crtc->lut.b[i - 1] >> 2, lut + 8*i + 4); in nv50_crtc_lut_load()
66 struct drm_device *dev = nv_crtc->base.dev; in nv50_crtc_blank()
67 struct drm_nouveau_private *dev_priv = dev->dev_private; in nv50_crtc_blank()
68 struct nouveau_channel *evo = nv50_display(dev)->master; in nv50_crtc_blank()
69 int index = nv_crtc->index, ret; in nv50_crtc_blank()
71 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index); in nv50_crtc_blank()
75 nv_crtc->cursor.hide(nv_crtc, false); in nv50_crtc_blank()
77 ret = RING_SPACE(evo, dev_priv->chipset != 0x50 ? 7 : 5); in nv50_crtc_blank()
85 if (dev_priv->chipset != 0x50) { in nv50_crtc_blank()
93 if (nv_crtc->cursor.visible) in nv50_crtc_blank()
94 nv_crtc->cursor.show(nv_crtc, false); in nv50_crtc_blank()
96 nv_crtc->cursor.hide(nv_crtc, false); in nv50_crtc_blank()
98 ret = RING_SPACE(evo, dev_priv->chipset != 0x50 ? 10 : 8); in nv50_crtc_blank()
104 OUT_RING(evo, nv_crtc->lut.depth == 8 ? in nv50_crtc_blank()
107 OUT_RING(evo, nv_crtc->lut.nvbo->bo.offset >> 8); in nv50_crtc_blank()
108 if (dev_priv->chipset != 0x50) { in nv50_crtc_blank()
114 OUT_RING(evo, nv_crtc->fb.offset >> 8); in nv50_crtc_blank()
117 if (dev_priv->chipset != 0x50) in nv50_crtc_blank()
118 if (nv_crtc->fb.tile_flags == 0x7a00 || in nv50_crtc_blank()
119 nv_crtc->fb.tile_flags == 0xfe00) in nv50_crtc_blank()
122 if (nv_crtc->fb.tile_flags == 0x7000) in nv50_crtc_blank()
130 nv_crtc->fb.blanked = blanked; in nv50_crtc_blank()
137 struct nouveau_channel *evo = nv50_display(nv_crtc->base.dev)->master; in nv50_crtc_set_dither()
140 int head = nv_crtc->index, ret; in nv50_crtc_set_dither()
144 connector = &nv_connector->base; in nv50_crtc_set_dither()
145 if (nv_connector->dithering_mode == DITHERING_MODE_AUTO) { in nv50_crtc_set_dither()
146 if (nv_crtc->base.fb->depth > connector->display_info.bpc * 3) in nv50_crtc_set_dither()
149 mode = nv_connector->dithering_mode; in nv50_crtc_set_dither()
152 if (nv_connector->dithering_depth == DITHERING_DEPTH_AUTO) { in nv50_crtc_set_dither()
153 if (connector->display_info.bpc >= 8) in nv50_crtc_set_dither()
156 mode |= nv_connector->dithering_depth; in nv50_crtc_set_dither()
176 struct drm_device *dev = nv_crtc->base.dev; in nouveau_crtc_connector_get()
182 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { in nouveau_crtc_connector_get()
183 if (connector->encoder) in nouveau_crtc_connector_get()
184 if (connector->encoder->crtc == crtc) in nouveau_crtc_connector_get()
195 struct drm_crtc *crtc = &nv_crtc->base; in nv50_crtc_set_scale()
196 struct drm_device *dev = crtc->dev; in nv50_crtc_set_scale()
197 struct nouveau_channel *evo = nv50_display(dev)->master; in nv50_crtc_set_scale()
198 struct drm_display_mode *umode = &crtc->mode; in nv50_crtc_set_scale()
206 if (!nv_connector || !nv_connector->native_mode) { in nv50_crtc_set_scale()
210 scaling_mode = nv_connector->scaling_mode; in nv50_crtc_set_scale()
217 omode = nv_connector->native_mode; in nv50_crtc_set_scale()
221 oX = omode->hdisplay; in nv50_crtc_set_scale()
222 oY = omode->vdisplay; in nv50_crtc_set_scale()
223 if (omode->flags & DRM_MODE_FLAG_DBLSCAN) in nv50_crtc_set_scale()
230 if (nv_connector && ( nv_connector->underscan == UNDERSCAN_ON || in nv50_crtc_set_scale()
231 (nv_connector->underscan == UNDERSCAN_AUTO && in nv50_crtc_set_scale()
232 nv_connector->edid && in nv50_crtc_set_scale()
233 drm_detect_hdmi_monitor(nv_connector->edid)))) { in nv50_crtc_set_scale()
234 u32 bX = nv_connector->underscan_hborder; in nv50_crtc_set_scale()
235 u32 bY = nv_connector->underscan_vborder; in nv50_crtc_set_scale()
239 oX -= (bX * 2); in nv50_crtc_set_scale()
240 if (bY) oY -= (bY * 2); in nv50_crtc_set_scale()
243 oX -= (oX >> 4) + 32; in nv50_crtc_set_scale()
244 if (bY) oY -= (bY * 2); in nv50_crtc_set_scale()
254 oX = min((u32)umode->hdisplay, oX); in nv50_crtc_set_scale()
255 oY = min((u32)umode->vdisplay, oY); in nv50_crtc_set_scale()
256 /* fall-through */ in nv50_crtc_set_scale()
259 u32 aspect = (umode->hdisplay << 19) / umode->vdisplay; in nv50_crtc_set_scale()
262 u32 aspect = (umode->vdisplay << 19) / umode->hdisplay; in nv50_crtc_set_scale()
270 if (umode->hdisplay != oX || umode->vdisplay != oY || in nv50_crtc_set_scale()
271 umode->flags & DRM_MODE_FLAG_INTERLACE || in nv50_crtc_set_scale()
272 umode->flags & DRM_MODE_FLAG_DBLSCAN) in nv50_crtc_set_scale()
279 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, SCALE_CTRL), 1); in nv50_crtc_set_scale()
281 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, SCALE_RES1), 2); in nv50_crtc_set_scale()
288 nv50_display_flip_next(crtc, crtc->fb, NULL); in nv50_crtc_set_scale()
297 struct drm_nouveau_private *dev_priv = dev->dev_private; in nv50_crtc_set_clock()
320 if (dev_priv->chipset < NV_C0) { in nv50_crtc_set_clock()
357 dev = crtc->dev; in nv50_crtc_destroy()
362 drm_crtc_cleanup(&nv_crtc->base); in nv50_crtc_destroy()
364 nouveau_bo_unmap(nv_crtc->lut.nvbo); in nv50_crtc_destroy()
365 nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo); in nv50_crtc_destroy()
366 nouveau_bo_unmap(nv_crtc->cursor.nvbo); in nv50_crtc_destroy()
367 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); in nv50_crtc_destroy()
375 struct drm_device *dev = crtc->dev; in nv50_crtc_cursor_set()
382 nv_crtc->cursor.hide(nv_crtc, true); in nv50_crtc_cursor_set()
387 return -EINVAL; in nv50_crtc_cursor_set()
391 return -ENOENT; in nv50_crtc_cursor_set()
398 /* The simple will do for now. */ in nv50_crtc_cursor_set()
400 nouveau_bo_wr32(nv_crtc->cursor.nvbo, i, nouveau_bo_rd32(cursor, i)); in nv50_crtc_cursor_set()
404 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.nvbo->bo.offset); in nv50_crtc_cursor_set()
405 nv_crtc->cursor.show(nv_crtc, true); in nv50_crtc_cursor_set()
417 nv_crtc->cursor.set_pos(nv_crtc, x, y); in nv50_crtc_cursor_move()
429 nv_crtc->lut.r[i] = r[i]; in nv50_crtc_gamma_set()
430 nv_crtc->lut.g[i] = g[i]; in nv50_crtc_gamma_set()
431 nv_crtc->lut.b[i] = b[i]; in nv50_crtc_gamma_set()
435 * get called before a framebuffer is bound. If this is the case, in nv50_crtc_gamma_set()
439 if (!nv_crtc->base.fb) { in nv50_crtc_gamma_set()
440 nv_crtc->lut.depth = 0; in nv50_crtc_gamma_set()
450 NV_ERROR(crtc->dev, "!!\n"); in nv50_crtc_save()
456 NV_ERROR(crtc->dev, "!!\n"); in nv50_crtc_restore()
479 struct drm_device *dev = crtc->dev; in nv50_crtc_prepare()
481 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index); in nv50_crtc_prepare()
484 drm_vblank_pre_modeset(dev, nv_crtc->index); in nv50_crtc_prepare()
491 struct drm_device *dev = crtc->dev; in nv50_crtc_commit()
494 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index); in nv50_crtc_commit()
497 drm_vblank_post_modeset(dev, nv_crtc->index); in nv50_crtc_commit()
499 nv50_display_flip_next(crtc, crtc->fb, NULL); in nv50_crtc_commit()
515 struct drm_device *dev = nv_crtc->base.dev; in nv50_crtc_do_mode_set_base()
516 struct drm_nouveau_private *dev_priv = dev->dev_private; in nv50_crtc_do_mode_set_base()
517 struct nouveau_channel *evo = nv50_display(dev)->master; in nv50_crtc_do_mode_set_base()
522 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index); in nv50_crtc_do_mode_set_base()
525 if (!atomic && !crtc->fb) { in nv50_crtc_do_mode_set_base()
538 drm_fb = crtc->fb; in nv50_crtc_do_mode_set_base()
539 fb = nouveau_framebuffer(crtc->fb); in nv50_crtc_do_mode_set_base()
543 ret = nouveau_bo_pin(fb->nvbo, TTM_PL_FLAG_VRAM); in nv50_crtc_do_mode_set_base()
549 nouveau_bo_unpin(ofb->nvbo); in nv50_crtc_do_mode_set_base()
553 nv_crtc->fb.offset = fb->nvbo->bo.offset; in nv50_crtc_do_mode_set_base()
554 nv_crtc->fb.tile_flags = nouveau_bo_tile_layout(fb->nvbo); in nv50_crtc_do_mode_set_base()
555 nv_crtc->fb.cpp = drm_fb->bits_per_pixel / 8; in nv50_crtc_do_mode_set_base()
556 if (!nv_crtc->fb.blanked && dev_priv->chipset != 0x50) { in nv50_crtc_do_mode_set_base()
561 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_DMA), 1); in nv50_crtc_do_mode_set_base()
562 OUT_RING (evo, fb->r_dma); in nv50_crtc_do_mode_set_base()
569 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_OFFSET), 5); in nv50_crtc_do_mode_set_base()
570 OUT_RING (evo, nv_crtc->fb.offset >> 8); in nv50_crtc_do_mode_set_base()
572 OUT_RING (evo, (drm_fb->height << 16) | drm_fb->width); in nv50_crtc_do_mode_set_base()
573 OUT_RING (evo, fb->r_pitch); in nv50_crtc_do_mode_set_base()
574 OUT_RING (evo, fb->r_format); in nv50_crtc_do_mode_set_base()
576 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, CLUT_MODE), 1); in nv50_crtc_do_mode_set_base()
577 OUT_RING (evo, fb->base.depth == 8 ? in nv50_crtc_do_mode_set_base()
580 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, COLOR_CTRL), 1); in nv50_crtc_do_mode_set_base()
582 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_POS), 1); in nv50_crtc_do_mode_set_base()
585 if (nv_crtc->lut.depth != fb->base.depth) { in nv50_crtc_do_mode_set_base()
586 nv_crtc->lut.depth = fb->base.depth; in nv50_crtc_do_mode_set_base()
598 struct drm_device *dev = crtc->dev; in nv50_crtc_mode_set()
599 struct nouveau_channel *evo = nv50_display(dev)->master; in nv50_crtc_mode_set()
601 u32 head = nv_crtc->index * 0x400; in nv50_crtc_mode_set()
602 u32 ilace = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 1; in nv50_crtc_mode_set()
603 u32 vscan = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1; in nv50_crtc_mode_set()
611 * <sync> <back porch> <---------display---------> <front porch> in nv50_crtc_mode_set()
613 * |____________|---------------------------|____________| in nv50_crtc_mode_set()
621 hactive = mode->htotal; in nv50_crtc_mode_set()
622 hsynce = mode->hsync_end - mode->hsync_start - 1; in nv50_crtc_mode_set()
623 hbackp = mode->htotal - mode->hsync_end; in nv50_crtc_mode_set()
625 hfrontp = mode->hsync_start - mode->hdisplay; in nv50_crtc_mode_set()
626 hblanks = mode->htotal - hfrontp - 1; in nv50_crtc_mode_set()
628 vactive = mode->vtotal * vscan / ilace; in nv50_crtc_mode_set()
629 vsynce = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1; in nv50_crtc_mode_set()
630 vbackp = (mode->vtotal - mode->vsync_end) * vscan / ilace; in nv50_crtc_mode_set()
632 vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace; in nv50_crtc_mode_set()
633 vblanks = vactive - vfrontp - 1; in nv50_crtc_mode_set()
634 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { in nv50_crtc_mode_set()
636 vblan2s = vblan2e + (mode->vdisplay * vscan / ilace); in nv50_crtc_mode_set()
643 OUT_RING (evo, 0x00800000 | mode->clock); in nv50_crtc_mode_set()
657 OUT_RING (evo, (umode->vdisplay << 16) | umode->hdisplay); in nv50_crtc_mode_set()
662 nv_crtc->set_dither(nv_crtc, false); in nv50_crtc_mode_set()
663 nv_crtc->set_scale(nv_crtc, false); in nv50_crtc_mode_set()
679 ret = nv50_display_sync(crtc->dev); in nv50_crtc_mode_set_base()
683 return nv50_display_flip_next(crtc, crtc->fb, NULL); in nv50_crtc_mode_set_base()
698 return nv50_display_sync(crtc->dev); in nv50_crtc_mode_set_base_atomic()
722 return -ENOMEM; in nv50_crtc_create()
728 nv_crtc->lut.r[i] = i << 8; in nv50_crtc_create()
729 nv_crtc->lut.g[i] = i << 8; in nv50_crtc_create()
730 nv_crtc->lut.b[i] = i << 8; in nv50_crtc_create()
732 nv_crtc->lut.depth = 0; in nv50_crtc_create()
735 0, 0x0000, &nv_crtc->lut.nvbo); in nv50_crtc_create()
737 ret = nouveau_bo_pin(nv_crtc->lut.nvbo, TTM_PL_FLAG_VRAM); in nv50_crtc_create()
739 ret = nouveau_bo_map(nv_crtc->lut.nvbo); in nv50_crtc_create()
741 nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo); in nv50_crtc_create()
749 nv_crtc->index = index; in nv50_crtc_create()
752 nv_crtc->set_dither = nv50_crtc_set_dither; in nv50_crtc_create()
753 nv_crtc->set_scale = nv50_crtc_set_scale; in nv50_crtc_create()
755 drm_crtc_init(dev, &nv_crtc->base, &nv50_crtc_funcs); in nv50_crtc_create()
756 drm_crtc_helper_add(&nv_crtc->base, &nv50_crtc_helper_funcs); in nv50_crtc_create()
757 drm_mode_crtc_set_gamma_size(&nv_crtc->base, 256); in nv50_crtc_create()
760 0, 0x0000, &nv_crtc->cursor.nvbo); in nv50_crtc_create()
762 ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM); in nv50_crtc_create()
764 ret = nouveau_bo_map(nv_crtc->cursor.nvbo); in nv50_crtc_create()
766 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); in nv50_crtc_create()