Lines Matching +full:fixed +full:- +full:factor +full:- +full:clock
5 * Copyright 2007-2009 Stuart Bennett
55 * this does not give a correct answer for off-chip dvi, but there's no in nv04_dfp_get_bound_head()
58 int ramdac = (dcbent->or & OUTPUT_C) >> 2; in nv04_dfp_get_bound_head()
69 * Luckily we do know the values ;-) in nv04_dfp_bind_head()
75 int ramdac = (dcbent->or & OUTPUT_C) >> 2; in nv04_dfp_bind_head()
81 if (dcbent->type == OUTPUT_LVDS) in nv04_dfp_bind_head()
84 nv_write_tmds(dev, dcbent->or, 0, 0x04, tmds04); in nv04_dfp_bind_head()
87 nv_write_tmds(dev, dcbent->or, 1, 0x04, tmds04 ^ 0x08); in nv04_dfp_bind_head()
92 struct drm_nouveau_private *dev_priv = dev->dev_private; in nv04_dfp_disable()
93 struct nv04_crtc_reg *crtcstate = dev_priv->mode_reg.crtc_reg; in nv04_dfp_disable()
113 struct drm_device *dev = encoder->dev; in nv04_dfp_update_fp_control()
114 struct drm_nouveau_private *dev_priv = dev->dev_private; in nv04_dfp_update_fp_control()
120 nv_crtc = nouveau_crtc(encoder->crtc); in nv04_dfp_update_fp_control()
121 fpc = &dev_priv->mode_reg.crtc_reg[nv_crtc->index].fp_control; in nv04_dfp_update_fp_control()
128 *fpc = nv_crtc->dpms_saved_fp_control; in nv04_dfp_update_fp_control()
131 nv_crtc->fp_users |= 1 << nouveau_encoder(encoder)->dcb->index; in nv04_dfp_update_fp_control()
132 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_FP_TG_CONTROL, *fpc); in nv04_dfp_update_fp_control()
134 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { in nv04_dfp_update_fp_control()
136 fpc = &dev_priv->mode_reg.crtc_reg[nv_crtc->index].fp_control; in nv04_dfp_update_fp_control()
138 nv_crtc->fp_users &= ~(1 << nouveau_encoder(encoder)->dcb->index); in nv04_dfp_update_fp_control()
139 if (!is_fpc_off(*fpc) && !nv_crtc->fp_users) { in nv04_dfp_update_fp_control()
140 nv_crtc->dpms_saved_fp_control = *fpc; in nv04_dfp_update_fp_control()
144 NVWriteRAMDAC(dev, nv_crtc->index, in nv04_dfp_update_fp_control()
153 struct drm_device *dev = encoder->dev; in get_tmds_slave()
154 struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb; in get_tmds_slave()
157 if (dcb->type != OUTPUT_TMDS || dcb->location == DCB_LOC_ON_CHIP) in get_tmds_slave()
163 * always hard-wired to a reasonable configuration using straps, in get_tmds_slave()
170 list_for_each_entry(slave, &dev->mode_config.encoder_list, head) { in get_tmds_slave()
171 struct dcb_entry *slave_dcb = nouveau_encoder(slave)->dcb; in get_tmds_slave()
173 if (slave_dcb->type == OUTPUT_TMDS && get_slave_funcs(slave) && in get_tmds_slave()
174 slave_dcb->tmdsconf.slave_addr == dcb->tmdsconf.slave_addr) in get_tmds_slave()
188 if (!nv_connector->native_mode || in nv04_dfp_mode_fixup()
189 nv_connector->scaling_mode == DRM_MODE_SCALE_NONE || in nv04_dfp_mode_fixup()
190 mode->hdisplay > nv_connector->native_mode->hdisplay || in nv04_dfp_mode_fixup()
191 mode->vdisplay > nv_connector->native_mode->vdisplay) { in nv04_dfp_mode_fixup()
192 nv_encoder->mode = *adjusted_mode; in nv04_dfp_mode_fixup()
195 nv_encoder->mode = *nv_connector->native_mode; in nv04_dfp_mode_fixup()
196 adjusted_mode->clock = nv_connector->native_mode->clock; in nv04_dfp_mode_fixup()
205 struct drm_nouveau_private *dev_priv = dev->dev_private; in nv04_dfp_prepare_sel_clk()
206 struct nv04_mode_state *state = &dev_priv->mode_reg; in nv04_dfp_prepare_sel_clk()
207 uint32_t bits1618 = nv_encoder->dcb->or & OUTPUT_A ? 0x10000 : 0x40000; in nv04_dfp_prepare_sel_clk()
209 if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP) in nv04_dfp_prepare_sel_clk()
217 state->sel_clk |= bits1618; in nv04_dfp_prepare_sel_clk()
219 state->sel_clk &= ~bits1618; in nv04_dfp_prepare_sel_clk()
231 * bits 8&10 seen on dual-link dvi outputs, purpose unknown (set by POST scripts) in nv04_dfp_prepare_sel_clk()
233 * and which bit-pair to use, is unclear on nv40 (for earlier cards, the fp table in nv04_dfp_prepare_sel_clk()
236 if (nv_encoder->dcb->type == OUTPUT_LVDS && dev_priv->saved_reg.sel_clk & 0xf0) { in nv04_dfp_prepare_sel_clk()
237 int shift = (dev_priv->saved_reg.sel_clk & 0x50) ? 0 : 1; in nv04_dfp_prepare_sel_clk()
239 state->sel_clk &= ~0xf0; in nv04_dfp_prepare_sel_clk()
240 state->sel_clk |= (head ? 0x40 : 0x10) << shift; in nv04_dfp_prepare_sel_clk()
247 struct drm_encoder_helper_funcs *helper = encoder->helper_private; in nv04_dfp_prepare()
248 struct drm_device *dev = encoder->dev; in nv04_dfp_prepare()
249 struct drm_nouveau_private *dev_priv = dev->dev_private; in nv04_dfp_prepare()
250 int head = nouveau_crtc(encoder->crtc)->index; in nv04_dfp_prepare()
251 struct nv04_crtc_reg *crtcstate = dev_priv->mode_reg.crtc_reg; in nv04_dfp_prepare()
255 helper->dpms(encoder, DRM_MODE_DPMS_OFF); in nv04_dfp_prepare()
262 if (nv_encoder->dcb->location == DCB_LOC_ON_CHIP) in nv04_dfp_prepare()
265 *cr_lcd |= (nv_encoder->dcb->or << 4) & 0x30; in nv04_dfp_prepare()
266 if (nv_encoder->dcb->type == OUTPUT_LVDS) in nv04_dfp_prepare()
284 struct drm_device *dev = encoder->dev; in nv04_dfp_mode_set()
285 struct drm_nouveau_private *dev_priv = dev->dev_private; in nv04_dfp_mode_set()
286 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); in nv04_dfp_mode_set()
287 struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index]; in nv04_dfp_mode_set()
288 struct nv04_crtc_reg *savep = &dev_priv->saved_reg.crtc_reg[nv_crtc->index]; in nv04_dfp_mode_set()
291 struct drm_display_mode *output_mode = &nv_encoder->mode; in nv04_dfp_mode_set()
292 struct drm_connector *connector = &nv_connector->base; in nv04_dfp_mode_set()
295 NV_DEBUG_KMS(dev, "Output mode on CRTC %d:\n", nv_crtc->index); in nv04_dfp_mode_set()
299 regp->fp_horiz_regs[FP_DISPLAY_END] = output_mode->hdisplay - 1; in nv04_dfp_mode_set()
300 regp->fp_horiz_regs[FP_TOTAL] = output_mode->htotal - 1; in nv04_dfp_mode_set()
302 (output_mode->hsync_start - output_mode->hdisplay) >= in nv04_dfp_mode_set()
303 dev_priv->vbios.digital_min_front_porch) in nv04_dfp_mode_set()
304 regp->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay; in nv04_dfp_mode_set()
306 …regp->fp_horiz_regs[FP_CRTC] = output_mode->hsync_start - dev_priv->vbios.digital_min_front_porch … in nv04_dfp_mode_set()
307 regp->fp_horiz_regs[FP_SYNC_START] = output_mode->hsync_start - 1; in nv04_dfp_mode_set()
308 regp->fp_horiz_regs[FP_SYNC_END] = output_mode->hsync_end - 1; in nv04_dfp_mode_set()
309 regp->fp_horiz_regs[FP_VALID_START] = output_mode->hskew; in nv04_dfp_mode_set()
310 regp->fp_horiz_regs[FP_VALID_END] = output_mode->hdisplay - 1; in nv04_dfp_mode_set()
312 regp->fp_vert_regs[FP_DISPLAY_END] = output_mode->vdisplay - 1; in nv04_dfp_mode_set()
313 regp->fp_vert_regs[FP_TOTAL] = output_mode->vtotal - 1; in nv04_dfp_mode_set()
314 regp->fp_vert_regs[FP_CRTC] = output_mode->vtotal - 5 - 1; in nv04_dfp_mode_set()
315 regp->fp_vert_regs[FP_SYNC_START] = output_mode->vsync_start - 1; in nv04_dfp_mode_set()
316 regp->fp_vert_regs[FP_SYNC_END] = output_mode->vsync_end - 1; in nv04_dfp_mode_set()
317 regp->fp_vert_regs[FP_VALID_START] = 0; in nv04_dfp_mode_set()
318 regp->fp_vert_regs[FP_VALID_END] = output_mode->vdisplay - 1; in nv04_dfp_mode_set()
321 regp->fp_control = NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS | in nv04_dfp_mode_set()
322 (savep->fp_control & (1 << 26 | NV_PRAMDAC_FP_TG_CONTROL_READ_PROG)); in nv04_dfp_mode_set()
325 if (output_mode->flags & DRM_MODE_FLAG_PVSYNC) in nv04_dfp_mode_set()
326 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS; in nv04_dfp_mode_set()
327 if (output_mode->flags & DRM_MODE_FLAG_PHSYNC) in nv04_dfp_mode_set()
328 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS; in nv04_dfp_mode_set()
330 if (nv_connector->scaling_mode == DRM_MODE_SCALE_NONE || in nv04_dfp_mode_set()
331 nv_connector->scaling_mode == DRM_MODE_SCALE_CENTER) /* panel handles it */ in nv04_dfp_mode_set()
332 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_CENTER; in nv04_dfp_mode_set()
333 else if (adjusted_mode->hdisplay == output_mode->hdisplay && in nv04_dfp_mode_set()
334 adjusted_mode->vdisplay == output_mode->vdisplay) /* native mode */ in nv04_dfp_mode_set()
335 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_NATIVE; in nv04_dfp_mode_set()
337 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_SCALE; in nv04_dfp_mode_set()
339 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12; in nv04_dfp_mode_set()
340 if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP && in nv04_dfp_mode_set()
341 output_mode->clock > 165000) in nv04_dfp_mode_set()
342 regp->fp_control |= (2 << 24); in nv04_dfp_mode_set()
343 if (nv_encoder->dcb->type == OUTPUT_LVDS) { in nv04_dfp_mode_set()
345 if (nv_connector->edid && in nv04_dfp_mode_set()
346 nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) { in nv04_dfp_mode_set()
347 duallink = (((u8 *)nv_connector->edid)[121] == 2); in nv04_dfp_mode_set()
349 nouveau_bios_parse_lvds_table(dev, output_mode->clock, in nv04_dfp_mode_set()
354 regp->fp_control |= (8 << 28); in nv04_dfp_mode_set()
356 if (output_mode->clock > 165000) in nv04_dfp_mode_set()
357 regp->fp_control |= (8 << 28); in nv04_dfp_mode_set()
359 regp->fp_debug_0 = NV_PRAMDAC_FP_DEBUG_0_YWEIGHT_ROUND | in nv04_dfp_mode_set()
368 regp->fp_debug_1 = 0; in nv04_dfp_mode_set()
370 regp->fp_debug_2 = 0; in nv04_dfp_mode_set()
372 /* Use 20.12 fixed point format to avoid floats */ in nv04_dfp_mode_set()
373 mode_ratio = (1 << 12) * adjusted_mode->hdisplay / adjusted_mode->vdisplay; in nv04_dfp_mode_set()
374 panel_ratio = (1 << 12) * output_mode->hdisplay / output_mode->vdisplay; in nv04_dfp_mode_set()
377 if (nv_connector->scaling_mode == DRM_MODE_SCALE_ASPECT && in nv04_dfp_mode_set()
384 * horizontal needs to be scaled at vertical scale factor in nv04_dfp_mode_set()
387 scale = (1 << 12) * adjusted_mode->vdisplay / output_mode->vdisplay; in nv04_dfp_mode_set()
388 regp->fp_debug_1 = NV_PRAMDAC_FP_DEBUG_1_XSCALE_TESTMODE_ENABLE | in nv04_dfp_mode_set()
392 diff = output_mode->hdisplay - in nv04_dfp_mode_set()
393 output_mode->vdisplay * mode_ratio / (1 << 12); in nv04_dfp_mode_set()
394 regp->fp_horiz_regs[FP_VALID_START] += diff / 2; in nv04_dfp_mode_set()
395 regp->fp_horiz_regs[FP_VALID_END] -= diff / 2; in nv04_dfp_mode_set()
400 * vertical needs to be scaled at horizontal scale factor in nv04_dfp_mode_set()
403 scale = (1 << 12) * adjusted_mode->hdisplay / output_mode->hdisplay; in nv04_dfp_mode_set()
404 regp->fp_debug_1 = NV_PRAMDAC_FP_DEBUG_1_YSCALE_TESTMODE_ENABLE | in nv04_dfp_mode_set()
408 diff = output_mode->vdisplay - in nv04_dfp_mode_set()
409 (1 << 12) * output_mode->hdisplay / mode_ratio; in nv04_dfp_mode_set()
410 regp->fp_vert_regs[FP_VALID_START] += diff / 2; in nv04_dfp_mode_set()
411 regp->fp_vert_regs[FP_VALID_END] -= diff / 2; in nv04_dfp_mode_set()
416 if ((nv_connector->dithering_mode == DITHERING_MODE_ON) || in nv04_dfp_mode_set()
417 (nv_connector->dithering_mode == DITHERING_MODE_AUTO && in nv04_dfp_mode_set()
418 encoder->crtc->fb->depth > connector->display_info.bpc * 3)) { in nv04_dfp_mode_set()
419 if (dev_priv->chipset == 0x11) in nv04_dfp_mode_set()
420 regp->dither = savep->dither | 0x00010000; in nv04_dfp_mode_set()
423 regp->dither = savep->dither | 0x00000001; in nv04_dfp_mode_set()
425 regp->dither_regs[i] = 0xe4e4e4e4; in nv04_dfp_mode_set()
426 regp->dither_regs[i + 3] = 0x44444444; in nv04_dfp_mode_set()
430 if (dev_priv->chipset != 0x11) { in nv04_dfp_mode_set()
434 regp->dither_regs[i] = savep->dither_regs[i]; in nv04_dfp_mode_set()
435 regp->dither_regs[i + 3] = savep->dither_regs[i + 3]; in nv04_dfp_mode_set()
438 regp->dither = savep->dither; in nv04_dfp_mode_set()
441 regp->fp_margin_color = 0; in nv04_dfp_mode_set()
446 struct drm_device *dev = encoder->dev; in nv04_dfp_commit()
447 struct drm_nouveau_private *dev_priv = dev->dev_private; in nv04_dfp_commit()
448 struct drm_encoder_helper_funcs *helper = encoder->helper_private; in nv04_dfp_commit()
449 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); in nv04_dfp_commit()
451 struct dcb_entry *dcbe = nv_encoder->dcb; in nv04_dfp_commit()
452 int head = nouveau_crtc(encoder->crtc)->index; in nv04_dfp_commit()
455 if (dcbe->type == OUTPUT_TMDS) in nv04_dfp_commit()
456 run_tmds_table(dev, dcbe, head, nv_encoder->mode.clock); in nv04_dfp_commit()
457 else if (dcbe->type == OUTPUT_LVDS) in nv04_dfp_commit()
458 call_lvds_script(dev, dcbe, head, LVDS_RESET, nv_encoder->mode.clock); in nv04_dfp_commit()
462 dev_priv->mode_reg.crtc_reg[head].fp_control = in nv04_dfp_commit()
466 if (dev_priv->chipset < 0x44) in nv04_dfp_commit()
474 get_slave_funcs(slave_encoder)->mode_set( in nv04_dfp_commit()
475 slave_encoder, &nv_encoder->mode, &nv_encoder->mode); in nv04_dfp_commit()
477 helper->dpms(encoder, DRM_MODE_DPMS_ON); in nv04_dfp_commit()
480 drm_get_connector_name(&nouveau_encoder_connector_get(nv_encoder)->base), in nv04_dfp_commit()
481 nv_crtc->index, '@' + ffs(nv_encoder->dcb->or)); in nv04_dfp_commit()
487 struct drm_device *dev = encoder->dev; in nv04_dfp_update_backlight()
492 if (dev->pci_device == 0x0179 || dev->pci_device == 0x0189 || in nv04_dfp_update_backlight()
493 dev->pci_device == 0x0329) { in nv04_dfp_update_backlight()
512 struct drm_device *dev = encoder->dev; in nv04_lvds_dpms()
513 struct drm_crtc *crtc = encoder->crtc; in nv04_lvds_dpms()
514 struct drm_nouveau_private *dev_priv = dev->dev_private; in nv04_lvds_dpms()
516 bool was_powersaving = is_powersaving_dpms(nv_encoder->last_dpms); in nv04_lvds_dpms()
518 if (nv_encoder->last_dpms == mode) in nv04_lvds_dpms()
520 nv_encoder->last_dpms = mode; in nv04_lvds_dpms()
523 mode, nv_encoder->dcb->index); in nv04_lvds_dpms()
528 if (nv_encoder->dcb->lvdsconf.use_power_scripts) { in nv04_lvds_dpms()
532 int head = crtc ? nouveau_crtc(crtc)->index : in nv04_lvds_dpms()
533 nv04_dfp_get_bound_head(dev, nv_encoder->dcb); in nv04_lvds_dpms()
536 call_lvds_script(dev, nv_encoder->dcb, head, in nv04_lvds_dpms()
537 LVDS_PANEL_ON, nv_encoder->mode.clock); in nv04_lvds_dpms()
542 call_lvds_script(dev, nv_encoder->dcb, head, in nv04_lvds_dpms()
550 nv04_dfp_prepare_sel_clk(dev, nv_encoder, nouveau_crtc(crtc)->index); in nv04_lvds_dpms()
552 dev_priv->mode_reg.sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK); in nv04_lvds_dpms()
553 dev_priv->mode_reg.sel_clk &= ~0xf0; in nv04_lvds_dpms()
555 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, dev_priv->mode_reg.sel_clk); in nv04_lvds_dpms()
560 struct drm_device *dev = encoder->dev; in nv04_tmds_dpms()
563 if (nv_encoder->last_dpms == mode) in nv04_tmds_dpms()
565 nv_encoder->last_dpms = mode; in nv04_tmds_dpms()
568 mode, nv_encoder->dcb->index); in nv04_tmds_dpms()
577 struct drm_device *dev = encoder->dev; in nv04_dfp_save()
580 nv_encoder->restore.head = in nv04_dfp_save()
581 nv04_dfp_get_bound_head(dev, nv_encoder->dcb); in nv04_dfp_save()
587 struct drm_device *dev = encoder->dev; in nv04_dfp_restore()
588 struct drm_nouveau_private *dev_priv = dev->dev_private; in nv04_dfp_restore()
589 int head = nv_encoder->restore.head; in nv04_dfp_restore()
591 if (nv_encoder->dcb->type == OUTPUT_LVDS) { in nv04_dfp_restore()
595 if (connector && connector->native_mode) in nv04_dfp_restore()
596 call_lvds_script(dev, nv_encoder->dcb, head, in nv04_dfp_restore()
598 connector->native_mode->clock); in nv04_dfp_restore()
600 } else if (nv_encoder->dcb->type == OUTPUT_TMDS) { in nv04_dfp_restore()
601 int clock = nouveau_hw_pllvals_to_clk in nv04_dfp_restore() local
602 (&dev_priv->saved_reg.crtc_reg[head].pllvals); in nv04_dfp_restore()
604 run_tmds_table(dev, nv_encoder->dcb, head, clock); in nv04_dfp_restore()
607 nv_encoder->last_dpms = NV_DPMS_CLEARED; in nv04_dfp_restore()
614 NV_DEBUG_KMS(encoder->dev, "\n"); in nv04_dfp_destroy()
617 get_slave_funcs(encoder)->destroy(encoder); in nv04_dfp_destroy()
625 struct drm_device *dev = encoder->dev; in nv04_tmds_slave_init()
626 struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb; in nv04_tmds_slave_init()
631 .addr = (dcb->tmdsconf.slave_addr == 0x7 ? 0x3a : 0x38), in nv04_tmds_slave_init()
649 &i2c->adapter, &info[type]); in nv04_tmds_slave_init()
686 switch (entry->type) { in nv04_dfp_create()
696 return -EINVAL; in nv04_dfp_create()
701 return -ENOMEM; in nv04_dfp_create()
705 nv_encoder->dcb = entry; in nv04_dfp_create()
706 nv_encoder->or = ffs(entry->or) - 1; in nv04_dfp_create()
708 drm_encoder_init(connector->dev, encoder, &nv04_dfp_funcs, type); in nv04_dfp_create()
711 encoder->possible_crtcs = entry->heads; in nv04_dfp_create()
712 encoder->possible_clones = 0; in nv04_dfp_create()
714 if (entry->type == OUTPUT_TMDS && in nv04_dfp_create()
715 entry->location != DCB_LOC_ON_CHIP) in nv04_dfp_create()