drm/i915/i915_reg.h

18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
28 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
32  * fb aperture size and the amount of pre-reserved memory.
33  * This is all handled in the intel-gtt.ko module. i915.ko only
179  * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
181  * - One can actually load arbitrary many arbitrary registers: Simply issue x
184 #define MI_LOAD_REGISTER_IMM(x)	MI_INSTR(0x22, 2*x-1)
245 #define GFX_OP_PIPE_CONTROL(len)	((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))
279 #define   I830_FENCE_SIZE_BITS(size)	((ffs((size) >> 19) - 1) << 8)
287 #define   I915_FENCE_SIZE_BITS(size)	((ffs((size) >> 20) - 1) << 8)
379 /* GM45+ chicken bits -- debug workaround bits that may be required
385 /* Disables pipelining of read flushes past the SF-WIZ interface.
386  * Required on all Ironlake steppings according to the B-Spec, but the
416 #define   I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT	(1<<14) /* p-state */
491 /* Enables non-sequential data reads through arbiter
500 /* Arbiter time slice for non-isoch streams */
638 /* The bit 28-8 is reserved */
688 #define GMBUS0			0x5100 /* clock/port select */
724 #define GMBUS3			0x510c /* data buffer bytes 3-0 */
735  * Clock control & power management
792 /* i830, required in DVO non-gang */
804 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x)	(((x)-1) << 9)
810  * Selects the phase for the 10X DPLL clock for the PCIe
836  * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
837  * clock rate is 10 times the DPLL clock.  At low resolution/refresh rate
839  * dummy bytes in the datastream at an increased clock rate, with both sides of
842  * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
843  * rate to 130Mhz to get a bus rate of 1.30Ghz.  The DPLL clock rate would be
847  * This register field has values of multiplication factor minus 1, with
899 # define TVRUNIT_CLOCK_GATE_DISABLE		(1 << 23) /* 915-945 */
900 # define TVCUNIT_CLOCK_GATE_DISABLE		(1 << 22) /* 915-945 */
901 # define TVFUNIT_CLOCK_GATE_DISABLE		(1 << 21) /* 915-945 */
902 # define TVEUNIT_CLOCK_GATE_DISABLE		(1 << 20) /* 915-945 */
903 # define DVSUNIT_CLOCK_GATE_DISABLE		(1 << 19) /* 915-945 */
904 # define DSSUNIT_CLOCK_GATE_DISABLE		(1 << 18) /* 915-945 */
905 # define DDBUNIT_CLOCK_GATE_DISABLE		(1 << 17) /* 915-945 */
906 # define DPRUNIT_CLOCK_GATE_DISABLE		(1 << 16) /* 915-945 */
907 # define DPFUNIT_CLOCK_GATE_DISABLE		(1 << 15) /* 915-945 */
908 # define DPBMUNIT_CLOCK_GATE_DISABLE		(1 << 14) /* 915-945 */
909 # define DPLSUNIT_CLOCK_GATE_DISABLE		(1 << 13) /* 915-945 */
910 # define DPLUNIT_CLOCK_GATE_DISABLE		(1 << 12) /* 915-945 */
916 # define OVHUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 830-865 */
917 # define DPIOUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 915-945 */
1023 /** 915-945 and GM965 MCH register controlling DRAM channel access */
1066 #define PXVFREQ_BASE		0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
1070 #define VIDFREQ1		0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */
1086 #define INTTOEXT_BASE		0x11120 /* INTTOEXT1-8 (0x1113c) */
1106 #define   MEMCTL_FREQ_MASK	0x0f00 /* jitter, from 0-15 */
1152 #define   MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
1162 #define   MEMMODE_FSTART_MASK	0x00000f00 /* starting jitter, 0-15 */
1164 #define   MEMMODE_FMAX_MASK	0x000000f0 /* max jitter, 0-15 */
1166 #define   MEMMODE_FMIN_MASK	0x0000000f /* min jitter, 0-15 */
1177 #define   SWFREQ_MASK		0x0380 /* P0-7 */
1193 #define   RCX_SW_EXIT		(1<<23) /* Leave RSx and prevent re-entry */
1205 #define   JRSC			(1<<17) /* rsx coupled to cpu c-state */
1219 #define   RCENTSYNC		(1<<9) /* rs coupled to cpu c-state (3/6/7) */
1245 #define   MCPPCE_EN		(1<<0) /* enable PM_MSG from PCH->MPC */
1264 #define   ECR_CAP_MASK		0x0000001f /* Event range, 0-31 */
1417  * Programmed value is multiplier - 1, up to 5x.
1485 /* Selects pipe B for LVDS data.  Must be set on pre-965. */
1495 /* Enable border for unscaled (or aspect-scaled) display */
1498  * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
1520  * Controls the B0-B3 data pairs.  This must be set to match the DPLL p2
1521  * setting for whether we are in dual-channel mode.  The B3 pair will
1551  * - PLL enabled
1552  * - pipe enabled
1553  * - LVDS/DVOB/DVOC on
1600 /* Pre-965 */
1665 /** Sets the colorburst to PAL mode.  Required for non-M PAL modes. */
1680 /** Read-only state that reports all features enabled */
1682 /** Read-only state that reports that Macrovision is disabled in hardware*/
1684 /** Read-only state that reports that TV-out is disabled in hardware. */
1688 /** Encoder test pattern 1 - combo pattern */
1690 /** Encoder test pattern 2 - full screen vertical 75% color bars */
1692 /** Encoder test pattern 3 - full screen horizontal 75% color bars */
1694 /** Encoder test pattern 4 - random noise */
1696 /** Encoder test pattern 5 - linear color ramps */
1722  * Enables DAC state detection logic, for load-based TV detection.
1753  * mantissa and 2 or 3 bits of exponent.  The exponent is represented as 2**-n,
1754  * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
1755  * -1 (0x3) being the only legal negative value.
1769  * Stored in 1.9 fixed point.
1786  * Stored in 1.9 fixed point.
1803  * Stored in 1.9 fixed point.
1809 /** 2s-complement brightness adjustment */
1839 /** Enables the colorburst (needed for non-component color) */
2038  * Sets the horizontal scaling factor.
2040  * This should be the fractional part of the horizontal scaling factor divided
2043  * (src width - 1) / ((oversample * dest width) - 1)
2050  * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2052  * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
2057  * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2066  * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2068  * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
2075  * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2128 /* Link training mode - select a suitable mode for each stage */
2152 /* Signal pre-emphasis levels, like voltages, the other end tells us what
2182 /** sends the clock on lane 15 of the PEG for debug */
2203  * is 20 bytes in each direction, hence the 5 fixed
2259  * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
2261  * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
2272 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
2290  * Attributes and VB-ID.
2350 #define   PIPE_HOTPLUG_TV_INTERRUPT_ENABLE	(1UL<<18) /* pre-965 */
2364 #define   PIPE_HOTPLUG_TV_INTERRUPT_STATUS	(1UL<<2) /* pre-965 */
2472 /* the unit of memory self-refresh latency time is 0.5us */
2869 #define  TU_SIZE(x)             (((x)-1) << 25) /* default size 64 */
3002 /* Required on all Ironlake and Sandybridge according to the B-Spec. */
3232 /* Per-transcoder DIP controls */
3306 #define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
3307 #define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
3338 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
3340 /* SNB A-stepping */
3345 /* SNB B-stepping */
3371 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
3439 #define  ADPA_CRT_HOTPLUG_MASK  0x03ff0000 /* bit 25-16 */
3593 /* SNB A-stepping */
3598 /* SNB B-stepping */
3626 #define  FORCEWAKE_MT				0xa188 /* multi-threaded */
3754 /* These are the 4 32-bit write offset registers for each stream