drm/gma500/psb_drv.h

283 struct drm_psb_private {  struct
284 	struct drm_device *dev;
285 	const struct psb_ops *ops;
287 	struct psb_gtt gtt;
290 	struct psb_gtt_mm *gtt_mm;
291 	struct page *scratch_page;
292 	u32 *gtt_map;
293 	uint32_t stolen_base;
294 	void *vram_addr;
295 	unsigned long vram_stolen_size;
296 	int gtt_initialized;
297 	u16 gmch_ctrl;		/* Saved GTT setup */
298 	u32 pge_ctl;
300 	struct mutex gtt_mutex;
301 	struct resource *gtt_mem;	/* Our PCI resource */
303 	struct psb_mmu_driver *mmu;
304 	struct psb_mmu_pd *pf_pd;
310 	uint8_t *sgx_reg;
311 	uint8_t *vdc_reg;
312 	uint32_t gatt_free_offset;
318 	uint32_t vdc_irq_mask;
319 	uint32_t pipestat[PSB_NUM_PIPE];
321 	spinlock_t irqmask_lock;
327 	bool suspended;
328 	bool display_power;
329 	int display_count;
334 	struct psb_intel_mode_device mode_dev;
336 	struct drm_crtc *plane_to_crtc_mapping[PSB_NUM_PIPE];
337 	struct drm_crtc *pipe_to_crtc_mapping[PSB_NUM_PIPE];
338 	uint32_t num_pipe;
343 	uint32_t ospm_base;
349 	u32 fuse_reg_value;
350 	u32 video_device_fuse;
353 	uint8_t platform_rev_id;
356 	struct intel_gmbus *gmbus;
359 	int crt_ddc_pin;
362 	struct sdvo_device_mapping sdvo_mappings[2];
363 	u32 hotplug_supported_mask;
364 	struct drm_property *broadcast_rgb_property;
365 	struct drm_property *force_audio_property;
370 	int backlight_duty_cycle;	/* restore backlight to this value */
371 	bool panel_wants_dither;
372 	struct drm_display_mode *panel_fixed_mode;
373 	struct drm_display_mode *lfp_lvds_vbt_mode;
374 	struct drm_display_mode *sdvo_lvds_vbt_mode;
376 	struct bdb_lvds_backlight *lvds_bl; /* LVDS backlight info from VBT */
377 	struct psb_intel_i2c_chan *lvds_i2c_bus; /* FIXME: Remove this? */
380 	unsigned int int_tv_support:1;
381 	unsigned int lvds_dither:1;
382 	unsigned int lvds_vbt:1;
383 	unsigned int int_crt_support:1;
384 	unsigned int lvds_use_ssc:1;
385 	int lvds_ssc_freq;
386 	bool is_lvds_on;
387 	bool is_mipi_on;
388 	u32 mipi_ctrl_display;
390 	unsigned int core_freq;
391 	uint32_t iLVDS_enable;
394 	int rpm_enabled;
397 	struct oaktrail_vbt vbt_data;
398 	struct oaktrail_gct_data gct_data;
401 	int panel_id;
402 	bool dual_mipi;		/* dual display - DPI & DBI */
403 	bool dpi_panel_on;	/* The DPI panel power is on */
404 	bool dpi_panel_on2;	/* The DPI panel power is on */
405 	bool dbi_panel_on;	/* The DBI panel power is on */
406 	bool dbi_panel_on2;	/* The DBI panel power is on */
407 	u32 dsr_fb_update;	/* DSR FB update counter */
410 	struct oaktrail_hdmi_dev *hdmi_priv;
413 	uint32_t pipeconf;
414 	uint32_t pipeconf1;
415 	uint32_t pipeconf2;
418 	uint32_t dspcntr;
419 	uint32_t dspcntr1;
420 	uint32_t dspcntr2;
423 	uint8_t saveBKLTCNT;
424 	uint8_t saveBKLTREQ;
425 	uint8_t saveBKLTBRTL;
430 	uint32_t saveDSPACNTR;
431 	uint32_t saveDSPBCNTR;
432 	uint32_t savePIPEACONF;
433 	uint32_t savePIPEBCONF;
434 	uint32_t savePIPEASRC;
435 	uint32_t savePIPEBSRC;
436 	uint32_t saveFPA0;
437 	uint32_t saveFPA1;
438 	uint32_t saveDPLL_A;
439 	uint32_t saveDPLL_A_MD;
440 	uint32_t saveHTOTAL_A;
441 	uint32_t saveHBLANK_A;
442 	uint32_t saveHSYNC_A;
443 	uint32_t saveVTOTAL_A;
444 	uint32_t saveVBLANK_A;
445 	uint32_t saveVSYNC_A;
446 	uint32_t saveDSPASTRIDE;
447 	uint32_t saveDSPASIZE;
448 	uint32_t saveDSPAPOS;
449 	uint32_t saveDSPABASE;
450 	uint32_t saveDSPASURF;
451 	uint32_t saveDSPASTATUS;
452 	uint32_t saveFPB0;
453 	uint32_t saveFPB1;
454 	uint32_t saveDPLL_B;
455 	uint32_t saveDPLL_B_MD;
456 	uint32_t saveHTOTAL_B;
457 	uint32_t saveHBLANK_B;
458 	uint32_t saveHSYNC_B;
459 	uint32_t saveVTOTAL_B;
460 	uint32_t saveVBLANK_B;
461 	uint32_t saveVSYNC_B;
462 	uint32_t saveDSPBSTRIDE;
463 	uint32_t saveDSPBSIZE;
464 	uint32_t saveDSPBPOS;
465 	uint32_t saveDSPBBASE;
466 	uint32_t saveDSPBSURF;
467 	uint32_t saveDSPBSTATUS;
468 	uint32_t saveVCLK_DIVISOR_VGA0;
469 	uint32_t saveVCLK_DIVISOR_VGA1;
470 	uint32_t saveVCLK_POST_DIV;
471 	uint32_t saveVGACNTRL;
472 	uint32_t saveADPA;
473 	uint32_t saveLVDS;
474 	uint32_t saveDVOA;
475 	uint32_t saveDVOB;
476 	uint32_t saveDVOC;
477 	uint32_t savePP_ON;
478 	uint32_t savePP_OFF;
479 	uint32_t savePP_CONTROL;
480 	uint32_t savePP_CYCLE;
481 	uint32_t savePFIT_CONTROL;
482 	uint32_t savePaletteA[256];
483 	uint32_t savePaletteB[256];
484 	uint32_t saveBLC_PWM_CTL2;
485 	uint32_t saveBLC_PWM_CTL;
486 	uint32_t saveCLOCKGATING;
487 	uint32_t saveDSPARB;
488 	uint32_t saveDSPATILEOFF;
489 	uint32_t saveDSPBTILEOFF;
490 	uint32_t saveDSPAADDR;
491 	uint32_t saveDSPBADDR;
492 	uint32_t savePFIT_AUTO_RATIOS;
493 	uint32_t savePFIT_PGM_RATIOS;
494 	uint32_t savePP_ON_DELAYS;
495 	uint32_t savePP_OFF_DELAYS;
496 	uint32_t savePP_DIVISOR;
497 	uint32_t saveBSM;
498 	uint32_t saveVBT;
499 	uint32_t saveBCLRPAT_A;
500 	uint32_t saveBCLRPAT_B;
501 	uint32_t saveDSPALINOFF;
502 	uint32_t saveDSPBLINOFF;
503 	uint32_t savePERF_MODE;
504 	uint32_t saveDSPFW1;
505 	uint32_t saveDSPFW2;
506 	uint32_t saveDSPFW3;
507 	uint32_t saveDSPFW4;
508 	uint32_t saveDSPFW5;
509 	uint32_t saveDSPFW6;
510 	uint32_t saveCHICKENBIT;
511 	uint32_t saveDSPACURSOR_CTRL;
512 	uint32_t saveDSPBCURSOR_CTRL;
513 	uint32_t saveDSPACURSOR_BASE;
514 	uint32_t saveDSPBCURSOR_BASE;
515 	uint32_t saveDSPACURSOR_POS;
516 	uint32_t saveDSPBCURSOR_POS;
517 	uint32_t save_palette_a[256];
518 	uint32_t save_palette_b[256];
519 	uint32_t saveOV_OVADD;
520 	uint32_t saveOV_OGAMC0;
521 	uint32_t saveOV_OGAMC1;
522 	uint32_t saveOV_OGAMC2;
523 	uint32_t saveOV_OGAMC3;
524 	uint32_t saveOV_OGAMC4;
525 	uint32_t saveOV_OGAMC5;
526 	uint32_t saveOVC_OVADD;
527 	uint32_t saveOVC_OGAMC0;
528 	uint32_t saveOVC_OGAMC1;
529 	uint32_t saveOVC_OGAMC2;
530 	uint32_t saveOVC_OGAMC3;
531 	uint32_t saveOVC_OGAMC4;
532 	uint32_t saveOVC_OGAMC5;
535 	uint32_t msi_addr;
536 	uint32_t msi_data;
539 	uint32_t saveHDMIPHYMISCCTL;
540 	uint32_t saveHDMIB_CONTROL;
541 	uint32_t saveDSPCCNTR;
542 	uint32_t savePIPECCONF;
543 	uint32_t savePIPECSRC;
544 	uint32_t saveHTOTAL_C;
545 	uint32_t saveHBLANK_C;
546 	uint32_t saveHSYNC_C;
547 	uint32_t saveVTOTAL_C;
548 	uint32_t saveVBLANK_C;
549 	uint32_t saveVSYNC_C;
550 	uint32_t saveDSPCSTRIDE;
551 	uint32_t saveDSPCSIZE;
552 	uint32_t saveDSPCPOS;
553 	uint32_t saveDSPCSURF;
554 	uint32_t saveDSPCSTATUS;
555 	uint32_t saveDSPCLINOFF;
556 	uint32_t saveDSPCTILEOFF;
557 	uint32_t saveDSPCCURSOR_CTRL;
558 	uint32_t saveDSPCCURSOR_BASE;
559 	uint32_t saveDSPCCURSOR_POS;
560 	uint32_t save_palette_c[256];
561 	uint32_t saveOV_OVADD_C;
562 	uint32_t saveOV_OGAMC0_C;
563 	uint32_t saveOV_OGAMC1_C;
564 	uint32_t saveOV_OGAMC2_C;
565 	uint32_t saveOV_OGAMC3_C;
566 	uint32_t saveOV_OGAMC4_C;
567 	uint32_t saveOV_OGAMC5_C;
570 	uint32_t saveDEVICE_READY_REG;
571 	uint32_t saveINTR_EN_REG;
572 	uint32_t saveDSI_FUNC_PRG_REG;
573 	uint32_t saveHS_TX_TIMEOUT_REG;
574 	uint32_t saveLP_RX_TIMEOUT_REG;
575 	uint32_t saveTURN_AROUND_TIMEOUT_REG;
576 	uint32_t saveDEVICE_RESET_REG;
577 	uint32_t saveDPI_RESOLUTION_REG;
578 	uint32_t saveHORIZ_SYNC_PAD_COUNT_REG;
579 	uint32_t saveHORIZ_BACK_PORCH_COUNT_REG;
580 	uint32_t saveHORIZ_FRONT_PORCH_COUNT_REG;
581 	uint32_t saveHORIZ_ACTIVE_AREA_COUNT_REG;
582 	uint32_t saveVERT_SYNC_PAD_COUNT_REG;
583 	uint32_t saveVERT_BACK_PORCH_COUNT_REG;
584 	uint32_t saveVERT_FRONT_PORCH_COUNT_REG;
585 	uint32_t saveHIGH_LOW_SWITCH_COUNT_REG;
586 	uint32_t saveINIT_COUNT_REG;
587 	uint32_t saveMAX_RET_PAK_REG;
588 	uint32_t saveVIDEO_FMT_REG;
589 	uint32_t saveEOT_DISABLE_REG;
590 	uint32_t saveLP_BYTECLK_REG;
591 	uint32_t saveHS_LS_DBI_ENABLE_REG;
592 	uint32_t saveTXCLKESC_REG;
593 	uint32_t saveDPHY_PARAM_REG;
594 	uint32_t saveMIPI_CONTROL_REG;
595 	uint32_t saveMIPI;
596 	uint32_t saveMIPI_C;
599 	uint32_t saveHISTOGRAM_INT_CONTROL_REG;
600 	uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG;
601 	uint32_t savePWM_CONTROL_LOGIC;
606 	void * dbi_dsr_info;
607 	void * dbi_dpu_info;
608 	void * dsi_configs[2];
612 	spinlock_t lid_lock;
613 	struct timer_list lid_timer;
614 	struct psb_intel_opregion opregion;
615 	u32 *lid_state;
616 	u32 lid_last_state;
622 	uint32_t apm_reg;
623 	uint16_t apm_base;
629 	struct backlight_device *backlight_device;
630 	struct drm_property *backlight_property;
631 	uint32_t blc_adj1;
632 	uint32_t blc_adj2;
634 	void *fbdev;
637 	spinlock_t lock_2d;