Lines Matching +full:fixed +full:- +full:factor +full:- +full:clock
2 * Copyright © 1997-2003 by The XFree86 Project, Inc.
4 * Copyright © 2007-2008 Intel Corporation
6 * Copyright 2005-2006 Luc Verhaegen
41 * drm_mode_debug_printmodeline - debug print a mode
54 mode->base.id, mode->name, mode->vrefresh, mode->clock, in drm_mode_debug_printmodeline()
55 mode->hdisplay, mode->hsync_start, in drm_mode_debug_printmodeline()
56 mode->hsync_end, mode->htotal, in drm_mode_debug_printmodeline()
57 mode->vdisplay, mode->vsync_start, in drm_mode_debug_printmodeline()
58 mode->vsync_end, mode->vtotal, mode->type, mode->flags); in drm_mode_debug_printmodeline()
63 * drm_cvt_mode -create a modeline based on CVT algorithm
90 /* 1) top/bottom margin size (% of height) - default: 1.8, */ in drm_cvt_mode()
92 /* 2) character cell horizontal granularity (pixels) - default 8 */ in drm_cvt_mode()
94 /* 3) Minimum vertical porch (lines) - default 3 */ in drm_cvt_mode()
96 /* 4) Minimum number of vertical back porch lines - default 6 */ in drm_cvt_mode()
98 /* Pixel Clock step (kHz) */ in drm_cvt_mode()
123 hdisplay_rnd = hdisplay - (hdisplay % CVT_H_GRANULARITY); in drm_cvt_mode()
129 hmargin -= hmargin % CVT_H_GRANULARITY; in drm_cvt_mode()
132 drm_mode->hdisplay = hdisplay_rnd + 2 * hmargin; in drm_cvt_mode()
145 drm_mode->vdisplay = vdisplay + 2 * vmargin; in drm_cvt_mode()
174 /* 3) Nominal HSync width (% of line period) - default 8 */ in drm_cvt_mode()
180 tmp1 = HV_FACTOR * 1000000 - in drm_cvt_mode()
193 vback_porch = vsyncandback_porch - vsync; in drm_cvt_mode()
194 drm_mode->vtotal = vdisplay_rnd + 2 * vmargin + in drm_cvt_mode()
197 /* Gradient (%/kHz) - default 600 */ in drm_cvt_mode()
199 /* Offset (%) - default 40 */ in drm_cvt_mode()
201 /* Blanking time scaling factor - default 128 */ in drm_cvt_mode()
203 /* Scaling factor weighting - default 20 */ in drm_cvt_mode()
206 #define CVT_C_PRIME ((CVT_C_FACTOR - CVT_J_FACTOR) * CVT_K_FACTOR / 256 + \ in drm_cvt_mode()
209 hblank_percentage = CVT_C_PRIME * HV_FACTOR - CVT_M_PRIME * in drm_cvt_mode()
214 hblank = drm_mode->hdisplay * hblank_percentage / in drm_cvt_mode()
215 (100 * HV_FACTOR - hblank_percentage); in drm_cvt_mode()
216 hblank -= hblank % (2 * CVT_H_GRANULARITY); in drm_cvt_mode()
218 drm_mode->htotal = drm_mode->hdisplay + hblank; in drm_cvt_mode()
219 drm_mode->hsync_end = drm_mode->hdisplay + hblank / 2; in drm_cvt_mode()
220 drm_mode->hsync_start = drm_mode->hsync_end - in drm_cvt_mode()
221 (drm_mode->htotal * CVT_HSYNC_PERCENTAGE) / 100; in drm_cvt_mode()
222 drm_mode->hsync_start += CVT_H_GRANULARITY - in drm_cvt_mode()
223 drm_mode->hsync_start % CVT_H_GRANULARITY; in drm_cvt_mode()
225 drm_mode->vsync_start = drm_mode->vdisplay + CVT_MIN_V_PORCH; in drm_cvt_mode()
226 drm_mode->vsync_end = drm_mode->vsync_start + vsync; in drm_cvt_mode()
229 /* Minimum vertical blanking interval time (µs)- default 460 */ in drm_cvt_mode()
231 /* Fixed number of clocks for horizontal sync */ in drm_cvt_mode()
233 /* Fixed number of clocks for horizontal blanking */ in drm_cvt_mode()
235 /* Fixed number of lines for vertical front porch - default 3*/ in drm_cvt_mode()
240 tmp1 = HV_FACTOR * 1000000 - in drm_cvt_mode()
250 drm_mode->vtotal = vdisplay_rnd + 2 * vmargin + vbilines; in drm_cvt_mode()
252 drm_mode->htotal = drm_mode->hdisplay + CVT_RB_H_BLANK; in drm_cvt_mode()
254 drm_mode->hsync_end = drm_mode->hdisplay + CVT_RB_H_BLANK / 2; in drm_cvt_mode()
255 drm_mode->hsync_start = drm_mode->hsync_end - CVT_RB_H_SYNC; in drm_cvt_mode()
257 drm_mode->vsync_start = drm_mode->vdisplay + CVT_RB_VFPORCH; in drm_cvt_mode()
258 drm_mode->vsync_end = drm_mode->vsync_start + vsync; in drm_cvt_mode()
260 /* 15/13. Find pixel clock frequency (kHz for xf86) */ in drm_cvt_mode()
261 drm_mode->clock = drm_mode->htotal * HV_FACTOR * 1000 / hperiod; in drm_cvt_mode()
262 drm_mode->clock -= drm_mode->clock % CVT_CLOCK_STEP; in drm_cvt_mode()
264 /* ignore - just set the mode flag for interlaced */ in drm_cvt_mode()
266 drm_mode->vtotal *= 2; in drm_cvt_mode()
267 drm_mode->flags |= DRM_MODE_FLAG_INTERLACE; in drm_cvt_mode()
272 drm_mode->flags |= (DRM_MODE_FLAG_PHSYNC | in drm_cvt_mode()
275 drm_mode->flags |= (DRM_MODE_FLAG_PVSYNC | in drm_cvt_mode()
283 * drm_gtf_mode_complex - create the modeline based on full GTF algorithm
305 { /* 1) top/bottom margin size (% of height) - default: 1.8, */ in drm_gtf_mode_complex()
307 /* 2) character cell horizontal granularity (pixels) - default 8 */ in drm_gtf_mode_complex()
309 /* 3) Minimum vertical porch (lines) - default 3 */ in drm_gtf_mode_complex()
318 #define GTF_C_PRIME ((((GTF_2C - GTF_2J) * GTF_K / 256) + GTF_2J) / 2) in drm_gtf_mode_complex()
377 tmp1 = (1000000 - MIN_VSYNC_PLUS_BP * vfieldrate_rqd) / 500; in drm_gtf_mode_complex()
388 vback_porch = vsync_plus_bp - V_SYNC_RQD; in drm_gtf_mode_complex()
416 ideal_duty_cycle = GTF_C_PRIME * 1000 - in drm_gtf_mode_complex()
421 (100000 - ideal_duty_cycle); in drm_gtf_mode_complex()
426 /* 21.Find pixel clock frequency: */ in drm_gtf_mode_complex()
437 hfront_porch = hblank / 2 - hsync; in drm_gtf_mode_complex()
442 drm_mode->hdisplay = hdisplay_rnd; in drm_gtf_mode_complex()
443 drm_mode->hsync_start = hdisplay_rnd + hfront_porch; in drm_gtf_mode_complex()
444 drm_mode->hsync_end = drm_mode->hsync_start + hsync; in drm_gtf_mode_complex()
445 drm_mode->htotal = total_pixels; in drm_gtf_mode_complex()
446 drm_mode->vdisplay = vdisplay_rnd; in drm_gtf_mode_complex()
447 drm_mode->vsync_start = vdisplay_rnd + vodd_front_porch_lines; in drm_gtf_mode_complex()
448 drm_mode->vsync_end = drm_mode->vsync_start + V_SYNC_RQD; in drm_gtf_mode_complex()
449 drm_mode->vtotal = vtotal_lines; in drm_gtf_mode_complex()
451 drm_mode->clock = pixel_freq; in drm_gtf_mode_complex()
454 drm_mode->vtotal *= 2; in drm_gtf_mode_complex()
455 drm_mode->flags |= DRM_MODE_FLAG_INTERLACE; in drm_gtf_mode_complex()
460 drm_mode->flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC; in drm_gtf_mode_complex()
462 drm_mode->flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC; in drm_gtf_mode_complex()
469 * drm_gtf_mode - create the modeline based on GTF algorithm
509 * drm_mode_set_name - set the name on a mode
519 bool interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); in drm_mode_set_name()
521 snprintf(mode->name, DRM_DISPLAY_MODE_LEN, "%dx%d%s", in drm_mode_set_name()
522 mode->hdisplay, mode->vdisplay, in drm_mode_set_name()
528 * drm_mode_list_concat - move modes from one list to another
549 * drm_mode_width - get the width of a mode
560 * @mode->hdisplay
564 return mode->hdisplay; in drm_mode_width()
570 * drm_mode_height - get the height of a mode
581 * @mode->vdisplay
585 return mode->vdisplay; in drm_mode_height()
589 /** drm_mode_hsync - get the hsync of a mode
601 if (mode->hsync) in drm_mode_hsync()
602 return mode->hsync; in drm_mode_hsync()
604 if (mode->htotal < 0) in drm_mode_hsync()
607 calc_val = (mode->clock * 1000) / mode->htotal; /* hsync in Hz */ in drm_mode_hsync()
616 * drm_mode_vrefresh - get the vrefresh of a mode
636 if (mode->vrefresh > 0) in drm_mode_vrefresh()
637 refresh = mode->vrefresh; in drm_mode_vrefresh()
638 else if (mode->htotal > 0 && mode->vtotal > 0) { in drm_mode_vrefresh()
640 vtotal = mode->vtotal; in drm_mode_vrefresh()
642 calc_val = (mode->clock * 1000); in drm_mode_vrefresh()
643 calc_val /= mode->htotal; in drm_mode_vrefresh()
646 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in drm_mode_vrefresh()
648 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) in drm_mode_vrefresh()
650 if (mode->vscan > 1) in drm_mode_vrefresh()
651 refresh /= mode->vscan; in drm_mode_vrefresh()
658 * drm_mode_set_crtcinfo - set CRTC modesetting parameters
669 if ((p == NULL) || ((p->type & DRM_MODE_TYPE_CRTC_C) == DRM_MODE_TYPE_BUILTIN)) in drm_mode_set_crtcinfo()
672 p->crtc_hdisplay = p->hdisplay; in drm_mode_set_crtcinfo()
673 p->crtc_hsync_start = p->hsync_start; in drm_mode_set_crtcinfo()
674 p->crtc_hsync_end = p->hsync_end; in drm_mode_set_crtcinfo()
675 p->crtc_htotal = p->htotal; in drm_mode_set_crtcinfo()
676 p->crtc_hskew = p->hskew; in drm_mode_set_crtcinfo()
677 p->crtc_vdisplay = p->vdisplay; in drm_mode_set_crtcinfo()
678 p->crtc_vsync_start = p->vsync_start; in drm_mode_set_crtcinfo()
679 p->crtc_vsync_end = p->vsync_end; in drm_mode_set_crtcinfo()
680 p->crtc_vtotal = p->vtotal; in drm_mode_set_crtcinfo()
682 if (p->flags & DRM_MODE_FLAG_INTERLACE) { in drm_mode_set_crtcinfo()
684 p->crtc_vdisplay /= 2; in drm_mode_set_crtcinfo()
685 p->crtc_vsync_start /= 2; in drm_mode_set_crtcinfo()
686 p->crtc_vsync_end /= 2; in drm_mode_set_crtcinfo()
687 p->crtc_vtotal /= 2; in drm_mode_set_crtcinfo()
690 p->crtc_vtotal |= 1; in drm_mode_set_crtcinfo()
693 if (p->flags & DRM_MODE_FLAG_DBLSCAN) { in drm_mode_set_crtcinfo()
694 p->crtc_vdisplay *= 2; in drm_mode_set_crtcinfo()
695 p->crtc_vsync_start *= 2; in drm_mode_set_crtcinfo()
696 p->crtc_vsync_end *= 2; in drm_mode_set_crtcinfo()
697 p->crtc_vtotal *= 2; in drm_mode_set_crtcinfo()
700 if (p->vscan > 1) { in drm_mode_set_crtcinfo()
701 p->crtc_vdisplay *= p->vscan; in drm_mode_set_crtcinfo()
702 p->crtc_vsync_start *= p->vscan; in drm_mode_set_crtcinfo()
703 p->crtc_vsync_end *= p->vscan; in drm_mode_set_crtcinfo()
704 p->crtc_vtotal *= p->vscan; in drm_mode_set_crtcinfo()
707 p->crtc_vblank_start = min(p->crtc_vsync_start, p->crtc_vdisplay); in drm_mode_set_crtcinfo()
708 p->crtc_vblank_end = max(p->crtc_vsync_end, p->crtc_vtotal); in drm_mode_set_crtcinfo()
709 p->crtc_hblank_start = min(p->crtc_hsync_start, p->crtc_hdisplay); in drm_mode_set_crtcinfo()
710 p->crtc_hblank_end = max(p->crtc_hsync_end, p->crtc_htotal); in drm_mode_set_crtcinfo()
712 p->crtc_hadjusted = false; in drm_mode_set_crtcinfo()
713 p->crtc_vadjusted = false; in drm_mode_set_crtcinfo()
719 * drm_mode_duplicate - allocate and duplicate an existing mode
738 new_id = nmode->base.id; in drm_mode_duplicate()
740 nmode->base.id = new_id; in drm_mode_duplicate()
741 INIT_LIST_HEAD(&nmode->head); in drm_mode_duplicate()
747 * drm_mode_equal - test modes for equality
761 /* do clock check convert to PICOS so fb modes get matched in drm_mode_equal()
763 if (mode1->clock && mode2->clock) { in drm_mode_equal()
764 if (KHZ2PICOS(mode1->clock) != KHZ2PICOS(mode2->clock)) in drm_mode_equal()
766 } else if (mode1->clock != mode2->clock) in drm_mode_equal()
769 if (mode1->hdisplay == mode2->hdisplay && in drm_mode_equal()
770 mode1->hsync_start == mode2->hsync_start && in drm_mode_equal()
771 mode1->hsync_end == mode2->hsync_end && in drm_mode_equal()
772 mode1->htotal == mode2->htotal && in drm_mode_equal()
773 mode1->hskew == mode2->hskew && in drm_mode_equal()
774 mode1->vdisplay == mode2->vdisplay && in drm_mode_equal()
775 mode1->vsync_start == mode2->vsync_start && in drm_mode_equal()
776 mode1->vsync_end == mode2->vsync_end && in drm_mode_equal()
777 mode1->vtotal == mode2->vtotal && in drm_mode_equal()
778 mode1->vscan == mode2->vscan && in drm_mode_equal()
779 mode1->flags == mode2->flags) in drm_mode_equal()
787 * drm_mode_validate_size - make sure modes adhere to size constraints
808 if (maxPitch > 0 && mode->hdisplay > maxPitch) in drm_mode_validate_size()
809 mode->status = MODE_BAD_WIDTH; in drm_mode_validate_size()
811 if (maxX > 0 && mode->hdisplay > maxX) in drm_mode_validate_size()
812 mode->status = MODE_VIRTUAL_X; in drm_mode_validate_size()
814 if (maxY > 0 && mode->vdisplay > maxY) in drm_mode_validate_size()
815 mode->status = MODE_VIRTUAL_Y; in drm_mode_validate_size()
821 * drm_mode_validate_clocks - validate modes against clock limits
824 * @min: minimum clock rate array
825 * @max: maximum clock rate array
826 * @n_ranges: number of clock ranges (size of arrays)
831 * Some code may need to check a mode list against the clock limits of the
834 * arrays) and sets @mode->status as needed.
846 if (mode->clock >= min[i] && mode->clock <= max[i]) { in drm_mode_validate_clocks()
852 mode->status = MODE_CLOCK_RANGE; in drm_mode_validate_clocks()
858 * drm_mode_prune_invalid - remove invalid modes from mode list
876 if (mode->status != MODE_OK) { in drm_mode_prune_invalid()
877 list_del(&mode->head); in drm_mode_prune_invalid()
881 mode->name, mode->status); in drm_mode_prune_invalid()
890 * drm_mode_compare - compare modes for favorability
911 diff = ((b->type & DRM_MODE_TYPE_PREFERRED) != 0) - in drm_mode_compare()
912 ((a->type & DRM_MODE_TYPE_PREFERRED) != 0); in drm_mode_compare()
915 diff = b->hdisplay * b->vdisplay - a->hdisplay * a->vdisplay; in drm_mode_compare()
918 diff = b->clock - a->clock; in drm_mode_compare()
923 * drm_mode_sort - sort mode list
938 * drm_mode_connector_list_update - update the mode list for the connector
955 list_for_each_entry_safe(pmode, pt, &connector->probed_modes, in drm_mode_connector_list_update()
959 list_for_each_entry(mode, &connector->modes, head) { in drm_mode_connector_list_update()
963 mode->status = pmode->status; in drm_mode_connector_list_update()
965 mode->type |= pmode->type; in drm_mode_connector_list_update()
966 list_del(&pmode->head); in drm_mode_connector_list_update()
967 drm_mode_destroy(connector->dev, pmode); in drm_mode_connector_list_update()
973 list_move_tail(&pmode->head, &connector->modes); in drm_mode_connector_list_update()
980 * drm_mode_parse_command_line_for_connector - parse command line for connector
981 * @mode_option - per connector mode option
982 * @connector - connector to parse line for
988 * <xres>x<yres>[M][R][-<bpp>][@<refresh>][i][m][eDd]
1011 mode->specified = false; in drm_mode_parse_command_line_for_connector()
1017 for (i = namelen-1; i >= 0; i--) { in drm_mode_parse_command_line_for_connector()
1028 case '-': in drm_mode_parse_command_line_for_connector()
1079 if ((connector->connector_type != DRM_MODE_CONNECTOR_DVII) && in drm_mode_parse_command_line_for_connector()
1080 (connector->connector_type != DRM_MODE_CONNECTOR_HDMIB)) in drm_mode_parse_command_line_for_connector()
1103 i = ch - name; in drm_mode_parse_command_line_for_connector()
1113 mode->specified = false; in drm_mode_parse_command_line_for_connector()
1118 mode->specified = true; in drm_mode_parse_command_line_for_connector()
1119 mode->xres = xres; in drm_mode_parse_command_line_for_connector()
1120 mode->yres = yres; in drm_mode_parse_command_line_for_connector()
1124 mode->refresh_specified = true; in drm_mode_parse_command_line_for_connector()
1125 mode->refresh = refresh; in drm_mode_parse_command_line_for_connector()
1129 mode->bpp_specified = true; in drm_mode_parse_command_line_for_connector()
1130 mode->bpp = bpp; in drm_mode_parse_command_line_for_connector()
1132 mode->rb = rb; in drm_mode_parse_command_line_for_connector()
1133 mode->cvt = cvt; in drm_mode_parse_command_line_for_connector()
1134 mode->interlace = interlace; in drm_mode_parse_command_line_for_connector()
1135 mode->margins = margins; in drm_mode_parse_command_line_for_connector()
1136 mode->force = force; in drm_mode_parse_command_line_for_connector()
1148 if (cmd->cvt) in drm_mode_create_from_cmdline_mode()
1150 cmd->xres, cmd->yres, in drm_mode_create_from_cmdline_mode()
1151 cmd->refresh_specified ? cmd->refresh : 60, in drm_mode_create_from_cmdline_mode()
1152 cmd->rb, cmd->interlace, in drm_mode_create_from_cmdline_mode()
1153 cmd->margins); in drm_mode_create_from_cmdline_mode()
1156 cmd->xres, cmd->yres, in drm_mode_create_from_cmdline_mode()
1157 cmd->refresh_specified ? cmd->refresh : 60, in drm_mode_create_from_cmdline_mode()
1158 cmd->interlace, in drm_mode_create_from_cmdline_mode()
1159 cmd->margins); in drm_mode_create_from_cmdline_mode()