Lines Matching +full:interrupt +full:- +full:map +full:- +full:mask
3 * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
18 #include <linux/interrupt.h>
26 /* see 80-VA736-2 Rev C pp 695-751
32 ** Since the _BASE need to be page-aligned when we're mapping them
46 #define MSM7X00_GPIO_OUT_0 MSM_GPIO1_SHADOW_REG(0x00) /* gpio 15-0 */
47 #define MSM7X00_GPIO_OUT_1 MSM_GPIO2_SHADOW_REG(0x00) /* gpio 42-16 */
48 #define MSM7X00_GPIO_OUT_2 MSM_GPIO1_SHADOW_REG(0x04) /* gpio 67-43 */
49 #define MSM7X00_GPIO_OUT_3 MSM_GPIO1_SHADOW_REG(0x08) /* gpio 94-68 */
50 #define MSM7X00_GPIO_OUT_4 MSM_GPIO1_SHADOW_REG(0x0C) /* gpio 106-95 */
51 #define MSM7X00_GPIO_OUT_5 MSM_GPIO1_SHADOW_REG(0x50) /* gpio 107-121 */
53 /* same pin map as above, output enable */
61 /* same pin map as above, input read */
69 /* same pin map as above, 1=edge 0=level interrup */
77 /* same pin map as above, 1=positive 0=negative */
85 /* same pin map as above, interrupt enable */
93 /* same pin map as above, write 1 to clear interrupt */
101 /* same pin map as above, 1=interrupt pending */
113 #define QSD8X50_GPIO_OUT_0 MSM_GPIO1_SHADOW_REG(0x00) /* gpio 15-0 */
114 #define QSD8X50_GPIO_OUT_1 MSM_GPIO2_SHADOW_REG(0x00) /* gpio 42-16 */
115 #define QSD8X50_GPIO_OUT_2 MSM_GPIO1_SHADOW_REG(0x04) /* gpio 67-43 */
116 #define QSD8X50_GPIO_OUT_3 MSM_GPIO1_SHADOW_REG(0x08) /* gpio 94-68 */
117 #define QSD8X50_GPIO_OUT_4 MSM_GPIO1_SHADOW_REG(0x0C) /* gpio 103-95 */
118 #define QSD8X50_GPIO_OUT_5 MSM_GPIO1_SHADOW_REG(0x10) /* gpio 121-104 */
119 #define QSD8X50_GPIO_OUT_6 MSM_GPIO1_SHADOW_REG(0x14) /* gpio 152-122 */
120 #define QSD8X50_GPIO_OUT_7 MSM_GPIO1_SHADOW_REG(0x18) /* gpio 164-153 */
122 /* same pin map as above, output enable */
132 /* same pin map as above, input read */
142 /* same pin map as above, 1=edge 0=level interrup */
152 /* same pin map as above, 1=positive 0=negative */
162 /* same pin map as above, interrupt enable */
172 /* same pin map as above, write 1 to clear interrupt */
182 /* same pin map as above, 1=interrupt pending */
196 #define MSM7X30_GPIO_OUT_0 MSM_GPIO1_REG(0x00) /* gpio 15-0 */
197 #define MSM7X30_GPIO_OUT_1 MSM_GPIO2_REG(0x00) /* gpio 43-16 */
198 #define MSM7X30_GPIO_OUT_2 MSM_GPIO1_REG(0x04) /* gpio 67-44 */
199 #define MSM7X30_GPIO_OUT_3 MSM_GPIO1_REG(0x08) /* gpio 94-68 */
200 #define MSM7X30_GPIO_OUT_4 MSM_GPIO1_REG(0x0C) /* gpio 106-95 */
201 #define MSM7X30_GPIO_OUT_5 MSM_GPIO1_REG(0x50) /* gpio 133-107 */
202 #define MSM7X30_GPIO_OUT_6 MSM_GPIO1_REG(0xC4) /* gpio 150-134 */
203 #define MSM7X30_GPIO_OUT_7 MSM_GPIO1_REG(0x214) /* gpio 181-151 */
205 /* same pin map as above, output enable */
215 /* same pin map as above, input read */
225 /* same pin map as above, 1=edge 0=level interrup */
235 /* same pin map as above, 1=positive 0=negative */
245 /* same pin map as above, interrupt enable */
255 /* same pin map as above, write 1 to clear interrupt */
265 /* same pin map as above, 1=interrupt pending */
291 .ngpio = (last) - (first) + 1, \
329 unsigned mask = BIT(offset); in msm_gpio_write() local
332 val = readl(msm_chip->regs.out); in msm_gpio_write()
334 writel(val | mask, msm_chip->regs.out); in msm_gpio_write()
336 writel(val & ~mask, msm_chip->regs.out); in msm_gpio_write()
345 val = readl(msm_chip->regs.in); in msm_gpio_update_both_edge_detect()
346 pol = readl(msm_chip->regs.int_pos); in msm_gpio_update_both_edge_detect()
347 pol = (pol & ~msm_chip->both_edge_detect) | in msm_gpio_update_both_edge_detect()
348 (~val & msm_chip->both_edge_detect); in msm_gpio_update_both_edge_detect()
349 writel(pol, msm_chip->regs.int_pos); in msm_gpio_update_both_edge_detect()
350 intstat = readl(msm_chip->regs.int_status); in msm_gpio_update_both_edge_detect()
351 val2 = readl(msm_chip->regs.in); in msm_gpio_update_both_edge_detect()
352 if (((val ^ val2) & msm_chip->both_edge_detect & ~intstat) == 0) in msm_gpio_update_both_edge_detect()
354 } while (loop_limit-- > 0); in msm_gpio_update_both_edge_detect()
366 /* Any interrupt that triggers between the read of int_status */ in msm_gpio_clear_detect_status()
368 msm_chip->int_status_copy |= readl(msm_chip->regs.int_status); in msm_gpio_clear_detect_status()
369 msm_chip->int_status_copy &= ~bit; in msm_gpio_clear_detect_status()
371 writel(bit, msm_chip->regs.int_clear); in msm_gpio_clear_detect_status()
382 spin_lock_irqsave(&msm_chip->lock, irq_flags); in msm_gpio_direction_input()
383 writel(readl(msm_chip->regs.oe) & ~BIT(offset), msm_chip->regs.oe); in msm_gpio_direction_input()
384 spin_unlock_irqrestore(&msm_chip->lock, irq_flags); in msm_gpio_direction_input()
395 spin_lock_irqsave(&msm_chip->lock, irq_flags); in msm_gpio_direction_output()
397 writel(readl(msm_chip->regs.oe) | BIT(offset), msm_chip->regs.oe); in msm_gpio_direction_output()
398 spin_unlock_irqrestore(&msm_chip->lock, irq_flags); in msm_gpio_direction_output()
407 return (readl(msm_chip->regs.in) & (1U << offset)) ? 1 : 0; in msm_gpio_get()
416 spin_lock_irqsave(&msm_chip->lock, irq_flags); in msm_gpio_set()
418 spin_unlock_irqrestore(&msm_chip->lock, irq_flags); in msm_gpio_set()
423 return MSM_GPIO_TO_INT(chip->base + offset); in msm_gpio_to_irq()
429 return msm_gpiomux_get(chip->base + offset); in msm_gpio_request()
434 msm_gpiomux_put(chip->base + offset); in msm_gpio_free()
479 spin_lock_irqsave(&msm_chip->lock, irq_flags); in msm_gpio_irq_ack()
481 d->irq - gpio_to_irq(msm_chip->chip.base)); in msm_gpio_irq_ack()
482 spin_unlock_irqrestore(&msm_chip->lock, irq_flags); in msm_gpio_irq_ack()
489 unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base); in msm_gpio_irq_mask()
491 spin_lock_irqsave(&msm_chip->lock, irq_flags); in msm_gpio_irq_mask()
493 if (!(readl(msm_chip->regs.int_edge) & BIT(offset))) in msm_gpio_irq_mask()
495 msm_chip->int_enable[0] &= ~BIT(offset); in msm_gpio_irq_mask()
496 writel(msm_chip->int_enable[0], msm_chip->regs.int_en); in msm_gpio_irq_mask()
497 spin_unlock_irqrestore(&msm_chip->lock, irq_flags); in msm_gpio_irq_mask()
504 unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base); in msm_gpio_irq_unmask()
506 spin_lock_irqsave(&msm_chip->lock, irq_flags); in msm_gpio_irq_unmask()
508 if (!(readl(msm_chip->regs.int_edge) & BIT(offset))) in msm_gpio_irq_unmask()
510 msm_chip->int_enable[0] |= BIT(offset); in msm_gpio_irq_unmask()
511 writel(msm_chip->int_enable[0], msm_chip->regs.int_en); in msm_gpio_irq_unmask()
512 spin_unlock_irqrestore(&msm_chip->lock, irq_flags); in msm_gpio_irq_unmask()
519 unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base); in msm_gpio_irq_set_wake()
521 spin_lock_irqsave(&msm_chip->lock, irq_flags); in msm_gpio_irq_set_wake()
524 msm_chip->int_enable[1] |= BIT(offset); in msm_gpio_irq_set_wake()
526 msm_chip->int_enable[1] &= ~BIT(offset); in msm_gpio_irq_set_wake()
528 spin_unlock_irqrestore(&msm_chip->lock, irq_flags); in msm_gpio_irq_set_wake()
536 unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base); in msm_gpio_irq_set_type()
537 unsigned val, mask = BIT(offset); in msm_gpio_irq_set_type() local
539 spin_lock_irqsave(&msm_chip->lock, irq_flags); in msm_gpio_irq_set_type()
540 val = readl(msm_chip->regs.int_edge); in msm_gpio_irq_set_type()
542 writel(val | mask, msm_chip->regs.int_edge); in msm_gpio_irq_set_type()
543 __irq_set_handler_locked(d->irq, handle_edge_irq); in msm_gpio_irq_set_type()
545 writel(val & ~mask, msm_chip->regs.int_edge); in msm_gpio_irq_set_type()
546 __irq_set_handler_locked(d->irq, handle_level_irq); in msm_gpio_irq_set_type()
549 msm_chip->both_edge_detect |= mask; in msm_gpio_irq_set_type()
552 msm_chip->both_edge_detect &= ~mask; in msm_gpio_irq_set_type()
553 val = readl(msm_chip->regs.int_pos); in msm_gpio_irq_set_type()
555 writel(val | mask, msm_chip->regs.int_pos); in msm_gpio_irq_set_type()
557 writel(val & ~mask, msm_chip->regs.int_pos); in msm_gpio_irq_set_type()
559 spin_unlock_irqrestore(&msm_chip->lock, irq_flags); in msm_gpio_irq_set_type()
565 int i, j, mask; in msm_gpio_irq_handler() local
570 val = readl(msm_chip->regs.int_status); in msm_gpio_irq_handler()
571 val &= msm_chip->int_enable[0]; in msm_gpio_irq_handler()
573 mask = val & -val; in msm_gpio_irq_handler()
574 j = fls(mask) - 1; in msm_gpio_irq_handler()
576 __func__, v, m, j, msm_chip->chip.start + j, in msm_gpio_irq_handler()
577 FIRST_GPIO_IRQ + msm_chip->chip.start + j); */ in msm_gpio_irq_handler()
578 val &= ~mask; in msm_gpio_irq_handler()
580 msm_chip->chip.base + j); in msm_gpio_irq_handler()
583 desc->irq_data.chip->irq_ack(&desc->irq_data); in msm_gpio_irq_handler()
613 if (i - FIRST_GPIO_IRQ >= in msm_init_gpio()