Lines Matching +full:chip +full:- +full:to +full:- +full:chip
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
60 * struct ioh_gpio_reg_data - The register store data.
61 * @ien_reg To store contents of interrupt enable register.
62 * @imask_reg: To store contents of interrupt mask regist
63 * @po_reg: To store contents of PO register.
64 * @pm_reg: To store contents of PM register.
65 * @im0_reg: To store contents of interrupt mode regist0
66 * @im1_reg: To store contents of interrupt mode regist1
67 * @use_sel_reg: To store contents of GPIO_USE_SEL0~3
80 * struct ioh_gpio - GPIO private data structure.
83 * @dev: Pointer to device structure.
111 struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio); in ioh_gpio_set() local
113 mutex_lock(&chip->lock); in ioh_gpio_set()
114 reg_val = ioread32(&chip->reg->regs[chip->ch].po); in ioh_gpio_set()
120 iowrite32(reg_val, &chip->reg->regs[chip->ch].po); in ioh_gpio_set()
121 mutex_unlock(&chip->lock); in ioh_gpio_set()
126 struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio); in ioh_gpio_get() local
128 return ioread32(&chip->reg->regs[chip->ch].pi) & (1 << nr); in ioh_gpio_get()
134 struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio); in ioh_gpio_direction_output() local
138 mutex_lock(&chip->lock); in ioh_gpio_direction_output()
139 pm = ioread32(&chip->reg->regs[chip->ch].pm) & in ioh_gpio_direction_output()
140 ((1 << num_ports[chip->ch]) - 1); in ioh_gpio_direction_output()
142 iowrite32(pm, &chip->reg->regs[chip->ch].pm); in ioh_gpio_direction_output()
144 reg_val = ioread32(&chip->reg->regs[chip->ch].po); in ioh_gpio_direction_output()
149 iowrite32(reg_val, &chip->reg->regs[chip->ch].po); in ioh_gpio_direction_output()
151 mutex_unlock(&chip->lock); in ioh_gpio_direction_output()
158 struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio); in ioh_gpio_direction_input() local
161 mutex_lock(&chip->lock); in ioh_gpio_direction_input()
162 pm = ioread32(&chip->reg->regs[chip->ch].pm) & in ioh_gpio_direction_input()
163 ((1 << num_ports[chip->ch]) - 1); in ioh_gpio_direction_input()
165 iowrite32(pm, &chip->reg->regs[chip->ch].pm); in ioh_gpio_direction_input()
166 mutex_unlock(&chip->lock); in ioh_gpio_direction_input()
175 static void ioh_gpio_save_reg_conf(struct ioh_gpio *chip) in ioh_gpio_save_reg_conf() argument
179 for (i = 0; i < 8; i ++, chip++) { in ioh_gpio_save_reg_conf()
180 chip->ioh_gpio_reg.po_reg = in ioh_gpio_save_reg_conf()
181 ioread32(&chip->reg->regs[chip->ch].po); in ioh_gpio_save_reg_conf()
182 chip->ioh_gpio_reg.pm_reg = in ioh_gpio_save_reg_conf()
183 ioread32(&chip->reg->regs[chip->ch].pm); in ioh_gpio_save_reg_conf()
184 chip->ioh_gpio_reg.ien_reg = in ioh_gpio_save_reg_conf()
185 ioread32(&chip->reg->regs[chip->ch].ien); in ioh_gpio_save_reg_conf()
186 chip->ioh_gpio_reg.imask_reg = in ioh_gpio_save_reg_conf()
187 ioread32(&chip->reg->regs[chip->ch].imask); in ioh_gpio_save_reg_conf()
188 chip->ioh_gpio_reg.im0_reg = in ioh_gpio_save_reg_conf()
189 ioread32(&chip->reg->regs[chip->ch].im_0); in ioh_gpio_save_reg_conf()
190 chip->ioh_gpio_reg.im1_reg = in ioh_gpio_save_reg_conf()
191 ioread32(&chip->reg->regs[chip->ch].im_1); in ioh_gpio_save_reg_conf()
193 chip->ioh_gpio_reg.use_sel_reg = in ioh_gpio_save_reg_conf()
194 ioread32(&chip->reg->ioh_sel_reg[i]); in ioh_gpio_save_reg_conf()
201 static void ioh_gpio_restore_reg_conf(struct ioh_gpio *chip) in ioh_gpio_restore_reg_conf() argument
205 for (i = 0; i < 8; i ++, chip++) { in ioh_gpio_restore_reg_conf()
206 iowrite32(chip->ioh_gpio_reg.po_reg, in ioh_gpio_restore_reg_conf()
207 &chip->reg->regs[chip->ch].po); in ioh_gpio_restore_reg_conf()
208 iowrite32(chip->ioh_gpio_reg.pm_reg, in ioh_gpio_restore_reg_conf()
209 &chip->reg->regs[chip->ch].pm); in ioh_gpio_restore_reg_conf()
210 iowrite32(chip->ioh_gpio_reg.ien_reg, in ioh_gpio_restore_reg_conf()
211 &chip->reg->regs[chip->ch].ien); in ioh_gpio_restore_reg_conf()
212 iowrite32(chip->ioh_gpio_reg.imask_reg, in ioh_gpio_restore_reg_conf()
213 &chip->reg->regs[chip->ch].imask); in ioh_gpio_restore_reg_conf()
214 iowrite32(chip->ioh_gpio_reg.im0_reg, in ioh_gpio_restore_reg_conf()
215 &chip->reg->regs[chip->ch].im_0); in ioh_gpio_restore_reg_conf()
216 iowrite32(chip->ioh_gpio_reg.im1_reg, in ioh_gpio_restore_reg_conf()
217 &chip->reg->regs[chip->ch].im_1); in ioh_gpio_restore_reg_conf()
219 iowrite32(chip->ioh_gpio_reg.use_sel_reg, in ioh_gpio_restore_reg_conf()
220 &chip->reg->ioh_sel_reg[i]); in ioh_gpio_restore_reg_conf()
227 struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio); in ioh_gpio_to_irq() local
228 return chip->irq_base + offset; in ioh_gpio_to_irq()
231 static void ioh_gpio_setup(struct ioh_gpio *chip, int num_port) in ioh_gpio_setup() argument
233 struct gpio_chip *gpio = &chip->gpio; in ioh_gpio_setup()
235 gpio->label = dev_name(chip->dev); in ioh_gpio_setup()
236 gpio->owner = THIS_MODULE; in ioh_gpio_setup()
237 gpio->direction_input = ioh_gpio_direction_input; in ioh_gpio_setup()
238 gpio->get = ioh_gpio_get; in ioh_gpio_setup()
239 gpio->direction_output = ioh_gpio_direction_output; in ioh_gpio_setup()
240 gpio->set = ioh_gpio_set; in ioh_gpio_setup()
241 gpio->dbg_show = NULL; in ioh_gpio_setup()
242 gpio->base = -1; in ioh_gpio_setup()
243 gpio->ngpio = num_port; in ioh_gpio_setup()
244 gpio->can_sleep = 0; in ioh_gpio_setup()
245 gpio->to_irq = ioh_gpio_to_irq; in ioh_gpio_setup()
257 int irq = d->irq; in ioh_irq_type()
259 struct ioh_gpio *chip = gc->private; in ioh_irq_type() local
261 ch = irq - chip->irq_base; in ioh_irq_type()
262 if (irq <= chip->irq_base + 7) { in ioh_irq_type()
263 im_reg = &chip->reg->regs[chip->ch].im_0; in ioh_irq_type()
266 im_reg = &chip->reg->regs[chip->ch].im_1; in ioh_irq_type()
267 im_pos = ch - 8; in ioh_irq_type()
269 dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d type=%d\n", in ioh_irq_type()
272 spin_lock_irqsave(&chip->spinlock, flags); in ioh_irq_type()
293 dev_warn(chip->dev, "%s: unknown type(%dd)", in ioh_irq_type()
303 iowrite32(BIT(ch), &chip->reg->regs[chip->ch].iclr); in ioh_irq_type()
306 iowrite32(BIT(ch), &chip->reg->regs[chip->ch].imaskclr); in ioh_irq_type()
309 ien = ioread32(&chip->reg->regs[chip->ch].ien); in ioh_irq_type()
310 iowrite32(ien | BIT(ch), &chip->reg->regs[chip->ch].ien); in ioh_irq_type()
312 spin_unlock_irqrestore(&chip->spinlock, flags); in ioh_irq_type()
320 struct ioh_gpio *chip = gc->private; in ioh_irq_unmask() local
322 iowrite32(1 << (d->irq - chip->irq_base), in ioh_irq_unmask()
323 &chip->reg->regs[chip->ch].imaskclr); in ioh_irq_unmask()
329 struct ioh_gpio *chip = gc->private; in ioh_irq_mask() local
331 iowrite32(1 << (d->irq - chip->irq_base), in ioh_irq_mask()
332 &chip->reg->regs[chip->ch].imask); in ioh_irq_mask()
338 struct ioh_gpio *chip = gc->private; in ioh_irq_disable() local
342 spin_lock_irqsave(&chip->spinlock, flags); in ioh_irq_disable()
343 ien = ioread32(&chip->reg->regs[chip->ch].ien); in ioh_irq_disable()
344 ien &= ~(1 << (d->irq - chip->irq_base)); in ioh_irq_disable()
345 iowrite32(ien, &chip->reg->regs[chip->ch].ien); in ioh_irq_disable()
346 spin_unlock_irqrestore(&chip->spinlock, flags); in ioh_irq_disable()
352 struct ioh_gpio *chip = gc->private; in ioh_irq_enable() local
356 spin_lock_irqsave(&chip->spinlock, flags); in ioh_irq_enable()
357 ien = ioread32(&chip->reg->regs[chip->ch].ien); in ioh_irq_enable()
358 ien |= 1 << (d->irq - chip->irq_base); in ioh_irq_enable()
359 iowrite32(ien, &chip->reg->regs[chip->ch].ien); in ioh_irq_enable()
360 spin_unlock_irqrestore(&chip->spinlock, flags); in ioh_irq_enable()
365 struct ioh_gpio *chip = dev_id; in ioh_gpio_handler() local
370 for (i = 0; i < 8; i++, chip++) { in ioh_gpio_handler()
371 reg_val = ioread32(&chip->reg->regs[i].istatus); in ioh_gpio_handler()
374 dev_dbg(chip->dev, in ioh_gpio_handler()
378 &chip->reg->regs[chip->ch].iclr); in ioh_gpio_handler()
379 generic_handle_irq(chip->irq_base + j); in ioh_gpio_handler()
387 static __devinit void ioh_gpio_alloc_generic_chip(struct ioh_gpio *chip, in ioh_gpio_alloc_generic_chip() argument
393 gc = irq_alloc_generic_chip("ioh_gpio", 1, irq_start, chip->base, in ioh_gpio_alloc_generic_chip()
395 gc->private = chip; in ioh_gpio_alloc_generic_chip()
396 ct = gc->chip_types; in ioh_gpio_alloc_generic_chip()
398 ct->chip.irq_mask = ioh_irq_mask; in ioh_gpio_alloc_generic_chip()
399 ct->chip.irq_unmask = ioh_irq_unmask; in ioh_gpio_alloc_generic_chip()
400 ct->chip.irq_set_type = ioh_irq_type; in ioh_gpio_alloc_generic_chip()
401 ct->chip.irq_disable = ioh_irq_disable; in ioh_gpio_alloc_generic_chip()
402 ct->chip.irq_enable = ioh_irq_enable; in ioh_gpio_alloc_generic_chip()
413 struct ioh_gpio *chip; in ioh_gpio_probe() local
420 dev_err(&pdev->dev, "%s : pci_enable_device failed", __func__); in ioh_gpio_probe()
426 dev_err(&pdev->dev, "pci_request_regions failed-%d", ret); in ioh_gpio_probe()
432 dev_err(&pdev->dev, "%s : pci_iomap failed", __func__); in ioh_gpio_probe()
433 ret = -ENOMEM; in ioh_gpio_probe()
437 chip_save = kzalloc(sizeof(*chip) * 8, GFP_KERNEL); in ioh_gpio_probe()
439 dev_err(&pdev->dev, "%s : kzalloc failed", __func__); in ioh_gpio_probe()
440 ret = -ENOMEM; in ioh_gpio_probe()
444 chip = chip_save; in ioh_gpio_probe()
445 for (i = 0; i < 8; i++, chip++) { in ioh_gpio_probe()
446 chip->dev = &pdev->dev; in ioh_gpio_probe()
447 chip->base = base; in ioh_gpio_probe()
448 chip->reg = chip->base; in ioh_gpio_probe()
449 chip->ch = i; in ioh_gpio_probe()
450 mutex_init(&chip->lock); in ioh_gpio_probe()
451 spin_lock_init(&chip->spinlock); in ioh_gpio_probe()
452 ioh_gpio_setup(chip, num_ports[i]); in ioh_gpio_probe()
453 ret = gpiochip_add(&chip->gpio); in ioh_gpio_probe()
455 dev_err(&pdev->dev, "IOH gpio: Failed to register GPIO\n"); in ioh_gpio_probe()
460 chip = chip_save; in ioh_gpio_probe()
461 for (j = 0; j < 8; j++, chip++) { in ioh_gpio_probe()
462 irq_base = irq_alloc_descs(-1, IOH_IRQ_BASE, num_ports[j], in ioh_gpio_probe()
465 dev_warn(&pdev->dev, in ioh_gpio_probe()
466 "ml_ioh_gpio: Failed to get IRQ base num\n"); in ioh_gpio_probe()
467 chip->irq_base = -1; in ioh_gpio_probe()
470 chip->irq_base = irq_base; in ioh_gpio_probe()
471 ioh_gpio_alloc_generic_chip(chip, irq_base, num_ports[j]); in ioh_gpio_probe()
474 chip = chip_save; in ioh_gpio_probe()
475 ret = request_irq(pdev->irq, ioh_gpio_handler, in ioh_gpio_probe()
476 IRQF_SHARED, KBUILD_MODNAME, chip); in ioh_gpio_probe()
478 dev_err(&pdev->dev, in ioh_gpio_probe()
483 pci_set_drvdata(pdev, chip); in ioh_gpio_probe()
488 chip = chip_save; in ioh_gpio_probe()
490 while (--j >= 0) { in ioh_gpio_probe()
491 chip--; in ioh_gpio_probe()
492 irq_free_descs(chip->irq_base, num_ports[j]); in ioh_gpio_probe()
495 chip = chip_save; in ioh_gpio_probe()
497 while (--i >= 0) { in ioh_gpio_probe()
498 chip--; in ioh_gpio_probe()
499 ret = gpiochip_remove(&chip->gpio); in ioh_gpio_probe()
501 dev_err(&pdev->dev, "Failed gpiochip_remove(%d)\n", i); in ioh_gpio_probe()
516 dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret); in ioh_gpio_probe()
524 struct ioh_gpio *chip = pci_get_drvdata(pdev); in ioh_gpio_remove() local
527 chip_save = chip; in ioh_gpio_remove()
529 free_irq(pdev->irq, chip); in ioh_gpio_remove()
531 for (i = 0; i < 8; i++, chip++) { in ioh_gpio_remove()
532 irq_free_descs(chip->irq_base, num_ports[i]); in ioh_gpio_remove()
533 err = gpiochip_remove(&chip->gpio); in ioh_gpio_remove()
535 dev_err(&pdev->dev, "Failed gpiochip_remove\n"); in ioh_gpio_remove()
538 chip = chip_save; in ioh_gpio_remove()
539 pci_iounmap(pdev, chip->base); in ioh_gpio_remove()
542 kfree(chip); in ioh_gpio_remove()
549 struct ioh_gpio *chip = pci_get_drvdata(pdev); in ioh_gpio_suspend() local
552 spin_lock_irqsave(&chip->spinlock, flags); in ioh_gpio_suspend()
553 ioh_gpio_save_reg_conf(chip); in ioh_gpio_suspend()
554 spin_unlock_irqrestore(&chip->spinlock, flags); in ioh_gpio_suspend()
558 dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret); in ioh_gpio_suspend()
565 dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret); in ioh_gpio_suspend()
573 struct ioh_gpio *chip = pci_get_drvdata(pdev); in ioh_gpio_resume() local
581 dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret); in ioh_gpio_resume()
586 spin_lock_irqsave(&chip->spinlock, flags); in ioh_gpio_resume()
587 iowrite32(0x01, &chip->reg->srst); in ioh_gpio_resume()
588 iowrite32(0x00, &chip->reg->srst); in ioh_gpio_resume()
589 ioh_gpio_restore_reg_conf(chip); in ioh_gpio_resume()
590 spin_unlock_irqrestore(&chip->spinlock, flags); in ioh_gpio_resume()
626 MODULE_DESCRIPTION("OKI SEMICONDUCTOR ML-IOH series GPIO Driver");