Lines Matching +full:gpio +full:- +full:mux +full:- +full:clock
2 * TI DaVinci GPIO Support
4 * Copyright (c) 2006-2007 David Brownell
12 #include <linux/gpio.h>
40 static struct davinci_gpio_regs __iomem __init *gpio2regs(unsigned gpio) in gpio2regs() argument
44 if (gpio < 32 * 1) in gpio2regs()
46 else if (gpio < 32 * 2) in gpio2regs()
48 else if (gpio < 32 * 3) in gpio2regs()
50 else if (gpio < 32 * 4) in gpio2regs()
52 else if (gpio < 32 * 5) in gpio2regs()
70 /*--------------------------------------------------------------------------*/
72 /* board setup code *MUST* setup pinmux and enable the GPIO clock. */
77 struct davinci_gpio_regs __iomem *g = d->regs; in __davinci_direction()
82 spin_lock_irqsave(&d->lock, flags); in __davinci_direction()
83 temp = __raw_readl(&g->dir); in __davinci_direction()
86 __raw_writel(mask, value ? &g->set_data : &g->clr_data); in __davinci_direction()
90 __raw_writel(temp, &g->dir); in __davinci_direction()
91 spin_unlock_irqrestore(&d->lock, flags); in __davinci_direction()
111 * Note that changes are synched to the GPIO clock, so reading values back
117 struct davinci_gpio_regs __iomem *g = d->regs; in davinci_gpio_get()
119 return (1 << offset) & __raw_readl(&g->in_data); in davinci_gpio_get()
123 * Assuming the pin is muxed as a gpio output, set its output value.
129 struct davinci_gpio_regs __iomem *g = d->regs; in davinci_gpio_set()
131 __raw_writel((1 << offset), value ? &g->set_data : &g->clr_data); in davinci_gpio_set()
141 if (soc_info->gpio_type != GPIO_TYPE_DAVINCI) in davinci_gpio_setup()
145 * The gpio banks conceptually expose a segmented bitmap, in davinci_gpio_setup()
146 * and "ngpio" is one more than the largest zero-based in davinci_gpio_setup()
149 ngpio = soc_info->gpio_num; in davinci_gpio_setup()
151 pr_err("GPIO setup: how many GPIOs?\n"); in davinci_gpio_setup()
152 return -EINVAL; in davinci_gpio_setup()
158 gpio_base = ioremap(soc_info->gpio_base, SZ_4K); in davinci_gpio_setup()
160 return -ENOMEM; in davinci_gpio_setup()
171 chips[i].chip.ngpio = ngpio - base; in davinci_gpio_setup()
179 chips[i].set_data = ®s->set_data; in davinci_gpio_setup()
180 chips[i].clr_data = ®s->clr_data; in davinci_gpio_setup()
181 chips[i].in_data = ®s->in_data; in davinci_gpio_setup()
186 soc_info->gpio_ctlrs = chips; in davinci_gpio_setup()
187 soc_info->gpio_ctlrs_num = DIV_ROUND_UP(ngpio, 32); in davinci_gpio_setup()
194 /*--------------------------------------------------------------------------*/
208 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); in gpio_irq_disable()
211 __raw_writel(mask, &g->clr_falling); in gpio_irq_disable()
212 __raw_writel(mask, &g->clr_rising); in gpio_irq_disable()
217 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); in gpio_irq_enable()
226 __raw_writel(mask, &g->set_falling); in gpio_irq_enable()
228 __raw_writel(mask, &g->set_rising); in gpio_irq_enable()
234 return -EINVAL; in gpio_irq_type()
240 .name = "GPIO",
255 g = (struct davinci_gpio_regs __iomem *)d->regs; in gpio_irq_handler()
262 desc->irq_data.chip->irq_mask(&desc->irq_data); in gpio_irq_handler()
263 desc->irq_data.chip->irq_ack(&desc->irq_data); in gpio_irq_handler()
270 status = __raw_readl(&g->intstat) & mask; in gpio_irq_handler()
273 __raw_writel(status, &g->intstat); in gpio_irq_handler()
276 n = d->irq_base; in gpio_irq_handler()
285 generic_handle_irq(n - 1); in gpio_irq_handler()
289 desc->irq_data.chip->irq_unmask(&desc->irq_data); in gpio_irq_handler()
290 /* now it may re-trigger */ in gpio_irq_handler()
297 if (d->irq_base >= 0) in gpio_to_irq_banked()
298 return d->irq_base + offset; in gpio_to_irq_banked()
300 return -ENODEV; in gpio_to_irq_banked()
308 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs). in gpio_to_irq_unbanked()
310 if (offset < soc_info->gpio_unbanked) in gpio_to_irq_unbanked()
311 return soc_info->gpio_irq + offset; in gpio_to_irq_unbanked()
313 return -ENODEV; in gpio_to_irq_unbanked()
318 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); in gpio_irq_type_unbanked()
322 return -EINVAL; in gpio_irq_type_unbanked()
325 ? &g->set_falling : &g->clr_falling); in gpio_irq_type_unbanked()
327 ? &g->set_rising : &g->clr_rising); in gpio_irq_type_unbanked()
335 * calls ... so if no gpios are wakeup events the clock can be disabled,
342 unsigned gpio, irq, bank; in davinci_gpio_irq_setup() local
349 ngpio = soc_info->gpio_num; in davinci_gpio_irq_setup()
351 bank_irq = soc_info->gpio_irq; in davinci_gpio_irq_setup()
353 printk(KERN_ERR "Don't know first GPIO bank IRQ.\n"); in davinci_gpio_irq_setup()
354 return -EINVAL; in davinci_gpio_irq_setup()
357 clk = clk_get(NULL, "gpio"); in davinci_gpio_irq_setup()
359 printk(KERN_ERR "Error %ld getting gpio clock?\n", in davinci_gpio_irq_setup()
366 * banked IRQs. Having GPIOs in the first GPIO bank use direct in davinci_gpio_irq_setup()
370 for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) { in davinci_gpio_irq_setup()
372 chips[bank].irq_base = soc_info->gpio_unbanked in davinci_gpio_irq_setup()
373 ? -EINVAL in davinci_gpio_irq_setup()
374 : (soc_info->intc_irq_num + gpio); in davinci_gpio_irq_setup()
378 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO in davinci_gpio_irq_setup()
380 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs. in davinci_gpio_irq_setup()
382 if (soc_info->gpio_unbanked) { in davinci_gpio_irq_setup()
385 /* pass "bank 0" GPIO IRQs to AINTC */ in davinci_gpio_irq_setup()
389 /* AINTC handles mask/unmask; GPIO handles triggering */ in davinci_gpio_irq_setup()
392 gpio_irqchip_unbanked.name = "GPIO-AINTC"; in davinci_gpio_irq_setup()
397 __raw_writel(~0, &g->set_falling); in davinci_gpio_irq_setup()
398 __raw_writel(~0, &g->set_rising); in davinci_gpio_irq_setup()
401 for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) { in davinci_gpio_irq_setup()
403 irq_set_handler_data(irq, (void *)__gpio_mask(gpio)); in davinci_gpio_irq_setup()
412 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we in davinci_gpio_irq_setup()
415 for (gpio = 0, irq = gpio_to_irq(0), bank = 0; in davinci_gpio_irq_setup()
416 gpio < ngpio; in davinci_gpio_irq_setup()
421 g = gpio2regs(gpio); in davinci_gpio_irq_setup()
422 __raw_writel(~0, &g->clr_falling); in davinci_gpio_irq_setup()
423 __raw_writel(~0, &g->clr_rising); in davinci_gpio_irq_setup()
430 * gpio irqs. Pass the irq bank's corresponding controller to in davinci_gpio_irq_setup()
433 irq_set_handler_data(bank_irq, &chips[gpio / 32]); in davinci_gpio_irq_setup()
435 for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) { in davinci_gpio_irq_setup()
438 irq_set_handler_data(irq, (void *)__gpio_mask(gpio)); in davinci_gpio_irq_setup()
447 /* BINTEN -- per-bank interrupt enable. genirq would also let these in davinci_gpio_irq_setup()
452 printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0)); in davinci_gpio_irq_setup()