drivers/edac/amd64_edac.h

13  *		- K8 CPU Revision D and greater support
16  *		- Module largely rewritten, with new (and hopefully correct)
19  *		- Added support for memory hoisting using DRAM hole address
23  *		-K8 Rev (1207) revision support added, required Revision
24  *		specific mini-driver code to support Rev F as well as
28  *		-Family 10h revision support added. New PCI Device IDs,
37  *		- misc fixes and code cleanups
60  * The Family 10h BKDG was totally re-written from scratch with a new
107  *         This is a physical address generated by a CPU core or a device
108  *         doing DMA.  If generated by a CPU core, a SysAddr is the result of
109  *         a virtual to physical address translation by the CPU core's address
168 #define GENMASK(lo, hi)			(((1ULL << ((hi) - (lo) + 1)) - 1) << (lo))
171  * PCI-defined configuration space registers
178  * Function 1 - Address Map
183 #define dram_intlv_en(pvt, i)		((u8)((pvt->ranges[i].base.lo >> 8) & 0x7))
184 #define dram_rw(pvt, i)			((u8)(pvt->ranges[i].base.lo & 0x3))
185 #define dram_intlv_sel(pvt, i)		((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7))
186 #define dram_dst_node(pvt, i)		((u8)(pvt->ranges[i].lim.lo & 0x7))
189 #define dhar_valid(pvt)			((pvt)->dhar & BIT(0))
190 #define dhar_mem_hoist_valid(pvt)	((pvt)->dhar & BIT(1))
191 #define dhar_base(pvt)			((pvt)->dhar & 0xff000000)
192 #define k8_dhar_offset(pvt)		(((pvt)->dhar & 0x0000ff00) << 16)
195 #define f10_dhar_offset(pvt)		(((pvt)->dhar & 0x0000ff80) << 16)
207  * Function 2 - DRAM controller
216 #define csrow_enabled(i, dct, pvt)	((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE)
236 #define dct_sel_baseaddr(pvt)		((pvt)->dct_sel_lo & 0xFFFFF800)
237 #define dct_sel_interleave_addr(pvt)	(((pvt)->dct_sel_lo >> 6) & 0x3)
238 #define dct_high_range_enabled(pvt)	((pvt)->dct_sel_lo & BIT(0))
239 #define dct_interleave_enabled(pvt)	((pvt)->dct_sel_lo & BIT(2))
241 #define dct_ganging_enabled(pvt)	((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4)))
243 #define dct_data_intlv_enabled(pvt)	((pvt)->dct_sel_lo & BIT(5))
244 #define dct_memory_cleared(pvt)		((pvt)->dct_sel_lo & BIT(10))
251  * Function 3 - Misc Control
266 #define online_spare_swap_done(pvt, c)	(((pvt)->online_spare >> (1 + 2 * (c))) & 0x1)
267 #define online_spare_bad_dramcs(pvt, c)	(((pvt)->online_spare >> (4 + 4 * (c))) & 0x7)
272 /* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline  */
296 	return PCI_SLOT(pdev->devfn) - 0x18;  in get_node_id()
368 	u32 online_spare;	/* On-Line spare Reg */
379 	u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8;  in get_dram_base()
384 	return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr;  in get_dram_base()
389 	u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) | 0x00ffffff;  in get_dram_limit()
394 	return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) | lim;  in get_dram_limit()
403  * per-node ECC settings descriptor
459 	pvt->ops->read_dct_pci_cfg(pvt, offset, val, __func__)