183 #define dram_intlv_en(pvt, i)		((u8)((pvt->ranges[i].base.lo >> 8) & 0x7))  argument
184 #define dram_rw(pvt, i)			((u8)(pvt->ranges[i].base.lo & 0x3))  argument
185 #define dram_intlv_sel(pvt, i)		((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7))  argument
186 #define dram_dst_node(pvt, i)		((u8)(pvt->ranges[i].lim.lo & 0x7))  argument
189 #define dhar_valid(pvt)			((pvt)->dhar & BIT(0))  argument
190 #define dhar_mem_hoist_valid(pvt)	((pvt)->dhar & BIT(1))  argument
191 #define dhar_base(pvt)			((pvt)->dhar & 0xff000000)  argument
192 #define k8_dhar_offset(pvt)		(((pvt)->dhar & 0x0000ff00) << 16)  argument
195 #define f10_dhar_offset(pvt)		(((pvt)->dhar & 0x0000ff80) << 16)  argument
216 #define csrow_enabled(i, dct, pvt)	((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE)  argument
236 #define dct_sel_baseaddr(pvt)		((pvt)->dct_sel_lo & 0xFFFFF800)  argument
237 #define dct_sel_interleave_addr(pvt)	(((pvt)->dct_sel_lo >> 6) & 0x3)  argument
238 #define dct_high_range_enabled(pvt)	((pvt)->dct_sel_lo & BIT(0))  argument
239 #define dct_interleave_enabled(pvt)	((pvt)->dct_sel_lo & BIT(2))  argument
241 #define dct_ganging_enabled(pvt)	((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4)))  argument
243 #define dct_data_intlv_enabled(pvt)	((pvt)->dct_sel_lo & BIT(5))  argument
244 #define dct_memory_cleared(pvt)		((pvt)->dct_sel_lo & BIT(10))  argument
266 #define online_spare_swap_done(pvt, c)	(((pvt)->online_spare >> (1 + 2 * (c))) & 0x1)  argument
267 #define online_spare_bad_dramcs(pvt, c)	(((pvt)->online_spare >> (4 + 4 * (c))) & 0x7)  argument
377 static inline u64 get_dram_base(struct amd64_pvt *pvt, unsigned i)  in get_dram_base()
387 static inline u64 get_dram_limit(struct amd64_pvt *pvt, unsigned i)  in get_dram_limit()
458 #define amd64_read_dct_pci_cfg(pvt, offset, val) \  argument