Lines Matching +full:fixed +full:- +full:factor +full:- +full:clock
29 Complete the ABR logic of the driver, and added the ABR work-
32 Add the flow control logic to the driver to allow rate-limit VC.
128 #define ATM_DESC(skb) (skb->protocol)
129 #define IA_SKB_STATE(skb) (skb->protocol)
178 #define NRMCODE 5 /* 0 - 7 */
179 #define TRMCODE 3 /* 0 - 7 */
181 #define ATDFCODE 2 /* 0 - 15 */
183 /*---------------------- Packet/Cell Memory ------------------------*/
184 #define TX_PACKET_RAM 0x00000 /* start of Trasnmit Packet memory - 0 */
187 - descriptor 0 unused */
189 #define RX_PACKET_RAM 0x80000 /* start of Receive Packet memory - 512K */
192 - descriptor 0 unused */
246 u_short remainder; /* ABR and UBR fields - last 10 bits*/
259 #define CRC_APPEND 0x40 /* for status field - CRC-32 append */
330 /*--------SAR stuff ---------------------*/
336 /*------------ PCI Memory Space Map, 128K SAR memory ----------------*/
338 #define IPHASE5575_BUS_CONTROL_REG_BASE 0x1000 /* offsets 0x00 - 0x3c */
346 /*------------ Bus interface control registers -----------------*/
351 #define IPHASE5575_MAC2 0x03 /*actual offset 0x0e-reg 0x0c*/
395 /*--------------- Segmentation control registers -----------------*/
480 /*----------------- Reassembly control registers ---------------------*/
556 /*----------------- Front End registers/ DMA control --------------*/
558 eg:- 2 offsets given 800, a00 for rx counter
563 #define IPHASE5575_TX_COUNTER 0x200 /* offset - 0x800 */
564 #define IPHASE5575_RX_COUNTER 0x280 /* offset - 0xa00 */
565 #define IPHASE5575_TX_LIST_ADDR 0x300 /* offset - 0xc00 */
566 #define IPHASE5575_RX_LIST_ADDR 0x380 /* offset - 0xe00 */
568 /*--------------------------- RAM ---------------------------*/
632 /*-------------------- Base Registers --------------------*/
649 u_int filler5[0x17 - 0x06];
651 u_int filler18[0x20 - 0x18];
662 u_int filler2a[0x2C - 0x2A];
666 u_int filler2f[0x30 - 0x2F];
675 u_int filler38[0x40 - 0x38];
678 u_int filler42[0x45 - 0x42];
686 u_int filler4c[0x58 - 0x4c];
690 u_int filler5b[0x5d - 0x5b];
692 u_int filler5e[0x6a - 0x5e];
709 u_int filler7a[0x7c-0x7a];
711 u_int filler7d[0xca-0x7d]; /* pad out to full address space */
714 u_int fillercc[0x100-0xcc]; /* pad out to full address space */
724 u_int filler6[0x08 - 0x06];
726 u_int filler2[0x0c - 0x09];
729 u_int filler3[0x0f - 0x0e];
735 u_int filler14[0x16 - 0x14];
740 u_int filler1a[0x1c - 0x1a];
744 u_int filler1f[0x24 - 0x1f];
757 u_int filler30[0x34 - 0x30];
763 u_int filler39[0x42 - 0x39];
767 u_int filler45[0x84 - 0x45];
770 u_int filler86[0x8c - 0x86];
773 u_int filler8e[0x100-0x8e]; /* pad out to full address space */
811 u32 pcr; /* Peak Cell Rate (24-bit) */
817 u32 mcr; /* Min Cell Rate (24-bit) */
818 u32 icr; /* Initial Cell Rate (24-bit) */
819 u32 tbe; /* Transient Buffer Exposure (24-bit) */
820 u32 frtt; /* Fixed Round Trip Time (24-bit) */
823 bits 31 30 29 28 27-25 24-22 21-19 18-9
824 -----------------------------------------------------------------------------
826 -----------------------------------------------------------------------------
830 cell (3-bit) */
831 u8 trm; /* Time between forward RM cells (3-bit) */
832 u16 adtf; /* ACR Decrease Time Factor (10-bit) */
833 u8 cdf; /* Cutoff Decrease Factor (3-bit) */
834 u8 rif; /* Rate Increment Factor (4-bit) */
835 u8 rdf; /* Rate Decrease Factor (4-bit) */
897 SUNI_MASTER_CLK_MONITOR = 0x010, /* SUNI Master Clock Monitor */
898 SUNI_MASTER_CONTROL = 0x014, /* SUNI Master Clock Monitor */
902 SUNI_RSOP_SECTION_BIP8L = 0x048, /* RSOP Section BIP-8 LSB */
903 SUNI_RSOP_SECTION_BIP8M = 0x04c, /* RSOP Section BIP-8 MSB */
910 SUNI_RLOP_LINE_BIP24L = 0x068, /* RLOP Line BIP-24 LSB */
911 SUNI_RLOP_LINE_BIP24 = 0x06c, /* RLOP Line BIP-24 */
912 SUNI_RLOP_LINE_BIP24M = 0x070, /* RLOP Line BIP-24 MSB */
926 SUNI_RPOP_BIP8L = 0x0e0, /* RPOP Path BIP-8 LSB */
927 SUNI_RPOP_BIP8M = 0x0e4, /* RPOP Path BIP-8 MSB */
967 u32 rsop_bse_count; // section BIP-8 error count
971 u32 rlop_lbe_count; // BIP-24 count
977 u32 rpop_bip_count; // path BIP-8 error count
989 /*-----base pointers into (i)chipSAR+ address space */
1060 #define INPH_IA_DEV(d) ((IADEV *) (d)->dev_data)
1061 #define INPH_IA_VCC(v) ((struct ia_vcc *) (v)->dev_data)
1101 #define MB25_DC_ECEIO 0x20 /* Single/Multi-PHY config select */
1139 /* SUNI_RESERVED1 (0x13 - 0x11) */
1154 /* SUNI_RESERVED2 (0x23 - 0x21) */
1204 /* SUNI_RESERVED3 (0x57 - 0x54) */
1231 /* SUNI_PAD5 (0x7f - 0x71) */
1233 /* SUNI_PAD6 (0xff - 0x80) */
1375 t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS); \
1377 writel(t, iadev->reg+IPHASE5575_EEPROM_ACCESS); \
1389 t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS); \
1391 writel(t, iadev->reg+IPHASE5575_EEPROM_ACCESS); \
1399 * Clock each of the command bits out in the correct order with SK
1410 NVRAM_CLKOUT((c & (1 << (CMD_LEN - 1))) ? 1 : 0); \
1425 * clock the data bit in bitval out to the NOVRAM. The bitval must be
1439 * clock the data bit in and return a 1 or 0, depending on the value
1448 _t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS); \