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49 #define PCI_DIAGNOSTIC_0 0x40 /* 32 bits */
50 #define PCI_SIZE_0 0x44 /* 32 bits */
51 #define PCI_SIZE_1 0x48 /* 32 bits */
52 #define PCI_SIZE_2 0x4c /* 32 bits */
53 #define PCI_SIZE_3 0x50 /* 32 bits */
54 #define PCI_SIZE_4 0x54 /* 32 bits */
55 #define PCI_SIZE_5 0x58 /* 32 bits */
63 #define PCI_CPU_INTERRUPT_PENDING 0x64 /* 32 bits */
67 #define PCI_SYS_INT_PENDING 0x70 /* 32 bits */
72 #define PCI_SYS_INT_TARGET_MASK 0x74 /* 32 bits */
73 #define PCI_SYS_INT_TARGET_MASK_CLEAR 0x78 /* 32 bits */
74 #define PCI_SYS_INT_TARGET_MASK_SET 0x7c /* 32 bits */
85 #define PCI_IOTLB_RAM_INPUT 0x90 /* 32 bits */
86 #define PCI_IOTLB_CAM_INPUT 0x94 /* 32 bits */
87 #define PCI_IOTLB_RAM_OUTPUT 0x98 /* 32 bits */
88 #define PCI_IOTLB_CAM_OUTPUT 0x9c /* 32 bits */
104 #define PCI_CPU_COUNTER_LIMIT_HI 0xac /* 32 bits */
105 #define PCI_CPU_COUNTER_LIMIT_LO 0xb0 /* 32 bits */
106 #define PCI_CPU_COUNTER_LIMIT 0xb4 /* 32 bits */
107 #define PCI_SYS_LIMIT 0xb8 /* 32 bits */
108 #define PCI_SYS_COUNTER 0xbc /* 32 bits */
110 #define PCI_SYS_LIMIT_PSEUDO 0xc0 /* 32 bits */
119 #define PCI_PIO_ERROR_ADDRESS 0xc8 /* 32 bits */
120 #define PCI_IOTLB_ERROR_ADDRESS 0xcc /* 32 bits */