Lines Matching +full:multi +full:- +full:line
11 Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
14 On other systems (such as the SH-3 and 4) where an MMU exists,
50 ---help---
69 line. If unsure, consult your board specifications or just leave it
85 bool "Support 32-bit physical addressing through PMB"
91 32-bits through the SH-4A PMB. If this is not set, legacy
92 29-bit physical addressing will be used.
185 This enables 8kB pages as supported by SH-X2 and later MMUs.
191 This enables 16kB pages on MMU-less SH systems.
197 This enables support for 64kB pages, possible on all SH-4
236 bool "Multi-core scheduler support"
240 Multi-core scheduler support improves the CPU scheduler's decision
241 making when dealing with multi-core CPU chips at a cost of slightly
259 bool "Write-back"
262 bool "Write-through"
264 Selecting this option will configure the caches in write-through
265 mode, as opposed to the default write-back configuration.
267 Since there's sill some aliasing issues on SH-4, this option will